1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "esp_attr.h"
16 #include "soc/cpu.h"
17 #include "soc/soc.h"
18 #include "soc/rtc_periph.h"
19 #include "sdkconfig.h"
20
21 #include "hal/cpu_hal.h"
22 #include "esp_debug_helpers.h"
23 #include "hal/cpu_types.h"
24 #include "hal/mpu_hal.h"
25
26 #include "hal/soc_hal.h"
27 #include "soc/soc_caps.h"
28
29 #include "sdkconfig.h"
30
esp_cpu_stall(int cpu_id)31 void IRAM_ATTR esp_cpu_stall(int cpu_id)
32 {
33 #if SOC_CPU_CORES_NUM > 1
34 soc_hal_stall_core(cpu_id);
35 #endif
36 }
37
esp_cpu_unstall(int cpu_id)38 void IRAM_ATTR esp_cpu_unstall(int cpu_id)
39 {
40 #if SOC_CPU_CORES_NUM > 1
41 soc_hal_unstall_core(cpu_id);
42 #endif
43 }
44
esp_cpu_reset(int cpu_id)45 void IRAM_ATTR esp_cpu_reset(int cpu_id)
46 {
47 soc_hal_reset_core(cpu_id);
48 }
49
esp_set_watchpoint(int no,void * adr,int size,int flags)50 esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
51 {
52 watchpoint_trigger_t trigger;
53
54 switch (flags)
55 {
56 case ESP_WATCHPOINT_LOAD:
57 trigger = WATCHPOINT_TRIGGER_ON_RO;
58 break;
59 case ESP_WATCHPOINT_STORE:
60 trigger = WATCHPOINT_TRIGGER_ON_WO;
61 break;
62 case ESP_WATCHPOINT_ACCESS:
63 trigger = WATCHPOINT_TRIGGER_ON_RW;
64 break;
65 default:
66 return ESP_ERR_INVALID_ARG;
67 }
68
69 cpu_hal_set_watchpoint(no, adr, size, trigger);
70 return ESP_OK;
71 }
72
esp_clear_watchpoint(int no)73 void IRAM_ATTR esp_clear_watchpoint(int no)
74 {
75 cpu_hal_clear_watchpoint(no);
76 }
77
esp_cpu_in_ocd_debug_mode(void)78 bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
79 {
80 #if CONFIG_ESP32_DEBUG_OCDAWARE || \
81 CONFIG_ESP32S2_DEBUG_OCDAWARE || \
82 CONFIG_ESP32S3_DEBUG_OCDAWARE || \
83 CONFIG_ESP32C3_DEBUG_OCDAWARE
84 return cpu_ll_is_debugger_attached();
85 #else
86 return false; // Always return false if "OCD aware" is disabled
87 #endif
88 }
89
esp_set_breakpoint_if_jtag(void * fn)90 void IRAM_ATTR esp_set_breakpoint_if_jtag(void *fn)
91 {
92 if (esp_cpu_in_ocd_debug_mode()) {
93 cpu_hal_set_breakpoint(0, fn);
94 }
95 }
96
97 #if __XTENSA__
98
esp_cpu_configure_region_protection(void)99 void esp_cpu_configure_region_protection(void)
100 {
101 /* Note: currently this is configured the same on all Xtensa targets
102 *
103 * Both chips have the address space divided into 8 regions, 512MB each.
104 */
105 const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
106 for (size_t i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
107 mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
108 }
109
110 mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
111 }
112
113 #endif
114
