1 /*
2 * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stddef.h>
8 #include <stdlib.h>
9 #include <stdio.h>
10 #include <string.h>
11
12 #include "esp_random.h"
13 #include "esp_heap_caps.h"
14 #include "esp_heap_caps_init.h"
15 #include <esp_mac.h>
16
17 #include "sdkconfig.h"
18
19 #if CONFIG_BT_NIMBLE_ENABLED
20 #include "nimble/nimble_port.h"
21 #endif // CONFIG_BT_NIMBLE_ENABLED
22
23 #include "nimble/nimble_port_freertos.h"
24
25 #ifdef ESP_PLATFORM
26 #include "esp_log.h"
27 #endif
28
29 #if CONFIG_SW_COEXIST_ENABLE
30 #include "private/esp_coexist_internal.h"
31 #endif
32
33 #include "nimble/nimble_npl_os.h"
34 #include "esp_hci_transport.h"
35 #include "os/endian.h"
36
37 #include "esp_bt.h"
38 #include "esp_intr_alloc.h"
39 #include "esp_sleep.h"
40 #include "esp_pm.h"
41 #include "esp_phy_init.h"
42 #include "soc/syscon_reg.h"
43 #include "soc/modem_clkrst_reg.h"
44 #include "esp_private/periph_ctrl.h"
45 #include "bt_osi_mem.h"
46
47 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
48 #include "esp_private/sleep_modem.h"
49 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
50 #include "esp_private/esp_modem_clock.h"
51
52 #include "freertos/FreeRTOS.h"
53 #include "freertos/task.h"
54
55 #include "esp_private/periph_ctrl.h"
56 #include "esp_private/esp_clk.h"
57 #include "esp_sleep.h"
58
59 #include "soc/syscon_reg.h"
60 #include "soc/dport_access.h"
61
62 #include "hal/efuse_ll.h"
63 #include "soc/rtc.h"
64
65 /* Macro definition
66 ************************************************************************
67 */
68
69 #define NIMBLE_PORT_LOG_TAG "BLE_INIT"
70 #define OSI_COEX_VERSION 0x00010006
71 #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
72
73 #define EXT_FUNC_VERSION 0x20221122
74 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
75
76 #define BT_ASSERT_PRINT ets_printf
77 /* Types definition
78 ************************************************************************
79 */
80 struct osi_coex_funcs_t {
81 uint32_t _magic;
82 uint32_t _version;
83 void (* _coex_wifi_sleep_set)(bool sleep);
84 int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high);
85 void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
86 void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
87 };
88
89 struct ext_funcs_t {
90 uint32_t ext_version;
91 int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle);
92 int (*_esp_intr_free)(void **ret_handle);
93 void *(* _malloc)(size_t size);
94 void (*_free)(void *p);
95 void (*_rsv1)(int);
96 int (*_rsv2)(int, int (*)(void *arg), int (*)(void *arg, uint8_t byte), int (*)(void *arg, uint8_t byte), void *);
97 int (*_rsv3)(int, int32_t, uint8_t, uint8_t, int, int);
98 int (*_rsv4)(int);
99 void (*_rsv5)(int, uint8_t);
100 int (*_rsv6)(int, void *);
101 int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
102 void (* _task_delete)(void *task_handle);
103 void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
104 uint32_t (* _os_random)(void);
105 int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
106 int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey);
107 void (* _esp_reset_rpa_moudle)(void);
108 void (* _esp_bt_track_pll_cap)(void);
109 uint32_t magic;
110 };
111
112 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
113 typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
114 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
115
116 /* External functions or variables
117 ************************************************************************
118 */
119 extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
120 extern int ble_controller_init(esp_bt_controller_config_t *cfg);
121 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
122 extern int ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
123 extern int ble_log_deinit_async(void);
124 extern void ble_log_async_output_dump_all(bool output);
125 extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms);
126 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
127 extern int ble_controller_deinit(void);
128 extern int ble_controller_enable(uint8_t mode);
129 extern int ble_controller_disable(void);
130 extern int esp_register_ext_funcs (struct ext_funcs_t *);
131 extern void esp_unregister_ext_funcs (void);
132 extern int esp_ble_ll_set_public_addr(const uint8_t *addr);
133 extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func);
134 extern void esp_unregister_npl_funcs (void);
135 extern void npl_freertos_mempool_deinit(void);
136 extern void bt_bb_v2_init_cmplx(uint8_t i);
137 extern int os_msys_buf_alloc(void);
138 extern uint32_t r_os_cputime_get32(void);
139 extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks);
140 extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled);
141 extern void r_ble_rtc_wake_up_state_clr(void);
142 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
143 extern void esp_ble_set_wakeup_overhead(uint32_t overhead);
144 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
145 extern int os_msys_init(void);
146 extern void os_msys_buf_free(void);
147 extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
148 const uint8_t *peer_pub_key_y,
149 const uint8_t *our_priv_key, uint8_t *out_dhkey);
150 extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv);
151 extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level);
152 extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
153 extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info);
154 extern void bt_track_pll_cap(void);
155 extern char *ble_controller_get_compile_version(void);
156 extern const char *r_ble_controller_get_rom_compile_version(void);
157 #if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
158 extern void ble_ll_supported_features_init(void);
159 #endif //CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
160
161 #if CONFIG_BT_RELEASE_IRAM
162 extern uint32_t _iram_bt_text_start;
163 extern uint32_t _bss_bt_end;
164 #endif
165
166 extern uint32_t _bt_bss_start;
167 extern uint32_t _bt_bss_end;
168 extern uint32_t _bt_controller_bss_start;
169 extern uint32_t _bt_controller_bss_end;
170 extern uint32_t _bt_data_start;
171 extern uint32_t _bt_data_end;
172 extern uint32_t _bt_controller_data_start;
173 extern uint32_t _bt_controller_data_end;
174
175 /* Local Function Declaration
176 *********************************************************************
177 */
178 static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
179 static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
180 static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
181 static void task_delete_wrapper(void *task_handle);
182 static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
183 void *arg, void **ret_handle_in);
184 static int esp_intr_free_wrapper(void **ret_handle);
185 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
186 static uint32_t osi_random_wrapper(void);
187 static void esp_reset_rpa_moudle(void);
188 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
189 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
190 const uint8_t *our_priv_key, uint8_t *out_dhkey);
191 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
192 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
193 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
194 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
195 #endif // #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
196 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
197 /* Local variable definition
198 ***************************************************************************
199 */
200 #if (CONFIG_ESP32C2_REV_MIN_FULL < 200) && (!CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
201 void *g_ble_lll_rfmgmt_env_p;
202 #endif
203 /* Static variable declare */
204 static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
205 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
206 const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
207 enum log_out_mode {
208 LOG_DUMP_MEMORY,
209 LOG_ASYNC_OUT,
210 LOG_STORAGE_TO_FLASH,
211 };
212
213 bool log_is_inited = false;
214 #if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
215 uint8_t log_output_mode = LOG_DUMP_MEMORY;
216 #else
217 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
218 uint8_t log_output_mode = LOG_STORAGE_TO_FLASH;
219 #else
220 uint8_t log_output_mode = LOG_ASYNC_OUT;
221 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
222 #endif // CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
223
esp_bt_log_output_mode_set(uint8_t output_mode)224 void esp_bt_log_output_mode_set(uint8_t output_mode)
225 {
226 log_output_mode = output_mode;
227 }
228
esp_bt_log_output_mode_get(void)229 uint8_t esp_bt_log_output_mode_get(void)
230 {
231 return log_output_mode;
232 }
233
esp_bt_controller_log_init(uint8_t log_output_mode)234 esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
235 {
236 esp_err_t ret = ESP_OK;
237 interface_func_t bt_controller_log_interface;
238 bt_controller_log_interface = esp_bt_controller_log_interface;
239 bool task_create;
240 uint8_t buffers = 0;
241
242 if (log_is_inited) {
243 return ret;
244 }
245
246 #if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
247 buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
248 #endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
249 #if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
250 buffers |= ESP_BLE_LOG_BUF_HCI;
251 #endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
252
253 switch (log_output_mode) {
254 case LOG_DUMP_MEMORY:
255 task_create = false;
256 break;
257 case LOG_ASYNC_OUT:
258 case LOG_STORAGE_TO_FLASH:
259 task_create = true;
260 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
261 if (log_output_mode == LOG_STORAGE_TO_FLASH) {
262 esp_bt_ctrl_log_partition_get_and_erase_first_block();
263 }
264 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
265 break;
266 default:
267 assert(0);
268 }
269
270 ret = ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
271 if (ret == ESP_OK) {
272 log_is_inited = true;
273 }
274
275 return ret;
276 }
277
esp_bt_ontroller_log_deinit(void)278 void esp_bt_ontroller_log_deinit(void)
279 {
280 ble_log_deinit_async();
281 log_is_inited = false;
282 }
283
284 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
285 #include "esp_partition.h"
286 #include "hal/wdt_hal.h"
287
288 #define MAX_STORAGE_SIZE (CONFIG_BT_LE_CONTROLLER_LOG_PARTITION_SIZE)
289 #define BLOCK_SIZE (4096)
290 #define THRESHOLD (3072)
291 #define PARTITION_NAME "bt_ctrl_log"
292
293 static const esp_partition_t *log_partition;
294 static uint32_t write_index = 0;
295 static uint32_t next_erase_index = BLOCK_SIZE;
296 static bool block_erased = false;
297 static bool stop_write = false;
298 static bool is_filled = false;
299
esp_bt_ctrl_log_partition_get_and_erase_first_block(void)300 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void)
301 {
302 log_partition = NULL;
303 assert(MAX_STORAGE_SIZE % BLOCK_SIZE == 0);
304 // Find the partition map in the partition table
305 log_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, PARTITION_NAME);
306 assert(log_partition != NULL);
307 // Prepare data to be read later using the mapped address
308 ESP_ERROR_CHECK(esp_partition_erase_range(log_partition, 0, BLOCK_SIZE));
309 write_index = 0;
310 next_erase_index = BLOCK_SIZE;
311 block_erased = false;
312 is_filled = false;
313 stop_write = false;
314 }
315
esp_bt_controller_log_storage(uint32_t len,const uint8_t * addr,bool end)316 static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end)
317 {
318 if (len > MAX_STORAGE_SIZE) {
319 return -1;
320 }
321
322 if (stop_write) {
323 return 0;
324 }
325
326 assert(log_partition != NULL);
327 if (((write_index) % BLOCK_SIZE) >= THRESHOLD && !block_erased) {
328 // esp_rom_printf("Ers nxt: %d,%d\n", next_erase_index, write_index);
329 esp_partition_erase_range(log_partition, next_erase_index, BLOCK_SIZE);
330 next_erase_index = (next_erase_index + BLOCK_SIZE) % MAX_STORAGE_SIZE;
331 block_erased = true;
332 }
333
334 if (((write_index + len) / BLOCK_SIZE) > (write_index / BLOCK_SIZE)) {
335 block_erased = false;
336 }
337
338 if (write_index + len <= MAX_STORAGE_SIZE) {
339 esp_partition_write(log_partition, write_index, addr, len);
340 write_index = (write_index + len) % MAX_STORAGE_SIZE;
341 } else {
342 uint32_t first_part_len = MAX_STORAGE_SIZE - write_index;
343 esp_partition_write(log_partition, write_index, addr, first_part_len);
344 esp_partition_write(log_partition, 0, addr + first_part_len, len - first_part_len);
345 write_index = len - first_part_len;
346 is_filled = true;
347 // esp_rom_printf("old idx: %d,%d\n",next_erase_index, write_index);
348 }
349
350 return 0;
351 }
352
esp_bt_read_ctrl_log_from_flash(bool output)353 void esp_bt_read_ctrl_log_from_flash(bool output)
354 {
355 esp_partition_mmap_handle_t mmap_handle;
356 uint32_t read_index;
357 const void *mapped_ptr;
358 const uint8_t *buffer;
359 uint32_t print_len;
360 uint32_t max_print_len;
361 esp_err_t err;
362
363 print_len = 0;
364 max_print_len = 4096;
365 err = esp_partition_mmap(log_partition, 0, MAX_STORAGE_SIZE, ESP_PARTITION_MMAP_DATA, &mapped_ptr, &mmap_handle);
366 if (err != ESP_OK) {
367 ESP_LOGE("FLASH", "Mmap failed: %s", esp_err_to_name(err));
368 return;
369 }
370
371 portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
372 portENTER_CRITICAL_SAFE(&spinlock);
373 esp_panic_handler_reconfigure_wdts(5000);
374 ble_log_async_output_dump_all(true);
375 stop_write = true;
376 esp_bt_ontroller_log_deinit();
377 portEXIT_CRITICAL_SAFE(&spinlock);
378
379 buffer = (const uint8_t *)mapped_ptr;
380 if (is_filled) {
381 read_index = next_erase_index;
382 } else {
383 read_index = 0;
384 }
385
386 esp_rom_printf("\r\nREAD_CHECK:%ld,%ld,%d\r\n",read_index, write_index, is_filled);
387 esp_rom_printf("\r\n[DUMP_START:");
388 while (read_index != write_index) {
389 esp_rom_printf("%02x ", buffer[read_index]);
390 if (print_len > max_print_len) {
391 vTaskDelay(2);
392 print_len = 0;
393 }
394
395 print_len++;
396 read_index = (read_index + 1) % MAX_STORAGE_SIZE;
397 }
398 esp_rom_printf(":DUMP_END]\r\n");
399 esp_partition_munmap(mmap_handle);
400 err = esp_bt_controller_log_init(log_output_mode);
401 assert(err == ESP_OK);
402
403 }
404 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
esp_bt_controller_log_interface(uint32_t len,const uint8_t * addr,bool end)405 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
406 {
407 if (log_output_mode == LOG_STORAGE_TO_FLASH) {
408 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
409 esp_bt_controller_log_storage(len, addr, end);
410 #endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
411 } else {
412 for (int i = 0; i < len; i++) {
413 esp_rom_printf("%02x ", addr[i]);
414 }
415
416 if (end) {
417 esp_rom_printf("\n");
418 }
419 }
420 }
421
esp_ble_controller_log_dump_all(bool output)422 void esp_ble_controller_log_dump_all(bool output)
423 {
424 if (log_output_mode == LOG_STORAGE_TO_FLASH) {
425 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
426 esp_bt_read_ctrl_log_from_flash(output);
427 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
428 } else {
429 portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
430 portENTER_CRITICAL_SAFE(&spinlock);
431 esp_panic_handler_reconfigure_wdts(5000);
432 BT_ASSERT_PRINT("\r\n[DUMP_START:");
433 ble_log_async_output_dump_all(output);
434 BT_ASSERT_PRINT(":DUMP_END]\r\n");
435 portEXIT_CRITICAL_SAFE(&spinlock);
436 }
437 }
438 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
439
440 /* This variable tells if BLE is running */
441 static bool s_ble_active = false;
442 #ifdef CONFIG_PM_ENABLE
443 static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
444 #define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
445 #endif // CONFIG_PM_ENABLE
446 static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
447
448 #define BLE_RTC_DELAY_US (1800)
449
450 #define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA)
malloc_ble_controller_mem(size_t size)451 void *malloc_ble_controller_mem(size_t size)
452 {
453 return heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
454 }
455
get_ble_controller_free_heap_size(void)456 uint32_t get_ble_controller_free_heap_size(void)
457 {
458 return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
459 }
460
461 static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = {
462 ._magic = OSI_COEX_MAGIC_VALUE,
463 ._version = OSI_COEX_VERSION,
464 ._coex_wifi_sleep_set = NULL,
465 ._coex_core_ble_conn_dyn_prio_get = NULL,
466 ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
467 ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
468 };
469
470 struct ext_funcs_t ext_funcs_ro = {
471 .ext_version = EXT_FUNC_VERSION,
472 ._esp_intr_alloc = esp_intr_alloc_wrapper,
473 ._esp_intr_free = esp_intr_free_wrapper,
474 ._malloc = bt_osi_mem_malloc_internal,
475 ._free = bt_osi_mem_free,
476 ._task_create = task_create_wrapper,
477 ._task_delete = task_delete_wrapper,
478 ._osi_assert = osi_assert_wrapper,
479 ._os_random = osi_random_wrapper,
480 ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
481 ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
482 ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
483 ._esp_bt_track_pll_cap = NULL,
484 .magic = EXT_FUNC_MAGIC_VALUE,
485 };
486
esp_reset_rpa_moudle(void)487 static void IRAM_ATTR esp_reset_rpa_moudle(void)
488 {
489 DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
490 DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
491 }
492
osi_assert_wrapper(const uint32_t ln,const char * fn,uint32_t param1,uint32_t param2)493 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
494 uint32_t param1, uint32_t param2)
495 {
496 BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2);
497 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
498 esp_ble_controller_log_dump_all(true);
499 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
500 assert(0);
501 }
502
osi_random_wrapper(void)503 static uint32_t IRAM_ATTR osi_random_wrapper(void)
504 {
505 return esp_random();
506 }
507
coex_schm_status_bit_set_wrapper(uint32_t type,uint32_t status)508 static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
509 {
510 #if CONFIG_SW_COEXIST_ENABLE
511 coex_schm_status_bit_set(type, status);
512 #endif // CONFIG_SW_COEXIST_ENABLE
513 }
514
coex_schm_status_bit_clear_wrapper(uint32_t type,uint32_t status)515 static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
516 {
517 #if CONFIG_SW_COEXIST_ENABLE
518 coex_schm_status_bit_clear(type, status);
519 #endif // CONFIG_SW_COEXIST_ENABLE
520 }
521
task_create_wrapper(void * task_func,const char * name,uint32_t stack_depth,void * param,uint32_t prio,void * task_handle,uint32_t core_id)522 static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id)
523 {
524 return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
525 }
526
task_delete_wrapper(void * task_handle)527 static void task_delete_wrapper(void *task_handle)
528 {
529 vTaskDelete(task_handle);
530 }
531
esp_ecc_gen_key_pair(uint8_t * pub,uint8_t * priv)532 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
533 {
534 int rc = -1;
535 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
536 rc = ble_sm_alg_gen_key_pair(pub, priv);
537 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
538 return rc;
539 }
540
esp_ecc_gen_dh_key(const uint8_t * peer_pub_key_x,const uint8_t * peer_pub_key_y,const uint8_t * our_priv_key,uint8_t * out_dhkey)541 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
542 const uint8_t *our_priv_key, uint8_t *out_dhkey)
543 {
544 int rc = -1;
545 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
546 rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
547 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
548 return rc;
549 }
550
esp_intr_alloc_wrapper(int source,int flags,intr_handler_t handler,void * arg,void ** ret_handle_in)551 static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in)
552 {
553 #if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
554 int rc = esp_intr_alloc(source, flags, handler, arg, (intr_handle_t *)ret_handle_in);
555 #else
556 int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in);
557 #endif
558
559 return rc;
560 }
561
esp_intr_free_wrapper(void ** ret_handle)562 static int esp_intr_free_wrapper(void **ret_handle)
563 {
564 int rc = 0;
565 rc = esp_intr_free((intr_handle_t) * ret_handle);
566 *ret_handle = NULL;
567 return rc;
568 }
569
570 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
sleep_modem_light_sleep_overhead_set(uint32_t overhead)571 void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
572 {
573 esp_ble_set_wakeup_overhead(overhead);
574 }
575 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
576
esp_bt_get_lpclk_src(void)577 modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
578 {
579 return s_bt_lpclk_src;
580 }
581
esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)582 void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
583 {
584 if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
585 return;
586 }
587
588 s_bt_lpclk_src = clk_src;
589 }
590
controller_sleep_cb(uint32_t enable_tick,void * arg)591 IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
592 {
593 if (!s_ble_active) {
594 return;
595 }
596 #ifdef CONFIG_PM_ENABLE
597 r_ble_rtc_wake_up_state_clr();
598 esp_pm_lock_release(s_pm_lock);
599 #endif // CONFIG_PM_ENABLE
600 esp_phy_disable(PHY_MODEM_BT);
601 s_ble_active = false;
602 }
603
controller_wakeup_cb(void * arg)604 IRAM_ATTR void controller_wakeup_cb(void *arg)
605 {
606 if (s_ble_active) {
607 return;
608 }
609 esp_phy_enable(PHY_MODEM_BT);
610 // need to check if need to call pm lock here
611 #ifdef CONFIG_PM_ENABLE
612 esp_pm_lock_acquire(s_pm_lock);
613 #endif //CONFIG_PM_ENABLE
614 s_ble_active = true;
615 }
616
controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src)617 esp_err_t controller_sleep_init(modem_clock_lpclk_src_t slow_clk_src)
618 {
619 esp_err_t rc = 0;
620 #ifdef CONFIG_BT_LE_SLEEP_ENABLE
621 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled\n");
622 r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
623
624 #ifdef CONFIG_PM_ENABLE
625 if (slow_clk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
626 esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
627 } else {
628 esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
629 }
630 #endif // CONFIG_PM_ENABLE
631
632 #endif // CONFIG_BT_LE_SLEEP_ENABLE
633
634 // enable light sleep
635 #ifdef CONFIG_PM_ENABLE
636 rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock);
637 if (rc != ESP_OK) {
638 goto error;
639 }
640 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
641 esp_sleep_enable_bt_wakeup();
642 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
643
644 rc = esp_pm_register_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
645 if (rc != ESP_OK) {
646 goto error;
647 }
648 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
649 return rc;
650
651 error:
652 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
653 esp_sleep_disable_bt_wakeup();
654 esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
655 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
656 /*lock should release first and then delete*/
657 if (s_pm_lock != NULL) {
658 esp_pm_lock_delete(s_pm_lock);
659 s_pm_lock = NULL;
660 }
661 #endif //CONFIG_PM_ENABLE
662 return rc;
663 }
664
controller_sleep_deinit(void)665 void controller_sleep_deinit(void)
666 {
667 #ifdef CONFIG_FREERTOS_USE_TICKLESS_IDLE
668 r_ble_rtc_wake_up_state_clr();
669 esp_sleep_disable_bt_wakeup();
670 esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
671 esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
672 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
673 #ifdef CONFIG_PM_ENABLE
674 /*lock should release first and then delete*/
675 esp_pm_lock_delete(s_pm_lock);
676 s_pm_lock = NULL;
677 #endif //CONFIG_PM_ENABLE
678 }
679
esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)680 static void esp_bt_rtc_slow_clk_select(modem_clock_lpclk_src_t slow_clk_src)
681 {
682 /* Select slow clock source for BT momdule */
683 switch (slow_clk_src) {
684 case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
685 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
686 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
687 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
688 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
689 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
690 #ifdef CONFIG_XTAL_FREQ_26
691 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
692 #else
693 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
694 #endif // CONFIG_XTAL_FREQ_26
695 break;
696 case MODEM_CLOCK_LPCLK_SRC_EXT32K:
697 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
698 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
699 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
700 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
701 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
702 SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 0, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
703 break;
704 default:
705 ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported slow clock");
706 assert(0);
707 break;
708 }
709 SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 1, MODEM_CLKRST_ETM_CLK_ACTIVE_S);
710 SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
711 }
712
ble_rtc_clk_init(esp_bt_controller_config_t * cfg)713 static modem_clock_lpclk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
714 {
715 if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
716 #if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
717 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
718 #else
719 if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
720 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
721 } else {
722 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
723 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
724 }
725 #endif // CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
726 }
727
728 if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
729 cfg->rtc_freq = 32768;
730 } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
731 #ifdef CONFIG_XTAL_FREQ_26
732 cfg->rtc_freq = 40000;
733 #else
734 cfg->rtc_freq = 32000;
735 #endif // CONFIG_XTAL_FREQ_26
736 }
737 esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
738 return s_bt_lpclk_src;
739 }
740
esp_bt_controller_init(esp_bt_controller_config_t * cfg)741 esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
742 {
743 esp_err_t ret = ESP_OK;
744 ble_npl_count_info_t npl_info;
745 modem_clock_lpclk_src_t rtc_clk_src;
746 uint8_t hci_transport_mode;
747
748 memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
749 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
750 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
751 return ESP_ERR_INVALID_STATE;
752 }
753
754 if (!cfg) {
755 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL");
756 return ESP_ERR_INVALID_ARG;
757 }
758
759 rtc_clk_src = ble_rtc_clk_init(cfg);
760
761 ret = esp_register_ext_funcs(&ext_funcs_ro);
762 if (ret != ESP_OK) {
763 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed");
764 return ret;
765 }
766
767 /* If we place the ble code into flash, don't need to initialize ROM. */
768 #if !CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
769 #if DEFAULT_BT_LE_50_FEATURE_SUPPORT || DEFAULT_BT_LE_ROLE_CENTROL || DEFAULT_BT_LE_ROLE_OBSERVER
770 extern int esp_ble_rom_func_ptr_init_all(void);
771 esp_ble_rom_func_ptr_init_all();
772 #else
773 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Init only legacy adv and slave function");
774 extern int esp_ble_rom_func_ptr_init_legacy_adv_and_slave(void);
775 esp_ble_rom_func_ptr_init_legacy_adv_and_slave();
776 #endif
777 #endif //!CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
778
779 /* Initialize the function pointers for OS porting */
780 npl_freertos_funcs_init();
781 struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
782 if (!p_npl_funcs) {
783 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed");
784 return ESP_ERR_INVALID_ARG;
785 }
786
787 ret = esp_register_npl_funcs(p_npl_funcs);
788 if (ret != ESP_OK) {
789 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed");
790 goto free_mem;
791 }
792
793 ble_get_npl_element_info(cfg, &npl_info);
794 npl_freertos_set_controller_npl_info(&npl_info);
795 if (npl_freertos_mempool_init() != 0) {
796 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed");
797 ret = ESP_ERR_INVALID_ARG;
798 goto free_mem;
799 }
800
801 /* Initialize the global memory pool */
802 ret = os_msys_buf_alloc();
803 if (ret != ESP_OK) {
804 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "os msys alloc failed");
805 goto free_mem;
806 }
807
808 os_msys_init();
809 #if CONFIG_BT_NIMBLE_ENABLED
810 // ble_npl_eventq_init() need to use npl function in rom and must be called after esp_bt_controller_init()
811 /* Initialize default event queue */
812 ble_npl_eventq_init(nimble_port_get_dflt_eventq());
813 #endif
814 esp_phy_modem_init();
815 periph_module_enable(PERIPH_BT_MODULE);
816 periph_module_reset(PERIPH_BT_MODULE);
817
818 if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
819 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
820 ret = ESP_ERR_INVALID_ARG;
821 goto modem_deint;
822 }
823
824 #if CONFIG_SW_COEXIST_ENABLE
825 coex_init();
826 #endif
827
828 #if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
829 ble_ll_supported_features_init();
830 #endif //CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
831
832 ret = ble_controller_init(cfg);
833 if (ret != ESP_OK) {
834 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
835 goto modem_deint;
836 }
837
838 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
839 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble rom commit:[%s]", r_ble_controller_get_rom_compile_version());
840
841 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
842 ret = esp_bt_controller_log_init(log_output_mode);
843 if (ret != ESP_OK) {
844 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
845 goto controller_init_err;
846 }
847 #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
848
849 ret = controller_sleep_init(rtc_clk_src);
850 if (ret != ESP_OK) {
851 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
852 goto free_controller;
853 }
854
855 uint8_t mac[6];
856 ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
857
858 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
859 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
860
861 swap_in_place(mac, 6);
862
863 esp_ble_ll_set_public_addr(mac);
864
865 ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
866
867 #if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
868 hci_transport_mode = HCI_TRANSPORT_VHCI;
869 #elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
870 hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
871 #endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
872 ret = hci_transport_init(hci_transport_mode);
873 if (ret) {
874 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
875 goto free_controller;
876 }
877 return ESP_OK;
878 free_controller:
879 hci_transport_deinit();
880 controller_sleep_deinit();
881 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
882 controller_init_err:
883 esp_bt_ontroller_log_deinit();
884 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
885 ble_controller_deinit();
886 modem_deint:
887 esp_phy_modem_deinit();
888 periph_module_disable(PERIPH_BT_MODULE);
889 #if CONFIG_BT_NIMBLE_ENABLED
890 ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
891 #endif // CONFIG_BT_NIMBLE_ENABLED
892 free_mem:
893 os_msys_buf_free();
894 npl_freertos_mempool_deinit();
895 esp_unregister_npl_funcs();
896 npl_freertos_funcs_deinit();
897 esp_unregister_ext_funcs();
898 return ret;
899 }
900
esp_bt_controller_deinit(void)901 esp_err_t esp_bt_controller_deinit(void)
902 {
903 if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) || (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) {
904 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
905 return ESP_FAIL;
906 }
907
908 hci_transport_deinit();
909 controller_sleep_deinit();
910
911 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
912 esp_bt_ontroller_log_deinit();
913 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
914 ble_controller_deinit();
915
916 periph_module_disable(PERIPH_BT_MODULE);
917
918 #if CONFIG_BT_NIMBLE_ENABLED
919 /* De-initialize default event queue */
920 ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
921 #endif
922 os_msys_buf_free();
923
924 esp_unregister_npl_funcs();
925
926 esp_unregister_ext_funcs();
927
928 /* De-initialize npl functions */
929 npl_freertos_funcs_deinit();
930
931 npl_freertos_mempool_deinit();
932
933 esp_phy_modem_deinit();
934
935 ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
936
937 return ESP_OK;
938 }
939
esp_bt_controller_enable(esp_bt_mode_t mode)940 esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode)
941 {
942 esp_err_t ret = ESP_OK;
943
944 if (mode != ESP_BT_MODE_BLE) {
945 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode");
946 return ESP_FAIL;
947 }
948 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
949 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
950 return ESP_FAIL;
951 }
952 if (!s_ble_active) {
953 #if CONFIG_PM_ENABLE
954 esp_pm_lock_acquire(s_pm_lock);
955 #endif // CONFIG_PM_ENABLE
956 // init phy
957 esp_phy_enable(PHY_MODEM_BT);
958 s_ble_active = true;
959 }
960 // init bb
961 bt_bb_v2_init_cmplx(1);
962
963 #if CONFIG_SW_COEXIST_ENABLE
964 coex_enable();
965 #endif
966 if (ble_controller_enable(mode) != 0) {
967 ret = ESP_FAIL;
968 goto error;
969 }
970
971 ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
972 return ESP_OK;
973
974 error:
975 #if CONFIG_SW_COEXIST_ENABLE
976 coex_disable();
977 #endif
978 if (s_ble_active) {
979 esp_phy_disable(PHY_MODEM_BT);
980 #if CONFIG_PM_ENABLE
981 esp_pm_lock_release(s_pm_lock);
982 #endif // CONFIG_PM_ENABLE
983 s_ble_active = false;
984 }
985 return ret;
986 }
987
esp_bt_controller_disable(void)988 esp_err_t esp_bt_controller_disable(void)
989 {
990 if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) {
991 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
992 return ESP_FAIL;
993 }
994 if (ble_controller_disable() != 0) {
995 return ESP_FAIL;
996 }
997
998 if (s_ble_active) {
999 esp_phy_disable(PHY_MODEM_BT);
1000 #if CONFIG_PM_ENABLE
1001 esp_pm_lock_release(s_pm_lock);
1002 #endif // CONFIG_PM_ENABLE
1003 s_ble_active = false;
1004 }
1005 #if CONFIG_SW_COEXIST_ENABLE
1006 coex_disable();
1007 #endif
1008 ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
1009 return ESP_OK;
1010 }
1011
esp_bt_controller_mem_release(esp_bt_mode_t mode)1012 esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode)
1013 {
1014 ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__);
1015 return ESP_OK;
1016 }
1017
try_heap_caps_add_region(intptr_t start,intptr_t end)1018 static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end)
1019 {
1020 int ret = heap_caps_add_region(start, end);
1021 /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is
1022 * is too small to fit a heap. This cannot be termed as a fatal error and hence
1023 * we replace it by ESP_OK
1024 */
1025 if (ret == ESP_ERR_INVALID_SIZE) {
1026 return ESP_OK;
1027 }
1028 return ret;
1029 }
1030
1031 typedef struct {
1032 intptr_t start;
1033 intptr_t end;
1034 const char* name;
1035 } bt_area_t;
1036
esp_bt_mem_release_area(const bt_area_t * area)1037 static esp_err_t esp_bt_mem_release_area(const bt_area_t *area)
1038 {
1039 esp_err_t ret = ESP_OK;
1040 intptr_t mem_start = area->start;
1041 intptr_t mem_end = area->end;
1042 if (mem_start != mem_end) {
1043 ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release %s [0x%08x] - [0x%08x], len %d", area->name, mem_start, mem_end, mem_end - mem_start);
1044 ret = try_heap_caps_add_region(mem_start, mem_end);
1045 }
1046 return ret;
1047 }
1048
1049 #ifndef CONFIG_BT_RELEASE_IRAM
esp_bt_mem_release_areas(const bt_area_t * area1,const bt_area_t * area2)1050 static esp_err_t esp_bt_mem_release_areas(const bt_area_t *area1, const bt_area_t *area2)
1051 {
1052 esp_err_t ret = ESP_OK;
1053
1054 if(area1->end == area2->start) {
1055 bt_area_t merged_area = {
1056 .start = area1->start,
1057 .end = area2->end,
1058 .name = area1->name
1059 };
1060 ret = esp_bt_mem_release_area(&merged_area);
1061 } else {
1062 esp_bt_mem_release_area(area1);
1063 ret = esp_bt_mem_release_area(area2);
1064 }
1065
1066 return ret;
1067 }
1068 #endif
1069
esp_bt_mem_release(esp_bt_mode_t mode)1070 esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
1071 {
1072 esp_err_t ret = ESP_OK;
1073
1074 #if CONFIG_BT_RELEASE_IRAM && CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT
1075 /* Release Bluetooth text section and merge Bluetooth data, bss & text into a large free heap
1076 * region when esp_bt_mem_release is called, total saving ~21kB or more of IRAM. ESP32-C2 has
1077 * only 3 configurable PMP entries available, rest of them are hard-coded. We cannot split the
1078 * memory into 3 different regions (IRAM, BLE-IRAM, DRAM). So `ESP_SYSTEM_PMP_IDRAM_SPLIT` needs
1079 * to be disabled.
1080 */
1081 #error "ESP_SYSTEM_PMP_IDRAM_SPLIT should be disabled to allow BT to be released"
1082 #endif // CONFIG_BT_RELEASE_IRAM && CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT
1083
1084 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
1085 return ESP_ERR_INVALID_STATE;
1086 }
1087
1088 if ((mode & ESP_BT_MODE_BLE) == 0) {
1089 return ret;
1090 }
1091
1092 #if CONFIG_BT_RELEASE_IRAM
1093 bt_area_t merged_region = {
1094 .start = (intptr_t)MAP_IRAM_TO_DRAM((intptr_t)&_iram_bt_text_start),
1095 .end = (intptr_t)&_bss_bt_end,
1096 .name = "BT Text, BSS and Data"
1097 };
1098 ret = esp_bt_mem_release_area(&merged_region);
1099 #else
1100 bt_area_t bss = {
1101 .start = (intptr_t)&_bt_bss_start,
1102 .end = (intptr_t)&_bt_bss_end,
1103 .name = "BT BSS",
1104 };
1105 bt_area_t cont_bss = {
1106 .start = (intptr_t)&_bt_controller_bss_start,
1107 .end = (intptr_t)&_bt_controller_bss_end,
1108 .name = "BT Controller BSS",
1109 };
1110 bt_area_t data = {
1111 .start = (intptr_t)&_bt_data_start,
1112 .end = (intptr_t)&_bt_data_end,
1113 .name = "BT Data",
1114 };
1115 bt_area_t cont_data = {
1116 .start = (intptr_t)&_bt_controller_data_start,
1117 .end = (intptr_t)&_bt_controller_data_end,
1118 .name = "BT Controller Data"
1119 };
1120
1121 /* Start by freeing Bluetooth BSS section */
1122 if (ret == ESP_OK) {
1123 ret = esp_bt_mem_release_areas(&bss, &cont_bss);
1124 }
1125
1126 /* Do the same thing with the Bluetooth data section */
1127 if (ret == ESP_OK) {
1128 ret = esp_bt_mem_release_areas(&data, &cont_data);
1129 }
1130 #endif
1131
1132 return ret;
1133 }
1134
1135
esp_bt_controller_get_status(void)1136 esp_bt_controller_status_t esp_bt_controller_get_status(void)
1137 {
1138 return ble_controller_status;
1139 }
1140
1141 /* extra functions */
esp_ble_tx_power_set(esp_ble_power_type_t power_type,esp_power_level_t power_level)1142 esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
1143 {
1144 esp_err_t stat = ESP_FAIL;
1145
1146 switch (power_type) {
1147 case ESP_BLE_PWR_TYPE_DEFAULT:
1148 case ESP_BLE_PWR_TYPE_ADV:
1149 case ESP_BLE_PWR_TYPE_SCAN:
1150 if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
1151 stat = ESP_OK;
1152 }
1153 break;
1154 case ESP_BLE_PWR_TYPE_CONN_HDL0:
1155 case ESP_BLE_PWR_TYPE_CONN_HDL1:
1156 case ESP_BLE_PWR_TYPE_CONN_HDL2:
1157 case ESP_BLE_PWR_TYPE_CONN_HDL3:
1158 case ESP_BLE_PWR_TYPE_CONN_HDL4:
1159 case ESP_BLE_PWR_TYPE_CONN_HDL5:
1160 case ESP_BLE_PWR_TYPE_CONN_HDL6:
1161 case ESP_BLE_PWR_TYPE_CONN_HDL7:
1162 case ESP_BLE_PWR_TYPE_CONN_HDL8:
1163 if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) {
1164 stat = ESP_OK;
1165 }
1166 break;
1167 default:
1168 stat = ESP_ERR_NOT_SUPPORTED;
1169 break;
1170 }
1171
1172 return stat;
1173 }
1174
esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type,uint16_t handle,esp_power_level_t power_level)1175 esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level)
1176 {
1177 esp_err_t stat = ESP_FAIL;
1178 switch (power_type) {
1179 case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
1180 case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
1181 case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
1182 if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
1183 stat = ESP_OK;
1184 }
1185 break;
1186 case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
1187 case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
1188 if (ble_txpwr_set(power_type, handle, power_level) == 0) {
1189 stat = ESP_OK;
1190 }
1191 break;
1192 default:
1193 stat = ESP_ERR_NOT_SUPPORTED;
1194 break;
1195 }
1196
1197 return stat;
1198 }
1199
esp_ble_tx_power_get(esp_ble_power_type_t power_type)1200 esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
1201 {
1202 int tx_level = 0;
1203
1204 switch (power_type) {
1205 case ESP_BLE_PWR_TYPE_ADV:
1206 case ESP_BLE_PWR_TYPE_SCAN:
1207 case ESP_BLE_PWR_TYPE_DEFAULT:
1208 tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
1209 break;
1210 case ESP_BLE_PWR_TYPE_CONN_HDL0:
1211 case ESP_BLE_PWR_TYPE_CONN_HDL1:
1212 case ESP_BLE_PWR_TYPE_CONN_HDL2:
1213 case ESP_BLE_PWR_TYPE_CONN_HDL3:
1214 case ESP_BLE_PWR_TYPE_CONN_HDL4:
1215 case ESP_BLE_PWR_TYPE_CONN_HDL5:
1216 case ESP_BLE_PWR_TYPE_CONN_HDL6:
1217 case ESP_BLE_PWR_TYPE_CONN_HDL7:
1218 case ESP_BLE_PWR_TYPE_CONN_HDL8:
1219 tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type);
1220 break;
1221 default:
1222 return ESP_PWR_LVL_INVALID;
1223 }
1224
1225 if (tx_level < 0) {
1226 return ESP_PWR_LVL_INVALID;
1227 }
1228
1229 return (esp_power_level_t)tx_level;
1230 }
1231
esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type,uint16_t handle)1232 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle)
1233 {
1234 int tx_level = 0;
1235
1236 switch (power_type) {
1237 case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
1238 case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
1239 case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
1240 tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
1241 break;
1242 case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
1243 case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
1244 tx_level = ble_txpwr_get(power_type, handle);
1245 break;
1246 default:
1247 return ESP_PWR_LVL_INVALID;
1248 }
1249
1250 if (tx_level < 0) {
1251 return ESP_PWR_LVL_INVALID;
1252 }
1253
1254 return (esp_power_level_t)tx_level;
1255 }
1256
esp_ble_get_chip_rev_version(void)1257 uint8_t esp_ble_get_chip_rev_version(void)
1258 {
1259 return efuse_ll_get_chip_wafer_version_minor();
1260 }
1261
1262 #if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
1263 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
1264 #define BLE_SM_KEY_ERR 0x17
1265 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1266 #include "mbedtls/aes.h"
1267 #if CONFIG_BT_LE_SM_SC
1268 #include "mbedtls/cipher.h"
1269 #include "mbedtls/entropy.h"
1270 #include "mbedtls/ctr_drbg.h"
1271 #include "mbedtls/cmac.h"
1272 #include "mbedtls/ecdh.h"
1273 #include "mbedtls/ecp.h"
1274
1275 static mbedtls_ecp_keypair keypair;
1276 #endif // CONFIG_BT_LE_SM_SC
1277
1278 #else
1279 #include "tinycrypt/aes.h"
1280 #include "tinycrypt/constants.h"
1281 #include "tinycrypt/utils.h"
1282
1283 #if CONFIG_BT_LE_SM_SC
1284 #include "tinycrypt/cmac_mode.h"
1285 #include "tinycrypt/ecc_dh.h"
1286 #endif // CONFIG_BT_LE_SM_SC
1287 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1288
1289 /* Based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */
1290 static const uint8_t ble_sm_alg_dbg_priv_key[32] = {
1291 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3,
1292 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99,
1293 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd
1294 };
1295
ble_sm_alg_gen_dhkey(const uint8_t * peer_pub_key_x,const uint8_t * peer_pub_key_y,const uint8_t * our_priv_key,uint8_t * out_dhkey)1296 int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
1297 const uint8_t *our_priv_key, uint8_t *out_dhkey)
1298 {
1299 uint8_t dh[32];
1300 uint8_t pk[64];
1301 uint8_t priv[32];
1302 int rc = BLE_SM_KEY_ERR;
1303
1304 swap_buf(pk, peer_pub_key_x, 32);
1305 swap_buf(&pk[32], peer_pub_key_y, 32);
1306 swap_buf(priv, our_priv_key, 32);
1307
1308 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1309 struct mbedtls_ecp_point pt = {0}, Q = {0};
1310 mbedtls_mpi z = {0}, d = {0};
1311 mbedtls_ctr_drbg_context ctr_drbg = {0};
1312 mbedtls_entropy_context entropy = {0};
1313
1314 uint8_t pub[65] = {0};
1315 /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */
1316 pub[0] = 0x04;
1317 memcpy(&pub[1], pk, 64);
1318
1319 /* Initialize the required structures here */
1320 mbedtls_ecp_point_init(&pt);
1321 mbedtls_ecp_point_init(&Q);
1322 mbedtls_ctr_drbg_init(&ctr_drbg);
1323 mbedtls_entropy_init(&entropy);
1324 mbedtls_mpi_init(&d);
1325 mbedtls_mpi_init(&z);
1326
1327 /* Below 3 steps are to validate public key on curve secp256r1 */
1328 if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) {
1329 goto exit;
1330 }
1331
1332 if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) {
1333 goto exit;
1334 }
1335
1336 if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) {
1337 goto exit;
1338 }
1339
1340 /* Set PRNG */
1341 if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0)) != 0) {
1342 goto exit;
1343 }
1344
1345 /* Prepare point Q from pub key */
1346 if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) {
1347 goto exit;
1348 }
1349
1350 if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) {
1351 goto exit;
1352 }
1353
1354 rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d,
1355 mbedtls_ctr_drbg_random, &ctr_drbg);
1356 if (rc != 0) {
1357 goto exit;
1358 }
1359
1360 rc = mbedtls_mpi_write_binary(&z, dh, 32);
1361 if (rc != 0) {
1362 goto exit;
1363 }
1364
1365 exit:
1366 mbedtls_ecp_point_free(&pt);
1367 mbedtls_mpi_free(&z);
1368 mbedtls_mpi_free(&d);
1369 mbedtls_ecp_point_free(&Q);
1370 mbedtls_entropy_free(&entropy);
1371 mbedtls_ctr_drbg_free(&ctr_drbg);
1372 if (rc != 0) {
1373 return BLE_SM_KEY_ERR;
1374 }
1375
1376 #else
1377 if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) {
1378 return BLE_SM_KEY_ERR;
1379 }
1380
1381 rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1);
1382 if (rc == TC_CRYPTO_FAIL) {
1383 return BLE_SM_KEY_ERR;
1384 }
1385 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1386
1387 swap_buf(out_dhkey, dh, 32);
1388 return 0;
1389 }
1390
1391 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
mbedtls_gen_keypair(uint8_t * public_key,uint8_t * private_key)1392 static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key)
1393 {
1394 int rc = BLE_SM_KEY_ERR;
1395 mbedtls_entropy_context entropy = {0};
1396 mbedtls_ctr_drbg_context ctr_drbg = {0};
1397
1398 mbedtls_entropy_init(&entropy);
1399 mbedtls_ctr_drbg_init(&ctr_drbg);
1400 mbedtls_ecp_keypair_init(&keypair);
1401
1402 if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
1403 NULL, 0)) != 0) {
1404 goto exit;
1405 }
1406
1407 if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair,
1408 mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) {
1409 goto exit;
1410 }
1411
1412 if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) {
1413 goto exit;
1414 }
1415
1416 size_t olen = 0;
1417 uint8_t pub[65] = {0};
1418
1419 if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp), &keypair.MBEDTLS_PRIVATE(Q), MBEDTLS_ECP_PF_UNCOMPRESSED,
1420 &olen, pub, 65)) != 0) {
1421 goto exit;
1422 }
1423
1424 memcpy(public_key, &pub[1], 64);
1425
1426 exit:
1427 mbedtls_ctr_drbg_free(&ctr_drbg);
1428 mbedtls_entropy_free(&entropy);
1429 if (rc != 0) {
1430 mbedtls_ecp_keypair_free(&keypair);
1431 return BLE_SM_KEY_ERR;
1432 }
1433
1434 return 0;
1435 }
1436 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1437
1438 /**
1439 * pub: 64 bytes
1440 * priv: 32 bytes
1441 */
ble_sm_alg_gen_key_pair(uint8_t * pub,uint8_t * priv)1442 int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
1443 {
1444 #if CONFIG_BT_LE_SM_SC_DEBUG_KEYS
1445 swap_buf(pub, ble_sm_alg_dbg_pub_key, 32);
1446 swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32);
1447 swap_buf(priv, ble_sm_alg_dbg_priv_key, 32);
1448 #else
1449 uint8_t pk[64];
1450
1451 do {
1452 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1453 if (mbedtls_gen_keypair(pk, priv) != 0) {
1454 return BLE_SM_KEY_ERR;
1455 }
1456 #else
1457 if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) {
1458 return BLE_SM_KEY_ERR;
1459 }
1460 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1461 /* Make sure generated key isn't debug key. */
1462 } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0);
1463
1464 swap_buf(pub, pk, 32);
1465 swap_buf(&pub[32], &pk[32], 32);
1466 swap_in_place(priv, 32);
1467 #endif // CONFIG_BT_LE_SM_SC_DEBUG_KEYS
1468 return 0;
1469 }
1470
1471 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
1472 #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
1473
