1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _AON_SHARE_H_ 8 #define _AON_SHARE_H_ 9 10 #include "../ia_structs.h" 11 #include "../ish_pm.h" 12 13 /* magic ID for valid aontask image check */ 14 #define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ 15 16 /* aontask error code */ 17 #define AON_SUCCESS 0 18 #define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 19 #define AON_ERROR_DMA_FAILED 2 20 21 22 /* shared data structure between main FW and aontask */ 23 struct ish_aon_share { 24 /* magic ID */ 25 uint32_t magic_id; 26 /* error counter */ 27 uint32_t error_count; 28 /* last error */ 29 int last_error; 30 /* successfully exit from IPAPG or not */ 31 uint32_t pg_exit; 32 /* high 32bits of 64 bits dram address for dma */ 33 uint32_t uma_msb; 34 /* aontask's TSS segment entry */ 35 struct tss_entry *aon_tss; 36 /* aontask's LDT start address */ 37 ldt_entry *aon_ldt; 38 /* aontask's LDT's limit size */ 39 uint32_t aon_ldt_size; 40 /* current power state, see chip/ish/power_mgt.h */ 41 enum ish_pm_state pm_state; 42 /* for store/restore main FW's IDT */ 43 struct idt_header main_fw_idt_hdr; 44 45 /** 46 * main FW's read only code and data region in main SRAM, 47 * address need 64 bytes align due to DMA requirement 48 */ 49 uint32_t main_fw_ro_addr; 50 uint32_t main_fw_ro_size; 51 52 /** 53 * main FW's read and write data region in main SRAM, 54 * address need 64 bytes align due to DMA requirement 55 */ 56 uint32_t main_fw_rw_addr; 57 uint32_t main_fw_rw_size; 58 59 /* host suspend state */ 60 uint32_t host_in_suspend; 61 } __attribute__((packed)); 62 63 #endif /* _AON_SHARE_H_ */ 64
