1 /*
2  * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef CHIP_CHIPREGS_H
7 #define CHIP_CHIPREGS_H
8 
9 #include <zephyr/sys/util.h>
10 
11 #define EC_REG_BASE_ADDR 0x00f00000
12 
13 #ifdef _ASMLANGUAGE
14 #define ECREG(x)        x
15 #else
16 
17 /*
18  * Macros for hardware registers access.
19  */
20 #define ECREG(x)		(*((volatile unsigned char *)(x)))
21 #define ECREG_u16(x)		(*((volatile unsigned short *)(x)))
22 #define ECREG_u32(x)		(*((volatile unsigned long  *)(x)))
23 
24 /*
25  * MASK operation macros
26  */
27 #define SET_MASK(reg, bit_mask)			((reg) |= (bit_mask))
28 #define CLEAR_MASK(reg, bit_mask)		((reg) &= (~(bit_mask)))
29 #define IS_MASK_SET(reg, bit_mask)		(((reg) & (bit_mask)) != 0)
30 #endif /* _ASMLANGUAGE */
31 
32 #ifndef REG_BASE_ADDR
33 #define REG_BASE_ADDR				EC_REG_BASE_ADDR
34 #endif
35 
36 /* Common definition */
37 /*
38  * EC clock frequency (PWM and tachometer driver need it to reply
39  * to api or calculate RPM)
40  */
41 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
42 #define EC_FREQ			MHZ(24)
43 #else
44 #define EC_FREQ			MHZ(8)
45 
46 #endif
47 
48 /* --- General Control (GCTRL) --- */
49 #define IT8XXX2_GCTRL_BASE      0x00F02000
50 #define IT8XXX2_GCTRL_EIDSR     ECREG(IT8XXX2_GCTRL_BASE + 0x31)
51 #define IT8XXX2_GCTRL_PMER3     ECREG(IT8XXX2_GCTRL_BASE + 0x46)
52 /* RISC-V JTAG Debug Interface Enable */
53 #define IT8XXX2_GCTRL_JTAGEN    BIT(1)
54 /* RISC-V JTAG Debug Interface Selection */
55 #define IT8XXX2_GCTRL_JTAGSEL   BIT(0)
56 #define IT8XXX2_GCTRL_JTAG      (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
57 
58 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
59 #define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01660)
60 #define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF01648)
61 #elif CONFIG_SOC_IT8XXX2_REG_SET_V1
62 #define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01610)
63 #define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF016e9)
64 #endif
65 
66 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
67 /* --- External GPIO Control (EGPIO) --- */
68 #define IT8XXX2_EGPIO_BASE      0x00F02100
69 #define IT8XXX2_EGPIO_EGCR      ECREG(IT8XXX2_EGPIO_BASE + 0x04)
70 
71 /* EGPIO register fields */
72 /*
73  * 0x04: External GPIO Control
74  * BIT(4): EXGPIO EGAD Pin Output Driving Disable
75  */
76 #define IT8XXX2_EGPIO_EEPODD    BIT(4)
77 #endif
78 
79 /**
80  *
81  * (11xxh) Interrupt controller (INTC)
82  *
83  */
84 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
85 #define ISR0			ECREG(EC_REG_BASE_ADDR + 0x3F00)
86 #define ISR1			ECREG(EC_REG_BASE_ADDR + 0x3F01)
87 #define ISR2			ECREG(EC_REG_BASE_ADDR + 0x3F02)
88 #define ISR3			ECREG(EC_REG_BASE_ADDR + 0x3F03)
89 #define ISR4			ECREG(EC_REG_BASE_ADDR + 0x3F14)
90 #define ISR5			ECREG(EC_REG_BASE_ADDR + 0x3F18)
91 #define ISR6			ECREG(EC_REG_BASE_ADDR + 0x3F1C)
92 #define ISR7			ECREG(EC_REG_BASE_ADDR + 0x3F20)
93 #define ISR8			ECREG(EC_REG_BASE_ADDR + 0x3F24)
94 #define ISR9			ECREG(EC_REG_BASE_ADDR + 0x3F28)
95 #define ISR10			ECREG(EC_REG_BASE_ADDR + 0x3F2C)
96 #define ISR11			ECREG(EC_REG_BASE_ADDR + 0x3F30)
97 #define ISR12			ECREG(EC_REG_BASE_ADDR + 0x3F34)
98 #define ISR13			ECREG(EC_REG_BASE_ADDR + 0x3F38)
99 #define ISR14			ECREG(EC_REG_BASE_ADDR + 0x3F3C)
100 #define ISR15			ECREG(EC_REG_BASE_ADDR + 0x3F40)
101 #define ISR16			ECREG(EC_REG_BASE_ADDR + 0x3F44)
102 #define ISR17			ECREG(EC_REG_BASE_ADDR + 0x3F48)
103 #define ISR18			ECREG(EC_REG_BASE_ADDR + 0x3F4C)
104 #define ISR19			ECREG(EC_REG_BASE_ADDR + 0x3F50)
105 #define ISR20			ECREG(EC_REG_BASE_ADDR + 0x3F54)
106 #define ISR21			ECREG(EC_REG_BASE_ADDR + 0x3F58)
107 #define ISR22			ECREG(EC_REG_BASE_ADDR + 0x3F5C)
108 #define ISR23			ECREG(EC_REG_BASE_ADDR + 0x3F90)
109 
110 #define IER0			ECREG(EC_REG_BASE_ADDR + 0x3F04)
111 #define IER1			ECREG(EC_REG_BASE_ADDR + 0x3F05)
112 #define IER2			ECREG(EC_REG_BASE_ADDR + 0x3F06)
113 #define IER3			ECREG(EC_REG_BASE_ADDR + 0x3F07)
114 #define IER4			ECREG(EC_REG_BASE_ADDR + 0x3F15)
115 #define IER5			ECREG(EC_REG_BASE_ADDR + 0x3F19)
116 #define IER6			ECREG(EC_REG_BASE_ADDR + 0x3F1D)
117 #define IER7			ECREG(EC_REG_BASE_ADDR + 0x3F21)
118 #define IER8			ECREG(EC_REG_BASE_ADDR + 0x3F25)
119 #define IER9			ECREG(EC_REG_BASE_ADDR + 0x3F29)
120 #define IER10			ECREG(EC_REG_BASE_ADDR + 0x3F2D)
121 #define IER11			ECREG(EC_REG_BASE_ADDR + 0x3F31)
122 #define IER12			ECREG(EC_REG_BASE_ADDR + 0x3F35)
123 #define IER13			ECREG(EC_REG_BASE_ADDR + 0x3F39)
124 #define IER14			ECREG(EC_REG_BASE_ADDR + 0x3F3D)
125 #define IER15			ECREG(EC_REG_BASE_ADDR + 0x3F41)
126 #define IER16			ECREG(EC_REG_BASE_ADDR + 0x3F45)
127 #define IER17			ECREG(EC_REG_BASE_ADDR + 0x3F49)
128 #define IER18			ECREG(EC_REG_BASE_ADDR + 0x3F4D)
129 #define IER19			ECREG(EC_REG_BASE_ADDR + 0x3F51)
130 #define IER20			ECREG(EC_REG_BASE_ADDR + 0x3F55)
131 #define IER21			ECREG(EC_REG_BASE_ADDR + 0x3F59)
132 #define IER22			ECREG(EC_REG_BASE_ADDR + 0x3F5D)
133 #define IER23			ECREG(EC_REG_BASE_ADDR + 0x3F91)
134 
135 #define IELMR0			ECREG(EC_REG_BASE_ADDR + 0x3F08)
136 #define IELMR1			ECREG(EC_REG_BASE_ADDR + 0x3F09)
137 #define IELMR2			ECREG(EC_REG_BASE_ADDR + 0x3F0A)
138 #define IELMR3			ECREG(EC_REG_BASE_ADDR + 0x3F0B)
139 #define IELMR4			ECREG(EC_REG_BASE_ADDR + 0x3F16)
140 #define IELMR5			ECREG(EC_REG_BASE_ADDR + 0x3F1A)
141 #define IELMR6			ECREG(EC_REG_BASE_ADDR + 0x3F1E)
142 #define IELMR7			ECREG(EC_REG_BASE_ADDR + 0x3F22)
143 #define IELMR8			ECREG(EC_REG_BASE_ADDR + 0x3F26)
144 #define IELMR9			ECREG(EC_REG_BASE_ADDR + 0x3F2A)
145 #define IELMR10			ECREG(EC_REG_BASE_ADDR + 0x3F2E)
146 #define IELMR11			ECREG(EC_REG_BASE_ADDR + 0x3F32)
147 #define IELMR12			ECREG(EC_REG_BASE_ADDR + 0x3F36)
148 #define IELMR13			ECREG(EC_REG_BASE_ADDR + 0x3F3A)
149 #define IELMR14			ECREG(EC_REG_BASE_ADDR + 0x3F3E)
150 #define IELMR15			ECREG(EC_REG_BASE_ADDR + 0x3F42)
151 #define IELMR16			ECREG(EC_REG_BASE_ADDR + 0x3F46)
152 #define IELMR17			ECREG(EC_REG_BASE_ADDR + 0x3F4A)
153 #define IELMR18			ECREG(EC_REG_BASE_ADDR + 0x3F4E)
154 #define IELMR19			ECREG(EC_REG_BASE_ADDR + 0x3F52)
155 #define IELMR20			ECREG(EC_REG_BASE_ADDR + 0x3F56)
156 #define IELMR21			ECREG(EC_REG_BASE_ADDR + 0x3F5A)
157 #define IELMR22			ECREG(EC_REG_BASE_ADDR + 0x3F5E)
158 #define IELMR23			ECREG(EC_REG_BASE_ADDR + 0x3F92)
159 
160 #define IPOLR0			ECREG(EC_REG_BASE_ADDR + 0x3F0C)
161 #define IPOLR1			ECREG(EC_REG_BASE_ADDR + 0x3F0D)
162 #define IPOLR2			ECREG(EC_REG_BASE_ADDR + 0x3F0E)
163 #define IPOLR3			ECREG(EC_REG_BASE_ADDR + 0x3F0F)
164 #define IPOLR4			ECREG(EC_REG_BASE_ADDR + 0x3F17)
165 #define IPOLR5			ECREG(EC_REG_BASE_ADDR + 0x3F1B)
166 #define IPOLR6			ECREG(EC_REG_BASE_ADDR + 0x3F1F)
167 #define IPOLR7			ECREG(EC_REG_BASE_ADDR + 0x3F23)
168 #define IPOLR8			ECREG(EC_REG_BASE_ADDR + 0x3F27)
169 #define IPOLR9			ECREG(EC_REG_BASE_ADDR + 0x3F2B)
170 #define IPOLR10			ECREG(EC_REG_BASE_ADDR + 0x3F2F)
171 #define IPOLR11			ECREG(EC_REG_BASE_ADDR + 0x3F33)
172 #define IPOLR12			ECREG(EC_REG_BASE_ADDR + 0x3F37)
173 #define IPOLR13			ECREG(EC_REG_BASE_ADDR + 0x3F3B)
174 #define IPOLR14			ECREG(EC_REG_BASE_ADDR + 0x3F3F)
175 #define IPOLR15			ECREG(EC_REG_BASE_ADDR + 0x3F43)
176 #define IPOLR16			ECREG(EC_REG_BASE_ADDR + 0x3F47)
177 #define IPOLR17			ECREG(EC_REG_BASE_ADDR + 0x3F4B)
178 #define IPOLR18			ECREG(EC_REG_BASE_ADDR + 0x3F4F)
179 #define IPOLR19			ECREG(EC_REG_BASE_ADDR + 0x3F53)
180 #define IPOLR20			ECREG(EC_REG_BASE_ADDR + 0x3F57)
181 #define IPOLR21			ECREG(EC_REG_BASE_ADDR + 0x3F5B)
182 #define IPOLR22			ECREG(EC_REG_BASE_ADDR + 0x3F5F)
183 #define IPOLR23			ECREG(EC_REG_BASE_ADDR + 0x3F93)
184 #endif
185 #define IVECT			ECREG(EC_REG_BASE_ADDR + 0x3F10)
186 
187 
188 /*
189  * TODO: use pinctrl node instead of following register declarations
190  *       to fix in tcpm\it83xx_pd.h.
191  */
192 /* GPIO control register */
193 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
194 #define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x163C)
195 #define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x163D)
196 #define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1649)
197 #define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x164A)
198 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
199 #define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x168C)
200 #define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x168D)
201 #define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1699)
202 #define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x169A)
203 #endif
204 
205 /*
206  * IT8XXX2 register structure size/offset checking macro function to mitigate
207  * the risk of unexpected compiling results.
208  */
209 #define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \
210 	BUILD_ASSERT(sizeof(struct reg_def) == size, \
211 		"Failed in size check of register structure!")
212 #define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \
213 	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
214 		"Failed in offset check of register structure member!")
215 
216 /**
217  *
218  * (18xxh) PWM & SmartAuto Fan Control (PWM)
219  *
220  */
221 #ifndef __ASSEMBLER__
222 struct pwm_it8xxx2_regs {
223 	/* 0x000: Channel0 Clock Prescaler */
224 	volatile uint8_t C0CPRS;
225 	/* 0x001: Cycle Time0 */
226 	volatile uint8_t CTR;
227 	/* 0x002~0x00A: Reserved1 */
228 	volatile uint8_t Reserved1[9];
229 	/* 0x00B: Prescaler Clock Frequency Select */
230 	volatile uint8_t PCFSR;
231 	/* 0x00C~0x00F: Reserved2 */
232 	volatile uint8_t Reserved2[4];
233 	/* 0x010: Cycle Time1 MSB */
234 	volatile uint8_t CTR1M;
235 	/* 0x011~0x022: Reserved3 */
236 	volatile uint8_t Reserved3[18];
237 	/* 0x023: PWM Clock Control */
238 	volatile uint8_t ZTIER;
239 	/* 0x024~0x026: Reserved4 */
240 	volatile uint8_t Reserved4[3];
241 	/* 0x027: Channel4 Clock Prescaler */
242 	volatile uint8_t C4CPRS;
243 	/* 0x028: Channel4 Clock Prescaler MSB */
244 	volatile uint8_t C4MCPRS;
245 	/* 0x029~0x02A: Reserved5 */
246 	volatile uint8_t Reserved5[2];
247 	/* 0x02B: Channel6 Clock Prescaler */
248 	volatile uint8_t C6CPRS;
249 	/* 0x02C: Channel6 Clock Prescaler MSB */
250 	volatile uint8_t C6MCPRS;
251 	/* 0x02D: Channel7 Clock Prescaler */
252 	volatile uint8_t C7CPRS;
253 	/* 0x02E: Channel7 Clock Prescaler MSB */
254 	volatile uint8_t C7MCPRS;
255 	/* 0x02F~0x040: Reserved6 */
256 	volatile uint8_t reserved6[18];
257 	/* 0x041: Cycle Time1 */
258 	volatile uint8_t CTR1;
259 	/* 0x042: Cycle Time2 */
260 	volatile uint8_t CTR2;
261 	/* 0x043: Cycle Time3 */
262 	volatile uint8_t CTR3;
263 	/* 0x044~0x048: Reserved7 */
264 	volatile uint8_t reserved7[5];
265 	/* 0x049: PWM Output Open-Drain Enable */
266 	volatile uint8_t PWMODENR;
267 };
268 #endif /* !__ASSEMBLER__ */
269 
270 /* PWM register fields */
271 /* 0x023: PWM Clock Control */
272 #define IT8XXX2_PWM_PCCE		BIT(1)
273 /* 0x048: Tachometer Switch Control */
274 #define IT8XXX2_PWM_T0DVS		BIT(3)
275 #define IT8XXX2_PWM_T0CHSEL		BIT(2)
276 #define IT8XXX2_PWM_T1DVS		BIT(1)
277 #define IT8XXX2_PWM_T1CHSEL		BIT(0)
278 
279 
280 /* --- Wake-Up Control (WUC) --- */
281 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
282 #define IT8XXX2_WUC_BASE   0x00F01B00
283 
284 /* TODO: should a defined interface for configuring wake-up interrupts */
285 #define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00)
286 #define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c)
287 #define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04)
288 #define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
289 #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
290 #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
291 #endif
292 
293 /**
294  *
295  * (1Dxxh) Keyboard Matrix Scan control (KSCAN)
296  *
297  */
298 #ifndef __ASSEMBLER__
299 struct kscan_it8xxx2_regs {
300 	/* 0x000: Keyboard Scan Out */
301 	volatile uint8_t KBS_KSOL;
302 	/* 0x001: Keyboard Scan Out */
303 	volatile uint8_t KBS_KSOH1;
304 	/* 0x002: Keyboard Scan Out Control */
305 	volatile uint8_t KBS_KSOCTRL;
306 	/* 0x003: Keyboard Scan Out */
307 	volatile uint8_t KBS_KSOH2;
308 	/* 0x004: Keyboard Scan In */
309 	volatile uint8_t KBS_KSI;
310 	/* 0x005: Keyboard Scan In Control */
311 	volatile uint8_t KBS_KSICTRL;
312 	/* 0x006: Keyboard Scan In [7:0] GPIO Control */
313 	volatile uint8_t KBS_KSIGCTRL;
314 	/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
315 	volatile uint8_t KBS_KSIGOEN;
316 	/* 0x008: Keyboard Scan In [7:0] GPIO Data */
317 	volatile uint8_t KBS_KSIGDAT;
318 	/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
319 	volatile uint8_t KBS_KSIGDMRR;
320 	/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
321 	volatile uint8_t KBS_KSOHGCTRL;
322 	/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
323 	volatile uint8_t KBS_KSOHGOEN;
324 	/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
325 	volatile uint8_t KBS_KSOHGDMRR;
326 	/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
327 	volatile uint8_t KBS_KSOLGCTRL;
328 	/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
329 	volatile uint8_t KBS_KSOLGOEN;
330 };
331 #endif /* !__ASSEMBLER__ */
332 
333 /* KBS register fields */
334 /* 0x002: Keyboard Scan Out Control */
335 #define IT8XXX2_KBS_KSOPU	BIT(2)
336 #define IT8XXX2_KBS_KSOOD	BIT(0)
337 /* 0x005: Keyboard Scan In Control */
338 #define IT8XXX2_KBS_KSIPU	BIT(2)
339 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
340 #define IT8XXX2_KBS_KSO2GCTRL	BIT(2)
341 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
342 #define IT8XXX2_KBS_KSO2GOEN	BIT(2)
343 
344 
345 /**
346  *
347  * (1Fxxh) External Timer & External Watchdog (ETWD)
348  *
349  */
350 #define WDT_IT8XXX2_REGS_BASE \
351 	((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
352 
353 #ifndef __ASSEMBLER__
354 struct wdt_it8xxx2_regs {
355 	/* 0x000: Reserved1 */
356 	volatile uint8_t reserved1;
357 	/* 0x001: External Timer1/WDT Configuration */
358 	volatile uint8_t ETWCFG;
359 	/* 0x002: External Timer1 Prescaler */
360 	volatile uint8_t ET1PSR;
361 	/* 0x003: External Timer1 Counter High Byte */
362 	volatile uint8_t ET1CNTLHR;
363 	/* 0x004: External Timer1 Counter Low Byte */
364 	volatile uint8_t ET1CNTLLR;
365 	/* 0x005: External Timer1/WDT Control */
366 	volatile uint8_t ETWCTRL;
367 	/* 0x006: External WDT Counter Low Byte */
368 	volatile uint8_t EWDCNTLR;
369 	/* 0x007: External WDT Key */
370 	volatile uint8_t EWDKEYR;
371 	/* 0x008: Reserved2 */
372 	volatile uint8_t reserved2;
373 	/* 0x009: External WDT Counter High Byte */
374 	volatile uint8_t EWDCNTHR;
375 	/* 0x00A: External Timer2 Prescaler */
376 	volatile uint8_t ET2PSR;
377 	/* 0x00B: External Timer2 Counter High Byte */
378 	volatile uint8_t ET2CNTLHR;
379 	/* 0x00C: External Timer2 Counter Low Byte */
380 	volatile uint8_t ET2CNTLLR;
381 	/* 0x00D: Reserved3 */
382 	volatile uint8_t reserved3;
383 	/* 0x00E: External Timer2 Counter High Byte2 */
384 	volatile uint8_t ET2CNTLH2R;
385 };
386 #endif /* !__ASSEMBLER__ */
387 
388 /* WDT register fields */
389 /* 0x001: External Timer1/WDT Configuration */
390 #define IT8XXX2_WDT_EWDKEYEN		BIT(5)
391 #define IT8XXX2_WDT_EWDSRC		BIT(4)
392 #define IT8XXX2_WDT_LEWDCNTL		BIT(3)
393 #define IT8XXX2_WDT_LET1CNTL		BIT(2)
394 #define IT8XXX2_WDT_LET1PS		BIT(1)
395 #define IT8XXX2_WDT_LETWCFG		BIT(0)
396 /* 0x002: External Timer1 Prescaler */
397 #define IT8XXX2_WDT_ETPS_32P768_KHZ	0x00
398 #define IT8XXX2_WDT_ETPS_1P024_KHZ	0x01
399 #define IT8XXX2_WDT_ETPS_32_HZ		0x02
400 /* 0x005: External Timer1/WDT Control */
401 #define IT8XXX2_WDT_EWDSCEN		BIT(5)
402 #define IT8XXX2_WDT_EWDSCMS		BIT(4)
403 #define IT8XXX2_WDT_ET2TC		BIT(3)
404 #define IT8XXX2_WDT_ET2RST		BIT(2)
405 #define IT8XXX2_WDT_ET1TC		BIT(1)
406 #define IT8XXX2_WDT_ET1RST		BIT(0)
407 
408 /* External Timer register fields */
409 /* External Timer 3~8 control */
410 #define IT8XXX2_EXT_ETX_COMB_RST_EN	(IT8XXX2_EXT_ETXCOMB | \
411 					 IT8XXX2_EXT_ETXRST | \
412 					 IT8XXX2_EXT_ETXEN)
413 #define IT8XXX2_EXT_ETXCOMB		BIT(3)
414 #define IT8XXX2_EXT_ETXRST		BIT(1)
415 #define IT8XXX2_EXT_ETXEN		BIT(0)
416 
417 /* Control external timer3~8 */
418 #define IT8XXX2_EXT_TIMER_BASE  DT_REG_ADDR(DT_NODELABEL(timer))  /*0x00F01F10*/
419 #define IT8XXX2_EXT_CTRLX(n)    ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
420 #define IT8XXX2_EXT_PSRX(n)     ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
421 #define IT8XXX2_EXT_CNTX(n)     ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
422 					(n << 3))
423 #define IT8XXX2_EXT_CNTOX(n)    ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
424 					(n << 2))
425 
426 /* Free run timer configurations */
427 #define FREE_RUN_TIMER          EXT_TIMER_4
428 #define FREE_RUN_TIMER_IRQ      DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq)
429 /* Free run timer configurations */
430 #define FREE_RUN_TIMER_FLAG     DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags)
431 /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
432 #define FREE_RUN_TIMER_MAX_CNT  0xFFFFFFFFUL
433 
434 #ifndef __ASSEMBLER__
435 enum ext_clk_src_sel {
436 	EXT_PSR_32P768K = 0,
437 	EXT_PSR_1P024K,
438 	EXT_PSR_32,
439 	EXT_PSR_EC_CLK,
440 };
441 /*
442  * 24-bit timers: external timer 3, 5, and 7
443  * 32-bit timers: external timer 4, 6, and 8
444  */
445 enum ext_timer_idx {
446 	EXT_TIMER_3 = 0,	/* Event timer */
447 	EXT_TIMER_4,		/* Free run timer */
448 	EXT_TIMER_5,		/* Busy wait low timer */
449 	EXT_TIMER_6,		/* Busy wait high timer */
450 	EXT_TIMER_7,
451 	EXT_TIMER_8,
452 };
453 #endif
454 
455 
456 /*
457  *
458  * (2Cxxh) Platform Environment Control Interface (PECI)
459  *
460  */
461 #ifndef __ASSEMBLER__
462 struct peci_it8xxx2_regs {
463 	/* 0x00: Host Status */
464 	volatile uint8_t HOSTAR;
465 	/* 0x01: Host Control */
466 	volatile uint8_t HOCTLR;
467 	/* 0x02: Host Command */
468 	volatile uint8_t HOCMDR;
469 	/* 0x03: Host Target Address */
470 	volatile uint8_t HOTRADDR;
471 	/* 0x04: Host Write Length */
472 	volatile uint8_t HOWRLR;
473 	/* 0x05: Host Read Length */
474 	volatile uint8_t HORDLR;
475 	/* 0x06: Host Write Data */
476 	volatile uint8_t HOWRDR;
477 	/* 0x07: Host Read Data */
478 	volatile uint8_t HORDDR;
479 	/* 0x08: Host Control 2 */
480 	volatile uint8_t HOCTL2R;
481 	/* 0x09: Received Write FCS value */
482 	volatile uint8_t RWFCSV;
483 	/* 0x0A: Received Read FCS value */
484 	volatile uint8_t RRFCSV;
485 	/* 0x0B: Write FCS Value */
486 	volatile uint8_t WFCSV;
487 	/* 0x0C: Read FCS Value */
488 	volatile uint8_t RFCSV;
489 	/* 0x0D: Assured Write FCS Value */
490 	volatile uint8_t AWFCSV;
491 	/* 0x0E: Pad Control */
492 	volatile uint8_t PADCTLR;
493 };
494 #endif /* !__ASSEMBLER__ */
495 
496 /**
497  *
498  * (2Fxxh) USB Device Controller (USBDC) Registers
499  *
500  */
501 #define EP_EXT_REGS_9X        1
502 #define EP_EXT_REGS_BX        2
503 #define EP_EXT_REGS_DX        3
504 
505 #ifndef __ASSEMBLER__
506 
507 /* EP0 to EP15 Enumeration */
508 enum usb_dc_endpoints {
509 	EP0,
510 	EP1,
511 	EP2,
512 	EP3,
513 	EP4,
514 	EP5,
515 	EP6,
516 	EP7,
517 	EP8,
518 	EP9,
519 	EP10,
520 	EP11,
521 	EP12,
522 	EP13,
523 	EP14,
524 	EP15,
525 	MAX_NUM_ENDPOINTS
526 };
527 
528 union ep_ctrl_reg {
529 	volatile uint8_t value;
530 	struct {
531 		volatile uint8_t enable_bit: 1;
532 		volatile uint8_t ready_bit: 1;
533 		volatile uint8_t outdata_sequence_bit: 1;
534 		volatile uint8_t send_stall_bit: 1;
535 		volatile uint8_t iso_enable_bit: 1;
536 		volatile uint8_t direction_bit: 1;
537 		volatile uint8_t reserved: 2;
538 	} __packed fields;
539 } __packed;
540 
541 struct it82xx2_usb_ep_regs {
542 	union ep_ctrl_reg ep_ctrl;
543 	volatile uint8_t ep_status;
544 	volatile uint8_t ep_transtype_sts;
545 	volatile uint8_t ep_nak_transtype_sts;
546 };
547 
548 /* Reserved EP Extended Registers */
549 struct ep_ext_regs_7x {
550 	/* 0x75 Reserved */
551 	volatile uint8_t ep_ext_ctrl_75;
552 	/* 0x76 Reserved */
553 	volatile uint8_t ep_ext_ctrl_76;
554 	/* 0x77 Reserved */
555 	volatile uint8_t ep_ext_ctrl_77;
556 	/* 0x78 Reserved */
557 	volatile uint8_t ep_ext_ctrl_78;
558 	/* 0x79 Reserved */
559 	volatile uint8_t ep_ext_ctrl_79;
560 	/* 0x7A Reserved */
561 	volatile uint8_t ep_ext_ctrl_7a;
562 	/* 0x7B Reserved */
563 	volatile uint8_t ep_ext_ctrl_7b;
564 	/* 0x7C Reserved */
565 	volatile uint8_t ep_ext_ctrl_7c;
566 	/* 0x7D Reserved */
567 	volatile uint8_t ep_ext_ctrl_7d;
568 	/* 0x7E Reserved */
569 	volatile uint8_t ep_ext_ctrl_7e;
570 	/* 0x7F Reserved */
571 	volatile uint8_t ep_ext_ctrl_7f;
572 };
573 
574 /* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers
575  * are defined, and their bits definitions are as follows:
576  *
577  * Bit    Description
578  *  7     Reserved
579  *  6     EPPOINT5_ISO_ENABLE
580  *  5     EPPOINT5_SEND_STALL
581  *  4     EPPOINT5_OUT_DATA_SEQUENCE
582  *  3     Reserved
583  *  2     EPPOINT4_ISO_ENABLE
584  *  1     EPPOINT4_SEND_STALL
585  *  0     EPPOINT4_OUT_DATA_SEQUENCE
586  *
587  * Apparently, we can tell that the EP4 and EP5 share the same register, and
588  * the EP6 and EP7 share the same one, and the rest EPs are defined in the
589  * same way.
590  */
591 union epn0n1_extend_ctrl_reg {
592 	volatile uint8_t value;
593 	struct {
594 		volatile uint8_t epn0_outdata_sequence_bit: 1;
595 		volatile uint8_t epn0_send_stall_bit: 1;
596 		volatile uint8_t epn0_iso_enable_bit: 1;
597 		volatile uint8_t reserved0: 1;
598 		volatile uint8_t epn1_outdata_sequence_bit: 1;
599 		volatile uint8_t epn1_send_stall_bit: 1;
600 		volatile uint8_t epn1_iso_enable_bit: 1;
601 		volatile uint8_t reserved1: 1;
602 	} __packed fields;
603 } __packed;
604 
605 struct ep_ext_regs_9x {
606 	/* 0x95 Reserved */
607 	volatile uint8_t ep_ext_ctrl_95;
608 	/* 0x96 Reserved */
609 	volatile uint8_t ep_ext_ctrl_96;
610 	/* 0x97 Reserved */
611 	volatile uint8_t ep_ext_ctrl_97;
612 	/* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */
613 	union epn0n1_extend_ctrl_reg epn0n1_ext_ctrl[6];
614 	/* 0x9E Reserved */
615 	volatile uint8_t ep_ext_ctrl_9e;
616 	/* 0x9F Reserved */
617 	volatile uint8_t ep_ext_ctrl_9f;
618 };
619 
620 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
621  * definitions as follows:
622  * B8h: EP_FIFO1_CONTROL0_REG
623  * B9h: EP_FIFO1_CONTROL1_REG
624  * BAh: EP_FIFO2_CONTROL0_REG
625  * BBh: EP_FIFO2_CONTROL1_REG
626  * BCh: EP_FIFO3_CONTROL0_REG
627  * BDh: EP_FIFO3_CONTROL1_REG
628  *
629  * For each one, its bits definitions are as follows:
630  * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15)
631  *
632  * Bit  Description
633  *
634  *  7   EP15 select FIFO1 as data buffer
635  *  6   EP14 select FIFO1 as data buffer
636  *  5   EP13 select FIFO1 as data buffer
637  *  4   EP12 select FIFO1 as data buffer
638  *  3   EP11 select FIFO1 as data buffer
639  *  2   EP10 select FIFO1 as data buffer
640  *  1   EP9 select FIFO1 as data buffer
641  *  0   EP8 select FIFO1 as data buffer
642  *
643  *  1: Select
644  *  0: Not select
645  */
646 struct ep_ext_regs_bx {
647 	/* 0xB5 Reserved */
648 	volatile uint8_t ep_ext_ctrl_b5;
649 	/* 0xB6 Reserved */
650 	volatile uint8_t ep_ext_ctrl_b6;
651 	/* 0xB7 Reserved */
652 	volatile uint8_t ep_ext_ctrl_b7;
653 	/* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
654 	volatile uint8_t ep_fifo_ctrl[6];
655 	/* 0xBE Reserved */
656 	volatile uint8_t ep_ext_ctrl_be;
657 	/* 0xBF Reserved */
658 	volatile uint8_t ep_ext_ctrl_bf;
659 };
660 
661 
662 /* From D6h to DDh are EP Extended Control Registers, and their
663  * definitions as follows:
664  * D6h: EP0_EXT_CTRL1
665  * D7h: EP0_EXT_CTRL2
666  * D8h: EP1_EXT_CTRL1
667  * D9h: EP1_EXT_CTRL2
668  * DAh: EP2_EXT_CTRL1
669  * DBh: EP2_EXT_CTRL2
670  * DCh: EP3_EXT_CTRL1
671  * DDh: EP3_EXT_CTRL2
672  *
673  * We classify them into 4 groups which each of them contains Control 1 and 2
674  * according to the EP number as follows:
675  */
676 union epn_extend_ctrl1_reg {
677 	volatile uint8_t value;
678 	struct {
679 		volatile uint8_t epn0_enable_bit: 1;
680 		volatile uint8_t epn0_direction_bit: 1;
681 		volatile uint8_t epn3_enable_bit: 1;
682 		volatile uint8_t epn3_direction_bit: 1;
683 		volatile uint8_t epn6_enable_bit: 1;
684 		volatile uint8_t epn6_direction_bit: 1;
685 		volatile uint8_t epn9_enable_bit: 1;
686 		volatile uint8_t epn9_direction_bit: 1;
687 	} __packed fields;
688 } __packed;
689 
690 struct epn_ext_ctrl_regs {
691 	/* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */
692 	union epn_extend_ctrl1_reg epn_ext_ctrl1;
693 	/* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */
694 	volatile uint8_t epn_ext_ctrl2;
695 };
696 
697 struct ep_ext_regs_dx {
698 	/* 0xD5 Reserved */
699 	volatile uint8_t ep_ext_ctrl_d5;
700 	/* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */
701 	struct epn_ext_ctrl_regs epn_ext_ctrl[4];
702 	/* 0xDE Reserved */
703 	volatile uint8_t ep_ext_ctrl_de;
704 	/* 0xDF Reserved */
705 	volatile uint8_t ep_ext_ctrl_df;
706 };
707 
708 
709 /* The USB EPx FIFO Registers Definitions
710  * EP0: 60h ~ 74h
711  * EP1: 80h ~ 94h
712  * EP2: A0h ~ B4h
713  * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage)
714  */
715 struct it82xx2_usb_ep_fifo_regs {
716 	/* 0x60 + ep * 0x20 : EP RX FIFO Data Register  */
717 	volatile uint8_t ep_rx_fifo_data;
718 	/* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */
719 	volatile uint8_t ep_rx_fifo_dma_count;
720 	/* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */
721 	volatile uint8_t ep_rx_fifo_dcnt_msb;
722 	/* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */
723 	volatile uint8_t ep_rx_fifo_dcnt_lsb;
724 	/* 0x64 + ep * 0x20  : EP RX FIFO Control Register */
725 	volatile uint8_t ep_rx_fifo_ctrl;
726 	/* (0x65 ~ 0x6F) + ep * 0x20 */
727 	volatile uint8_t reserved_65_6f_add_20[11];
728 	/* 0x70 + ep * 0x20 : EP TX FIFO Data Register  */
729 	volatile uint8_t ep_tx_fifo_data;
730 	/* (0x71 ~ 0x73) + ep * 0x20 */
731 	volatile uint8_t reserved_71_73_add_20[3];
732 	/* 0x74 + ep * 0x20 : EP TX FIFO Control Register */
733 	volatile uint8_t ep_tx_fifo_ctrl;
734 	/* (0x75 ~ 0x7F) + ep * 0x20 */
735 	union {
736 		struct ep_ext_regs_7x ep_res;
737 		struct ep_ext_regs_9x ext_4_15;
738 		struct ep_ext_regs_bx fifo_ctrl;
739 		struct ep_ext_regs_dx ext_0_3;
740 	};
741 
742 };
743 
744 /* USB Control registers */
745 #define USB_IT82XX2_REGS_BASE \
746 	((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
747 
748 /* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
749 #define PULL_DOWN_EN	BIT(4)
750 
751 struct usb_it82xx2_regs {
752 	/* 0x00:  Host TX Contrl Register */
753 	volatile uint8_t host_tx_ctrl;
754 	/* 0x01:  Host TX Transaction Type Register */
755 	volatile uint8_t host_tx_trans_type;
756 	/* 0x02:  Host TX Line Control Register */
757 	volatile uint8_t host_tx_line_ctrl;
758 	/* 0x03:  Host TX SOF Enable Register */
759 	volatile uint8_t host_tx_sof_enable;
760 	/* 0x04:  Host TX Address Register */
761 	volatile uint8_t host_tx_addr;
762 	/* 0x05:  Host TX EP Number Register */
763 	volatile uint8_t host_tx_endp;
764 	/* 0x06:  Host Frame Number MSP Register */
765 	volatile uint8_t host_frame_num_msp;
766 	/* 0x07:  Host Frame Number LSP Register */
767 	volatile uint8_t host_frame_num_lsp;
768 	/* 0x08:  Host Interrupt Status Register */
769 	volatile uint8_t host_interrupt_status;
770 	/* 0x09:  Host Interrupt Mask Register */
771 	volatile uint8_t host_interrupt_mask;
772 	/* 0x0A:  Host RX Status Register */
773 	volatile uint8_t host_rx_status;
774 	/* 0x0B:  Host RX PID Register */
775 	volatile uint8_t host_rx_pid;
776 	/* 0x0C:  MISC Control Register */
777 	volatile uint8_t misc_control;
778 	/* 0x0D:  MISC Status Register */
779 	volatile uint8_t misc_status;
780 	/* 0x0E:  Host RX Connect State Register */
781 	volatile uint8_t host_rx_connect_state;
782 	/* 0x0F:  Host SOF Timer MSB Register */
783 	volatile uint8_t host_sof_timer_msb;
784 	/* 0x10 ~ 0x1F:  Reserved Registers 10h - 1Fh */
785 	volatile uint8_t reserved_10_1f[16];
786 	/* 0x20:  Host RX FIFO Data Port Register */
787 	volatile uint8_t host_rx_fifo_data;
788 	/* 0x21:  Host RX FIFO DMA Input Data Count Register */
789 	volatile uint8_t host_rx_fifo_dma_data_count;
790 	/* 0x22:  Host TX FIFO Data Count MSB Register */
791 	volatile uint8_t host_rx_fifo_data_count_msb;
792 	/* 0x23:  Host TX FIFO Data Count LSB Register */
793 	volatile uint8_t host_rx_fifo_data_count_lsb;
794 	/* 0x24:  Host RX FIFO Data Port Register */
795 	volatile uint8_t host_rx_fifo_control;
796 	/* 0x25 ~ 0x2F:  Reserved Registers 25h - 2Fh */
797 	volatile uint8_t reserved_25_2f[11];
798 	/* 0x30:  Host TX FIFO Data Port Register */
799 	volatile uint8_t host_tx_fifo_data;
800 	/* 0x31 ~ 0x3F:  Reserved Registers 31h - 3Fh */
801 	volatile uint8_t reserved_31_3f[15];
802 	/* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
803 	struct it82xx2_usb_ep_regs usb_ep_regs[4];
804 	/* 0x50:  Device Controller Control Register */
805 	volatile uint8_t dc_control;
806 	/* 0x51:  Device Controller LINE Status Register */
807 	volatile uint8_t dc_line_status;
808 	/* 0x52:  Device Controller Interrupt Status Register */
809 	volatile uint8_t dc_interrupt_status;
810 	/* 0x53:  Device Controller Interrupt Mask Register */
811 	volatile uint8_t dc_interrupt_mask;
812 	/* 0x54:  Device Controller Address Register */
813 	volatile uint8_t dc_address;
814 	/* 0x55:  Device Controller Frame Number MSP Register */
815 	volatile uint8_t dc_frame_num_msp;
816 	/* 0x56:  Device Controller Frame Number LSP Register */
817 	volatile uint8_t dc_frame_num_lsp;
818 	/* 0x57 ~ 0x5F:  Reserved Registers 57h - 5Fh */
819 	volatile uint8_t reserved_57_5f[9];
820 	/* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
821 	struct it82xx2_usb_ep_fifo_regs fifo_regs[4];
822 	/* 0xE0:  Host/Device Control Register */
823 	volatile uint8_t host_device_control;
824 	/* 0xE1 ~ 0xE3:  Reserved Registers E1h - E3h */
825 	volatile uint8_t reserved_e1_e3[3];
826 	/* 0xE4:  Port0 MISC Control Register */
827 	volatile uint8_t port0_misc_control;
828 	/* 0xE5 ~ 0xE7:  Reserved Registers E5h - E7h */
829 	volatile uint8_t reserved_e5_e7[3];
830 	/* 0xE8:  Port1 MISC Control Register */
831 	volatile uint8_t port1_misc_control;
832 };
833 #endif /* #ifndef __ASSEMBLER__ */
834 
835 /**
836  *
837  * (37xxh, 38xxh) USBPD Controller
838  *
839  */
840 #ifndef __ASSEMBLER__
841 struct usbpd_it8xxx2_regs {
842 	/* 0x000~0x003: Reserved1 */
843 	volatile uint8_t Reserved1[4];
844 	/* 0x004: CC General Configuration */
845 	volatile uint8_t CCGCR;
846 	/* 0x005: CC Channel Setting */
847 	volatile uint8_t CCCSR;
848 	/* 0x006: CC Pad Setting */
849 	volatile uint8_t CCPSR;
850 };
851 #endif /* !__ASSEMBLER__ */
852 
853 /* USBPD controller register fields */
854 /* 0x004: CC General Configuration */
855 #define IT8XXX2_USBPD_DISABLE_CC			BIT(7)
856 #define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR		BIT(6)
857 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED		(BIT(3) | BIT(2) | BIT(1))
858 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF			(BIT(3) | BIT(2))
859 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5			BIT(3)
860 #define IT8XXX2_USBPD_CC_SELECT_RP_3A0			BIT(2)
861 #define IT8XXX2_USBPD_CC1_CC2_SELECTION			BIT(0)
862 /* 0x005: CC Channel Setting */
863 #define IT8XXX2_USBPD_CC2_DISCONNECT			BIT(7)
864 #define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND	BIT(6)
865 #define IT8XXX2_USBPD_CC1_DISCONNECT			BIT(3)
866 #define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND	BIT(2)
867 #define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT		(BIT(1) | BIT(5))
868 /* 0x006: CC Pad Setting */
869 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB		BIT(6)
870 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC2		BIT(5)
871 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB		BIT(2)
872 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC1		BIT(1)
873 
874 
875 /**
876  *
877  * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
878  *
879  */
880 #ifndef __ASSEMBLER__
881 struct smfi_it8xxx2_regs {
882 	volatile uint8_t reserved1[59];
883 	/* 0x3B: EC-Indirect memory address 0 */
884 	volatile uint8_t SMFI_ECINDAR0;
885 	/* 0x3C: EC-Indirect memory address 1 */
886 	volatile uint8_t SMFI_ECINDAR1;
887 	/* 0x3D: EC-Indirect memory address 2 */
888 	volatile uint8_t SMFI_ECINDAR2;
889 	/* 0x3E: EC-Indirect memory address 3 */
890 	volatile uint8_t SMFI_ECINDAR3;
891 	/* 0x3F: EC-Indirect memory data */
892 	volatile uint8_t SMFI_ECINDDR;
893 	/* 0x40: Scratch SRAM 0 address low byte */
894 	volatile uint8_t SMFI_SCAR0L;
895 	/* 0x41: Scratch SRAM 0 address middle byte */
896 	volatile uint8_t SMFI_SCAR0M;
897 	/* 0x42: Scratch SRAM 0 address high byte */
898 	volatile uint8_t SMFI_SCAR0H;
899 	volatile uint8_t reserved1_1[23];
900 	/* 0x5A: Host RAM Window Control */
901 	volatile uint8_t SMFI_HRAMWC;
902 	/* 0x5B: Host RAM Window 0 Base Address [11:4] */
903 	volatile uint8_t SMFI_HRAMW0BA;
904 	/* 0x5C: Host RAM Window 1 Base Address [11:4] */
905 	volatile uint8_t SMFI_HRAMW1BA;
906 	/* 0x5D: Host RAM Window 0 Access Allow Size */
907 	volatile uint8_t SMFI_HRAMW0AAS;
908 	/* 0x5E: Host RAM Window 1 Access Allow Size */
909 	volatile uint8_t SMFI_HRAMW1AAS;
910 	volatile uint8_t reserved2[67];
911 	/* 0xA2: Flash control 6 */
912 	volatile uint8_t SMFI_FLHCTRL6R;
913 	volatile uint8_t reserved3[46];
914 };
915 #endif /* !__ASSEMBLER__ */
916 
917 /* SMFI register fields */
918 /* EC-Indirect read internal flash */
919 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
920 /* Enable EC-indirect page program command */
921 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3)
922 /* Scratch SRAM 0 address(BIT(19)) */
923 #define IT8XXX2_SMFI_SC0A19 BIT(7)
924 /* Scratch SRAM enable */
925 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
926 
927 /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
928 #define SMFI_H2RAMPS           BIT(4)
929 /* H2RAM Window 1 Enable */
930 #define SMFI_H2RAMW1E          BIT(1)
931 /* H2RAM Window 0 Enable */
932 #define SMFI_H2RAMW0E          BIT(0)
933 
934 /* Host RAM Window x Write Protect Enable (All protected) */
935 #define SMFI_HRAMWXWPE_ALL     (BIT(5) | BIT(4))
936 
937 
938 /**
939  *
940  * (16xxh) General Purpose I/O Port (GPIO) registers
941  *
942  */
943 #define GPIO_IT8XXX2_REG_BASE \
944 	((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
945 
946 #ifndef __ASSEMBLER__
947 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
948 struct gpio_it8xxx2_regs {
949 	/* 0x00: General Control */
950 	volatile uint8_t GPIO_GCR;
951 	/* 0x01-D0: Reserved1 */
952 	volatile uint8_t reserved1[208];
953 	/* 0xD1: General Control 25 */
954 	volatile uint8_t GPIO_GCR25;
955 	/* 0xD2: General Control 26 */
956 	volatile uint8_t GPIO_GCR26;
957 	/* 0xD3: General Control 27 */
958 	volatile uint8_t GPIO_GCR27;
959 	/* 0xD4: General Control 28 */
960 	volatile uint8_t GPIO_GCR28;
961 	/* 0xD5: General Control 31 */
962 	volatile uint8_t GPIO_GCR31;
963 	/* 0xD6: General Control 32 */
964 	volatile uint8_t GPIO_GCR32;
965 	/* 0xD7: General Control 33 */
966 	volatile uint8_t GPIO_GCR33;
967 	/* 0xD8-0xDF: Reserved2 */
968 	volatile uint8_t reserved2[8];
969 	/* 0xE0: General Control 16 */
970 	volatile uint8_t GPIO_GCR16;
971 	/* 0xE1: General Control 17 */
972 	volatile uint8_t GPIO_GCR17;
973 	/* 0xE2: General Control 18 */
974 	volatile uint8_t GPIO_GCR18;
975 	/* 0xE3: Reserved3 */
976 	volatile uint8_t reserved3;
977 	/* 0xE4: General Control 19 */
978 	volatile uint8_t GPIO_GCR19;
979 	/* 0xE5: General Control 20 */
980 	volatile uint8_t GPIO_GCR20;
981 	/* 0xE6: General Control 21 */
982 	volatile uint8_t GPIO_GCR21;
983 	/* 0xE7: General Control 22 */
984 	volatile uint8_t GPIO_GCR22;
985 	/* 0xE8: General Control 23 */
986 	volatile uint8_t GPIO_GCR23;
987 	/* 0xE9: General Control 24 */
988 	volatile uint8_t GPIO_GCR24;
989 	/* 0xEA-0xEC: Reserved4 */
990 	volatile uint8_t reserved4[3];
991 	/* 0xED: General Control 30 */
992 	volatile uint8_t GPIO_GCR30;
993 	/* 0xEE: General Control 29 */
994 	volatile uint8_t GPIO_GCR29;
995 	/* 0xEF: Reserved5 */
996 	volatile uint8_t reserved5;
997 	/* 0xF0: General Control 1 */
998 	volatile uint8_t GPIO_GCR1;
999 	/* 0xF1: General Control 2 */
1000 	volatile uint8_t GPIO_GCR2;
1001 	/* 0xF2: General Control 3 */
1002 	volatile uint8_t GPIO_GCR3;
1003 	/* 0xF3: General Control 4 */
1004 	volatile uint8_t GPIO_GCR4;
1005 	/* 0xF4: General Control 5 */
1006 	volatile uint8_t GPIO_GCR5;
1007 	/* 0xF5: General Control 6 */
1008 	volatile uint8_t GPIO_GCR6;
1009 	/* 0xF6: General Control 7 */
1010 	volatile uint8_t GPIO_GCR7;
1011 	/* 0xF7: General Control 8 */
1012 	volatile uint8_t GPIO_GCR8;
1013 	/* 0xF8: General Control 9 */
1014 	volatile uint8_t GPIO_GCR9;
1015 	/* 0xF9: General Control 10 */
1016 	volatile uint8_t GPIO_GCR10;
1017 	/* 0xFA: General Control 11 */
1018 	volatile uint8_t GPIO_GCR11;
1019 	/* 0xFB: General Control 12 */
1020 	volatile uint8_t GPIO_GCR12;
1021 	/* 0xFC: General Control 13 */
1022 	volatile uint8_t GPIO_GCR13;
1023 	/* 0xFD: General Control 14 */
1024 	volatile uint8_t GPIO_GCR14;
1025 	/* 0xFE: General Control 15 */
1026 	volatile uint8_t GPIO_GCR15;
1027 	/* 0xFF: Power Good Watch Control */
1028 	volatile uint8_t GPIO_PGWCR;
1029 };
1030 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
1031 struct gpio_it8xxx2_regs {
1032 	/* 0x00: General Control */
1033 	volatile uint8_t GPIO_GCR;
1034 	/* 0x01-0x0F: Reserved1 */
1035 	volatile uint8_t reserved1[15];
1036 	/* 0x10: General Control 1 */
1037 	volatile uint8_t GPIO_GCR1;
1038 	/* 0x11: General Control 2 */
1039 	volatile uint8_t GPIO_GCR2;
1040 	/* 0x12: General Control 3 */
1041 	volatile uint8_t GPIO_GCR3;
1042 	/* 0x13: General Control 4 */
1043 	volatile uint8_t GPIO_GCR4;
1044 	/* 0x14: General Control 5 */
1045 	volatile uint8_t GPIO_GCR5;
1046 	/* 0x15: General Control 6 */
1047 	volatile uint8_t GPIO_GCR6;
1048 	/* 0x16: General Control 7 */
1049 	volatile uint8_t GPIO_GCR7;
1050 	/* 0x17: General Control 8 */
1051 	volatile uint8_t GPIO_GCR8;
1052 	/* 0x18: General Control 9 */
1053 	volatile uint8_t GPIO_GCR9;
1054 	/* 0x19: General Control 10 */
1055 	volatile uint8_t GPIO_GCR10;
1056 	/* 0x1A: General Control 11 */
1057 	volatile uint8_t GPIO_GCR11;
1058 	/* 0x1B: General Control 12 */
1059 	volatile uint8_t GPIO_GCR12;
1060 	/* 0x1C: General Control 13 */
1061 	volatile uint8_t GPIO_GCR13;
1062 	/* 0x1D: General Control 14 */
1063 	volatile uint8_t GPIO_GCR14;
1064 	/* 0x1E: General Control 15 */
1065 	volatile uint8_t GPIO_GCR15;
1066 	/* 0x1F: Power Good Watch Control */
1067 	volatile uint8_t GPIO_PGWCR;
1068 	/* 0x20: General Control 16 */
1069 	volatile uint8_t GPIO_GCR16;
1070 	/* 0x21: General Control 17 */
1071 	volatile uint8_t GPIO_GCR17;
1072 	/* 0x22: General Control 18 */
1073 	volatile uint8_t GPIO_GCR18;
1074 	/* 0x23: Reserved2 */
1075 	volatile uint8_t reserved2;
1076 	/* 0x24: General Control 19 */
1077 	volatile uint8_t GPIO_GCR19;
1078 	/* 0x25: Reserved3 */
1079 	volatile uint8_t reserved3;
1080 	/* 0x26: General Control 21 */
1081 	volatile uint8_t GPIO_GCR21;
1082 	/* 0x27-0x28: Reserved4 */
1083 	volatile uint8_t reserved4[2];
1084 	/* 0x29: General Control 24 */
1085 	volatile uint8_t GPIO_GCR24;
1086 	/* 0x2A-0x2C: Reserved5 */
1087 	volatile uint8_t reserved5[3];
1088 	/* 0x2D: General Control 30 */
1089 	volatile uint8_t GPIO_GCR30;
1090 	/* 0x2E: General Control 29 */
1091 	volatile uint8_t GPIO_GCR29;
1092 };
1093 
1094 /* GPIO register fields */
1095 /* 0x16: General Control 7 */
1096 #define IT8XXX2_GPIO_SMB2PS                BIT(7)
1097 #define IT8XXX2_GPIO_SMB3PS                BIT(6)
1098 #define IT8XXX2_GPIO_SMB5PS                BIT(5)
1099 
1100 #endif
1101 #endif /* !__ASSEMBLER__ */
1102 
1103 /* GPIO register fields */
1104 /* 0x00: General Control */
1105 #define IT8XXX2_GPIO_LPCRSTEN              (BIT(2) | BIT(1))
1106 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2       0x2
1107 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS      1
1108 #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK  (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
1109 /* 0xF0: General Control 1 */
1110 #define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN  BIT(2)
1111 #define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN  BIT(0)
1112 /* 0xE6: General Control 21 */
1113 #define IT8XXX2_GPIO_GPH1VS                BIT(1)
1114 #define IT8XXX2_GPIO_GPH2VS                BIT(0)
1115 
1116 #define KSIX_KSOX_KBS_GPIO_MODE     BIT(7)
1117 #define KSIX_KSOX_GPIO_OUTPUT       BIT(6)
1118 #define KSIX_KSOX_GPIO_PULLUP       BIT(2)
1119 #define KSIX_KSOX_GPIO_PULLDOWN     BIT(1)
1120 
1121 #define GPCR_PORT_PIN_MODE_INPUT    BIT(7)
1122 #define GPCR_PORT_PIN_MODE_OUTPUT   BIT(6)
1123 #define GPCR_PORT_PIN_MODE_PULLUP   BIT(2)
1124 #define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
1125 
1126 /*
1127  * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
1128  * configured as tri-state.
1129  */
1130 #define GPCR_PORT_PIN_MODE_TRISTATE	(GPCR_PORT_PIN_MODE_INPUT |  \
1131 					 GPCR_PORT_PIN_MODE_PULLUP | \
1132 					 GPCR_PORT_PIN_MODE_PULLDOWN)
1133 
1134 /* --- GPIO --- */
1135 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
1136 #define IT8XXX2_GPIO_BASE  0x00F01600
1137 
1138 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
1139 #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
1140 #define IT8XXX2_GPIO_GCR26_OFFSET 0xd2
1141 #define IT8XXX2_GPIO_GCR27_OFFSET 0xd3
1142 #define IT8XXX2_GPIO_GCR28_OFFSET 0xd4
1143 #define IT8XXX2_GPIO_GCR31_OFFSET 0xd5
1144 #define IT8XXX2_GPIO_GCR32_OFFSET 0xd6
1145 #define IT8XXX2_GPIO_GCR33_OFFSET 0xd7
1146 #define IT8XXX2_GPIO_GCR19_OFFSET 0xe4
1147 #define IT8XXX2_GPIO_GCR20_OFFSET 0xe5
1148 #define IT8XXX2_GPIO_GCR21_OFFSET 0xe6
1149 #define IT8XXX2_GPIO_GCR22_OFFSET 0xe7
1150 #define IT8XXX2_GPIO_GCR23_OFFSET 0xe8
1151 #define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
1152 #define IT8XXX2_GPIO_GCR30_OFFSET 0xed
1153 #define IT8XXX2_GPIO_GCR29_OFFSET 0xee
1154 #endif
1155 
1156 /*
1157  * TODO: use pinctrl node instead of following register declarations
1158  *       to fix in tcpm\it83xx_pd.h.
1159  */
1160 #define IT8XXX2_GPIO2_BASE 0x00F03E00
1161 
1162 #define IT8XXX2_GPIO_GPCRP0     ECREG(IT8XXX2_GPIO2_BASE + 0x18)
1163 #define IT8XXX2_GPIO_GPCRP1     ECREG(IT8XXX2_GPIO2_BASE + 0x19)
1164 
1165 
1166 /**
1167  *
1168  * (19xxh) Analog to Digital Converter (ADC) registers
1169  *
1170  */
1171 #ifndef __ASSEMBLER__
1172 
1173 /* Data structure to define ADC channel 13-16 control registers. */
1174 struct adc_vchs_ctrl_t {
1175 	/* 0x60: Voltage Channel Control */
1176 	volatile uint8_t VCHCTL;
1177 	/* 0x61: Voltage Channel Data Buffer MSB */
1178 	volatile uint8_t VCHDATM;
1179 	/* 0x62: Voltage Channel Data Buffer LSB */
1180 	volatile uint8_t VCHDATL;
1181 };
1182 
1183 struct adc_it8xxx2_regs {
1184 	/* 0x00: ADC Status */
1185 	volatile uint8_t ADCSTS;
1186 	/* 0x01: ADC Configuration */
1187 	volatile uint8_t ADCCFG;
1188 	/* 0x02: ADC Clock Control */
1189 	volatile uint8_t ADCCTL;
1190 	/* 0x03: General Control */
1191 	volatile uint8_t ADCGCR;
1192 	/* 0x04: Voltage Channel 0 Control */
1193 	volatile uint8_t VCH0CTL;
1194 	/* 0x05: Calibration Data Control */
1195 	volatile uint8_t KDCTL;
1196 	/* 0x06-0x17: Reserved1 */
1197 	volatile uint8_t reserved1[18];
1198 	/* 0x18: Voltage Channel 0 Data Buffer LSB */
1199 	volatile uint8_t VCH0DATL;
1200 	/* 0x19: Voltage Channel 0 Data Buffer MSB */
1201 	volatile uint8_t VCH0DATM;
1202 	/* 0x1a-0x43: Reserved2 */
1203 	volatile uint8_t reserved2[42];
1204 	/* 0x44: ADC Data Valid Status */
1205 	volatile uint8_t ADCDVSTS;
1206 	/* 0x45-0x54: Reserved2-1 */
1207 	volatile uint8_t reserved2_1[16];
1208 	/* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
1209 	volatile uint8_t ADCIVMFSCS1;
1210 	/* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
1211 	volatile uint8_t ADCIVMFSCS2;
1212 	/* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
1213 	volatile uint8_t ADCIVMFSCS3;
1214 	/* 0x58-0x5f: Reserved3 */
1215 	volatile uint8_t reserved3[8];
1216 	/* 0x60-0x6b: ADC channel 13~16 controller */
1217 	struct adc_vchs_ctrl_t adc_vchs_ctrl[4];
1218 	/* 0x6c: ADC Data Valid Status 2 */
1219 	volatile uint8_t ADCDVSTS2;
1220 	/* 0x6d-0xef: Reserved4 */
1221 	volatile uint8_t reserved4[131];
1222 	/* 0xf0: ADC Clock Control Register 1 */
1223 	volatile uint8_t ADCCTL1;
1224 };
1225 #endif /* !__ASSEMBLER__ */
1226 
1227 /* ADC conversion time select 1 */
1228 #define IT8XXX2_ADC_ADCCTS1			BIT(7)
1229 /* Analog accuracy initialization */
1230 #define IT8XXX2_ADC_AINITB			BIT(3)
1231 /* ADC conversion time select 0 */
1232 #define IT8XXX2_ADC_ADCCTS0			BIT(5)
1233 /* ADC module enable */
1234 #define IT8XXX2_ADC_ADCEN			BIT(0)
1235 /* ADC data buffer keep enable */
1236 #define IT8XXX2_ADC_DBKEN			BIT(7)
1237 /* W/C data valid flag */
1238 #define IT8XXX2_ADC_DATVAL			BIT(7)
1239 /* Data valid interrupt of adc */
1240 #define IT8XXX2_ADC_INTDVEN			BIT(5)
1241 /* Voltage channel enable (Channel 4~7 and 13~16) */
1242 #define IT8XXX2_ADC_VCHEN			BIT(4)
1243 /* Automatic hardware calibration enable */
1244 #define IT8XXX2_ADC_AHCE			BIT(7)
1245 /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */
1246 #define IT8XXX2_VCMP_CMPEN			BIT(7)
1247 #define IT8XXX2_VCMP_CMPINTEN			BIT(6)
1248 #define IT8XXX2_VCMP_GREATER_THRESHOLD		BIT(5)
1249 #define IT8XXX2_VCMP_EDGE_TRIGGER		BIT(4)
1250 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW		BIT(3)
1251 /* 0x077~0x07c: Voltage comparator x channel select MSB */
1252 #define IT8XXX2_VCMP_VCMPXCSELM			BIT(0)
1253 
1254 /**
1255  *
1256  * (1Exxh) Clock and Power Management (ECPM) registers
1257  *
1258  */
1259 #define IT8XXX2_ECPM_BASE  0x00F01E00
1260 
1261 #ifndef __ASSEMBLER__
1262 enum chip_pll_mode {
1263 	CHIP_PLL_DOZE = 0,
1264 	CHIP_PLL_SLEEP = 1,
1265 	CHIP_PLL_DEEP_DOZE = 3,
1266 };
1267 #endif
1268 /*
1269  * TODO: use ecpm_it8xxx2_regs instead of following register declarations
1270  *       to fix in soc.c.
1271  */
1272 #define IT8XXX2_ECPM_PLLCTRL    ECREG(IT8XXX2_ECPM_BASE + 0x03)
1273 #define IT8XXX2_ECPM_AUTOCG     ECREG(IT8XXX2_ECPM_BASE + 0x04)
1274 #define IT8XXX2_ECPM_CGCTRL3R   ECREG(IT8XXX2_ECPM_BASE + 0x05)
1275 #define IT8XXX2_ECPM_PLLFREQR   ECREG(IT8XXX2_ECPM_BASE + 0x06)
1276 #define IT8XXX2_ECPM_PLLCSS     ECREG(IT8XXX2_ECPM_BASE + 0x08)
1277 #define IT8XXX2_ECPM_SCDCR0     ECREG(IT8XXX2_ECPM_BASE + 0x0c)
1278 #define IT8XXX2_ECPM_SCDCR1     ECREG(IT8XXX2_ECPM_BASE + 0x0d)
1279 #define IT8XXX2_ECPM_SCDCR2     ECREG(IT8XXX2_ECPM_BASE + 0x0e)
1280 #define IT8XXX2_ECPM_SCDCR3     ECREG(IT8XXX2_ECPM_BASE + 0x0f)
1281 #define IT8XXX2_ECPM_SCDCR4     ECREG(IT8XXX2_ECPM_BASE + 0x10)
1282 #define IT8XXX2_ECPM_PFACC0R    ECREG(IT8XXX2_ECPM_BASE + 0x20)
1283 #define IT8XXX2_ECPM_PFACC1R    ECREG(IT8XXX2_ECPM_BASE + 0x21)
1284 #define IT8XXX2_ECPM_PFACC2R    ECREG(IT8XXX2_ECPM_BASE + 0x40)
1285 #define IT8XXX2_ECPM_LCOTF2     ECREG(IT8XXX2_ECPM_BASE + 0x54)
1286 #define IT8XXX2_ECPM_LCOCR      ECREG(IT8XXX2_ECPM_BASE + 0x55)
1287 #define IT8XXX2_ECPM_LCOCR1     ECREG(IT8XXX2_ECPM_BASE + 0x57)
1288 
1289 /*
1290  * The count number of the counter for 25 ms register.
1291  * The 25 ms register is calculated by (count number *1.024 kHz).
1292  */
1293 
1294 #define I2C_CLK_LOW_TIMEOUT		255 /* ~=249 ms */
1295 
1296 /**
1297  *
1298  * (1Cxxh) SMBus Interface (SMB) registers
1299  *
1300  */
1301 #define IT8XXX2_SMB_BASE            0x00F01C00
1302 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
1303 #define IT8XXX2_SMB_4P7USL          ECREG(IT8XXX2_SMB_BASE + 0x00)
1304 #define IT8XXX2_SMB_4P0USL          ECREG(IT8XXX2_SMB_BASE + 0x01)
1305 #define IT8XXX2_SMB_300NS           ECREG(IT8XXX2_SMB_BASE + 0x02)
1306 #define IT8XXX2_SMB_250NS           ECREG(IT8XXX2_SMB_BASE + 0x03)
1307 #define IT8XXX2_SMB_25MS            ECREG(IT8XXX2_SMB_BASE + 0x04)
1308 #define IT8XXX2_SMB_45P3USL         ECREG(IT8XXX2_SMB_BASE + 0x05)
1309 #define IT8XXX2_SMB_45P3USH         ECREG(IT8XXX2_SMB_BASE + 0x06)
1310 #define IT8XXX2_SMB_4P7A4P0H        ECREG(IT8XXX2_SMB_BASE + 0x07)
1311 #define IT8XXX2_SMB_SLVISELR        ECREG(IT8XXX2_SMB_BASE + 0x08)
1312 #define IT8XXX2_SMB_SCLKTS(ch)      ECREG(IT8XXX2_SMB_BASE + 0x09 + ch)
1313 #define IT8XXX2_SMB_MSTFCTRL1       ECREG(IT8XXX2_SMB_BASE + 0x0D)
1314 #define IT8XXX2_SMB_MSTFSTS1        ECREG(IT8XXX2_SMB_BASE + 0x0E)
1315 #define IT8XXX2_SMB_MSTFCTRL2       ECREG(IT8XXX2_SMB_BASE + 0x0F)
1316 #define IT8XXX2_SMB_MSTFSTS2        ECREG(IT8XXX2_SMB_BASE + 0x10)
1317 #define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x11)
1318 #define IT8XXX2_SMB_I2CW2RF         ECREG(IT8XXX2_SMB_BASE + 0x12)
1319 #define IT8XXX2_SMB_IWRFISTA        ECREG(IT8XXX2_SMB_BASE + 0x13)
1320 #define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x20)
1321 #define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x21)
1322 #define IT8XXX2_SMB_SFFCTL          ECREG(IT8XXX2_SMB_BASE + 0x55)
1323 #define IT8XXX2_SMB_HOSTA(base)     ECREG(base + 0x00)
1324 #define IT8XXX2_SMB_HOCTL(base)     ECREG(base + 0x01)
1325 #define IT8XXX2_SMB_HOCMD(base)     ECREG(base + 0x02)
1326 #define IT8XXX2_SMB_TRASLA(base)    ECREG(base + 0x03)
1327 #define IT8XXX2_SMB_D0REG(base)     ECREG(base + 0x04)
1328 #define IT8XXX2_SMB_D1REG(base)     ECREG(base + 0x05)
1329 #define IT8XXX2_SMB_HOBDB(base)     ECREG(base + 0x06)
1330 #define IT8XXX2_SMB_PECERC(base)    ECREG(base + 0x07)
1331 #define IT8XXX2_SMB_SMBPCTL(base)   ECREG(base + 0x0A)
1332 #define IT8XXX2_SMB_HOCTL2(base)    ECREG(base + 0x10)
1333 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
1334 #define IT8XXX2_SMB_SLVISEL         ECREG(IT8XXX2_SMB_BASE + 0x08)
1335 #define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x09)
1336 #define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x0A)
1337 #define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x0B)
1338 #define IT8XXX2_SMB_SCLKTS_BRGS     ECREG(IT8XXX2_SMB_BASE + 0x80)
1339 #define IT8XXX2_SMB_SCLKTS_BRGM     ECREG(IT8XXX2_SMB_BASE + 0x81)
1340 #define IT8XXX2_SMB_CHSBRG          ECREG(IT8XXX2_SMB_BASE + 0x82)
1341 #define IT8XXX2_SMB_CHSMOT          ECREG(IT8XXX2_SMB_BASE + 0x83)
1342 
1343 /* SMBus register fields */
1344 /* 0x80: SMCLK Timing Setting Register Bridge Slave */
1345 #define IT8XXX2_SMB_PREDEN            BIT(7)
1346 #endif
1347 
1348 /**
1349  * Enhanced SMBus/I2C Interface
1350  * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580
1351  * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01
1352  */
1353 #define IT8XXX2_I2C_DRR(base)         ECREG(base + 0x00)
1354 #define IT8XXX2_I2C_PSR(base)         ECREG(base + 0x01)
1355 #define IT8XXX2_I2C_HSPR(base)        ECREG(base + 0x02)
1356 #define IT8XXX2_I2C_STR(base)         ECREG(base + 0x03)
1357 #define IT8XXX2_I2C_DHTR(base)        ECREG(base + 0x04)
1358 #define IT8XXX2_I2C_TOR(base)         ECREG(base + 0x05)
1359 #define IT8XXX2_I2C_DTR(base)         ECREG(base + 0x08)
1360 #define IT8XXX2_I2C_CTR(base)         ECREG(base + 0x09)
1361 #define IT8XXX2_I2C_CTR1(base)        ECREG(base + 0x0A)
1362 #define IT8XXX2_I2C_BYTE_CNT_H(base)  ECREG(base + 0x0B)
1363 #define IT8XXX2_I2C_BYTE_CNT_L(base)  ECREG(base + 0x0C)
1364 #define IT8XXX2_I2C_IRQ_ST(base)      ECREG(base + 0x0D)
1365 #define IT8XXX2_I2C_IDR(base)         ECREG(base + 0x06)
1366 #define IT8XXX2_I2C_TOS(base)         ECREG(base + 0x07)
1367 #define IT8XXX2_I2C_SLV_NUM_H(base)   ECREG(base + 0x10)
1368 #define IT8XXX2_I2C_SLV_NUM_L(base)   ECREG(base + 0x11)
1369 #define IT8XXX2_I2C_STR2(base)        ECREG(base + 0x12)
1370 #define IT8XXX2_I2C_NST(base)         ECREG(base + 0x13)
1371 #define IT8XXX2_I2C_TO_ARB_ST(base)   ECREG(base + 0x18)
1372 #define IT8XXX2_I2C_ERR_ST(base)      ECREG(base + 0x19)
1373 #define IT8XXX2_I2C_FST(base)         ECREG(base + 0x1B)
1374 #define IT8XXX2_I2C_EM(base)          ECREG(base + 0x1C)
1375 #define IT8XXX2_I2C_MODE_SEL(base)    ECREG(base + 0x1D)
1376 #define IT8XXX2_I2C_IDR2(base)        ECREG(base + 0x1F)
1377 #define IT8XXX2_I2C_CTR2(base)        ECREG(base + 0x20)
1378 #define IT8XXX2_I2C_RAMHA(base)       ECREG(base + 0x23)
1379 #define IT8XXX2_I2C_RAMLA(base)       ECREG(base + 0x24)
1380 #define IT8XXX2_I2C_RAMHA2(base)      ECREG(base + 0x2C)
1381 #define IT8XXX2_I2C_RAMLA2(base)      ECREG(base + 0x2D)
1382 #define IT8XXX2_I2C_CMD_ADDH(base)    ECREG(base + 0x25)
1383 #define IT8XXX2_I2C_CMD_ADDL(base)    ECREG(base + 0x26)
1384 #define IT8XXX2_I2C_RAMH2A(base)      ECREG(base + 0x50)
1385 #define IT8XXX2_I2C_CMD_ADDH2(base)   ECREG(base + 0x52)
1386 
1387 /* SMBus/I2C register fields */
1388 /* 0x09-0xB: SMCLK Timing Setting */
1389 #define IT8XXX2_SMB_SMCLKS_1M         4
1390 #define IT8XXX2_SMB_SMCLKS_400K       3
1391 #define IT8XXX2_SMB_SMCLKS_100K       2
1392 #define IT8XXX2_SMB_SMCLKS_50K        1
1393 
1394 /* 0x0E: SMBus FIFO Status 1 */
1395 #define IT8XXX2_SMB_FIFO1_EMPTY       BIT(7)
1396 #define IT8XXX2_SMB_FIFO1_FULL        BIT(6)
1397 /* 0x0D: SMBus FIFO Control 1 */
1398 /* 0x0F: SMBus FIFO Control 2 */
1399 #define IT8XXX2_SMB_BLKDS             BIT(4)
1400 #define IT8XXX2_SMB_FFEN              BIT(3)
1401 #define IT8XXX2_SMB_FFCHSEL2_B        0
1402 #define IT8XXX2_SMB_FFCHSEL2_C        BIT(0)
1403 /* 0x10: SMBus FIFO Status 2 */
1404 #define IT8XXX2_SMB_FIFO2_EMPTY       BIT(7)
1405 #define IT8XXX2_SMB_FIFO2_FULL        BIT(6)
1406 /* 0x12: I2C Wr To Rd FIFO */
1407 #define IT8XXX2_SMB_MAIF              BIT(7)
1408 #define IT8XXX2_SMB_MBCIF             BIT(6)
1409 #define IT8XXX2_SMB_MCIFI             BIT(2)
1410 #define IT8XXX2_SMB_MBIFI             BIT(1)
1411 #define IT8XXX2_SMB_MAIFI             BIT(0)
1412 /* 0x13: I2C Wr To Rd FIFO Interrupt Status */
1413 #define IT8XXX2_SMB_MCIFID            BIT(2)
1414 #define IT8XXX2_SMB_MAIFID            BIT(0)
1415 /* 0x41 0x81 0xC1: Host Control */
1416 #define IT8XXX2_SMB_SRT               BIT(6)
1417 #define IT8XXX2_SMB_LABY              BIT(5)
1418 #define IT8XXX2_SMB_SMCD_EXTND        BIT(4) | BIT(3) | BIT(2)
1419 #define IT8XXX2_SMB_KILL              BIT(1)
1420 #define IT8XXX2_SMB_INTREN            BIT(0)
1421 /* 0x43 0x83 0xC3: Transmit Slave Address */
1422 #define IT8XXX2_SMB_DIR               BIT(0)
1423 /* 0x4A 0x8A 0xCA: SMBus Pin Control */
1424 #define IT8XXX2_SMB_SMBDCS            BIT(1)
1425 #define IT8XXX2_SMB_SMBCS             BIT(0)
1426 /* 0x50 0x90 0xD0: Host Control 2 */
1427 #define IT8XXX2_SMB_SMD_TO_EN         BIT(4)
1428 #define IT8XXX2_SMB_I2C_SW_EN         BIT(3)
1429 #define IT8XXX2_SMB_I2C_SW_WAIT       BIT(2)
1430 #define IT8XXX2_SMB_I2C_EN            BIT(1)
1431 #define IT8XXX2_SMB_SMHEN             BIT(0)
1432 /* 0x55: Slave A FIFO Control */
1433 #define IT8XXX2_SMB_HSAPE             BIT(1)
1434 /* 0x03: Status Register */
1435 #define IT8XXX2_I2C_BYTE_DONE         BIT(7)
1436 #define IT8XXX2_I2C_RW                BIT(2)
1437 #define IT8XXX2_I2C_INT_PEND          BIT(1)
1438 /* 0x04: Data Hold Time */
1439 #define IT8XXX2_I2C_SOFT_RST          BIT(7)
1440 /* 0x07: Time Out Status */
1441 #define IT8XXX2_I2C_CLK_STRETCH       BIT(7)
1442 #define IT8XXX2_I2C_SCL_IN            BIT(2)
1443 #define IT8XXX2_I2C_SDA_IN            BIT(0)
1444 /* 0x09: Control Register */
1445 #define IT8XXX2_I2C_INT_EN            BIT(6)
1446 #define IT8XXX2_I2C_ACK               BIT(3)
1447 #define IT8XXX2_I2C_HALT              BIT(0)
1448 /* 0x0A: Control 1 */
1449 #define IT8XXX2_I2C_COMQ_EN           BIT(7)
1450 #define IT8XXX2_I2C_MDL_EN            BIT(1)
1451 /* 0x0C: Byte count */
1452 #define IT8XXX2_I2C_DMA_ADDR_RELOAD   BIT(5)
1453 #define IT8XXX2_I2C_BYTE_CNT_ENABLE   BIT(3)
1454 /* 0x0D: Interrupt Status */
1455 #define IT8XXX2_I2C_CNT_HOLD          BIT(4)
1456 #define IT8XXX2_I2C_IDW_CLR           BIT(3)
1457 #define IT8XXX2_I2C_IDR_CLR           BIT(2)
1458 #define IT8XXX2_I2C_SLVDATAFLG        BIT(1)
1459 #define IT8XXX2_I2C_P_CLR             BIT(0)
1460 /* 0x13: Nack Status */
1461 #define IT8XXX2_I2C_NST_CNS           BIT(7)
1462 #define IT8XXX2_I2C_NST_ID_NACK       BIT(3)
1463 /* 0x18: Timeout and Arbiter Status */
1464 #define IT8XXX2_I2C_SCL_TIMEOUT_EN    BIT(7)
1465 #define IT8XXX2_I2C_SDA_TIMEOUT_EN    BIT(6)
1466 /* 0x19: Error Status */
1467 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ  BIT(0)
1468 /* 0x1B: Finish Status */
1469 #define IT8XXX2_I2C_FST_DEV1_IRQ      BIT(4)
1470 /* 0x1C: Error Mask */
1471 #define IT8XXX2_I2C_EM_DEV1_IRQ       BIT(4)
1472 
1473 /*
1474  * TODO: use gctrl_it8xxx2_regs instead of following register declarations
1475  *       to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c.
1476  */
1477 /* --- General Control (GCTRL) --- */
1478 #define IT83XX_GCTRL_BASE 0x00F02000
1479 
1480 #define IT83XX_GCTRL_CHIPID1         ECREG(IT83XX_GCTRL_BASE + 0x85)
1481 #define IT83XX_GCTRL_CHIPID2         ECREG(IT83XX_GCTRL_BASE + 0x86)
1482 #define IT83XX_GCTRL_CHIPVER         ECREG(IT83XX_GCTRL_BASE + 0x02)
1483 #define IT83XX_GCTRL_MCCR3           ECREG(IT83XX_GCTRL_BASE + 0x20)
1484 #define IT83XX_GCTRL_SPISLVPFE             BIT(6)
1485 #define IT83XX_GCTRL_EWPR0PFH(i)     ECREG(IT83XX_GCTRL_BASE + 0x60 + i)
1486 #define IT83XX_GCTRL_EWPR0PFD(i)     ECREG(IT83XX_GCTRL_BASE + 0xA0 + i)
1487 #define IT83XX_GCTRL_EWPR0PFEC(i)    ECREG(IT83XX_GCTRL_BASE + 0xC0 + i)
1488 
1489 /*
1490  * TODO: use spisc_it8xxx2_regs instead of following register declarations
1491  *       to fix in cros_shi_it8xxx2.c.
1492  */
1493 /* Serial Peripheral Interface (SPI) */
1494 #define IT83XX_SPI_BASE  0x00F03A00
1495 
1496 #define IT83XX_SPI_SPISGCR           ECREG(IT83XX_SPI_BASE + 0x00)
1497 #define IT83XX_SPI_SPISCEN                 BIT(0)
1498 #define IT83XX_SPI_TXRXFAR           ECREG(IT83XX_SPI_BASE + 0x01)
1499 #define IT83XX_SPI_CPURXF2A                BIT(4)
1500 #define IT83XX_SPI_CPURXF1A                BIT(3)
1501 #define IT83XX_SPI_CPUTFA                  BIT(1)
1502 #define IT83XX_SPI_TXFCR             ECREG(IT83XX_SPI_BASE + 0x02)
1503 #define IT83XX_SPI_TXFCMR                  BIT(2)
1504 #define IT83XX_SPI_TXFR                    BIT(1)
1505 #define IT83XX_SPI_TXFS                    BIT(0)
1506 #define IT83XX_SPI_GCR2              ECREG(IT83XX_SPI_BASE + 0x03)
1507 #define IT83XX_SPI_RXF2OC                  BIT(4)
1508 #define IT83XX_SPI_RXF1OC                  BIT(3)
1509 #define IT83XX_SPI_RXFAR                   BIT(0)
1510 #define IT83XX_SPI_IMR               ECREG(IT83XX_SPI_BASE + 0x04)
1511 #define IT83XX_SPI_RX_FIFO_FULL            BIT(7)
1512 #define IT83XX_SPI_RX_REACH                BIT(5)
1513 #define IT83XX_SPI_EDIM                    BIT(2)
1514 #define IT83XX_SPI_ISR               ECREG(IT83XX_SPI_BASE + 0x05)
1515 #define IT83XX_SPI_TXFSR             ECREG(IT83XX_SPI_BASE + 0x06)
1516 #define IT83XX_SPI_ENDDETECTINT            BIT(2)
1517 #define IT83XX_SPI_RXFSR             ECREG(IT83XX_SPI_BASE + 0x07)
1518 #define IT83XX_SPI_RXFFSM                  (BIT(4) | BIT(3))
1519 #define IT83XX_SPI_RXF2FS                  BIT(2)
1520 #define IT83XX_SPI_RXF1FS                  BIT(1)
1521 #define IT83XX_SPI_SPISRDR           ECREG(IT83XX_SPI_BASE + 0x0b)
1522 #define IT83XX_SPI_CPUWTFDB0         ECREG_u32(IT83XX_SPI_BASE + 0x08)
1523 #define IT83XX_SPI_FCR               ECREG(IT83XX_SPI_BASE + 0x09)
1524 #define IT83XX_SPI_SPISRTXF                BIT(2)
1525 #define IT83XX_SPI_RXFR                    BIT(1)
1526 #define IT83XX_SPI_RXFCMR                  BIT(0)
1527 #define IT83XX_SPI_RXFRDRB0          ECREG_u32(IT83XX_SPI_BASE + 0x0C)
1528 #define IT83XX_SPI_FTCB0R            ECREG(IT83XX_SPI_BASE + 0x18)
1529 #define IT83XX_SPI_FTCB1R            ECREG(IT83XX_SPI_BASE + 0x19)
1530 #define IT83XX_SPI_TCCB0             ECREG(IT83XX_SPI_BASE + 0x1A)
1531 #define IT83XX_SPI_TCCB1             ECREG(IT83XX_SPI_BASE + 0x1B)
1532 #define IT83XX_SPI_HPR2              ECREG(IT83XX_SPI_BASE + 0x1E)
1533 #define IT83XX_SPI_EMMCBMR           ECREG(IT83XX_SPI_BASE + 0x21)
1534 #define IT83XX_SPI_EMMCABM                 BIT(1) /* eMMC Alternative Boot Mode */
1535 #define IT83XX_SPI_RX_VLISMR         ECREG(IT83XX_SPI_BASE + 0x26)
1536 #define IT83XX_SPI_RVLIM                   BIT(0)
1537 #define IT83XX_SPI_RX_VLISR          ECREG(IT83XX_SPI_BASE + 0x27)
1538 #define IT83XX_SPI_RVLI                    BIT(0)
1539 
1540 /**
1541  *
1542  * (20xxh) General Control (GCTRL) registers
1543  *
1544  */
1545 #define GCTRL_IT8XXX2_REGS_BASE \
1546 	((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
1547 
1548 #ifndef __ASSEMBLER__
1549 struct gctrl_it8xxx2_regs {
1550 	/* 0x00-0x01: Reserved_00_01 */
1551 	volatile uint8_t reserved_00_01[2];
1552 	/* 0x02: Chip Version */
1553 	volatile uint8_t GCTRL_ECHIPVER;
1554 	/* 0x03: DBGR Operate Status */
1555 	volatile uint8_t GCTRL_DBGROS;
1556 	/* 0x04-0x05: Reserved_04_05 */
1557 	volatile uint8_t reserved_04_05[2];
1558 	/* 0x06: Reset Status */
1559 	volatile uint8_t GCTRL_RSTS;
1560 	/* 0x07-0x09: Reserved_07_09 */
1561 	volatile uint8_t reserved_07_09[3];
1562 	/* 0x0A: Base Address Select */
1563 	volatile uint8_t GCTRL_BADRSEL;
1564 	/* 0x0B: Wait Next Clock Rising */
1565 	volatile uint8_t GCTRL_WNCKR;
1566 	/* 0x0C: reserved_0c */
1567 	volatile uint8_t reserved_0c;
1568 	/* 0x0D: Special Control 1 */
1569 	volatile uint8_t GCTRL_SPCTRL1;
1570 	/* 0x0E-0x0F: reserved_0e_0f */
1571 	volatile uint8_t reserved_0e_0f[2];
1572 	/* 0x10: Reset Control DMM */
1573 	volatile uint8_t GCTRL_RSTDMMC;
1574 	/* 0x11: Reset Control 4 */
1575 	volatile uint8_t GCTRL_RSTC4;
1576 	/* 0x12-0x1B: reserved_12_1b */
1577 	volatile uint8_t reserved_12_1b[10];
1578 	/* 0x1C: Special Control 4 */
1579 	volatile uint8_t GCTRL_SPCTRL4;
1580 	/* 0x1D-0x1F: reserved_1d_1f */
1581 	volatile uint8_t reserved_1d_1f[3];
1582 	/* 0x20: Memory Controller Configuration 3 */
1583 	volatile uint8_t GCTRL_MCCR3;
1584 	/* 0x21: Reset Control 5 */
1585 	volatile uint8_t GCTRL_RSTC5;
1586 	/* 0x22-0x2F: reserved_22_2f */
1587 	volatile uint8_t reserved_22_2f[14];
1588 	/* 0x30: Memory Controller Configuration */
1589 	volatile uint8_t GCTRL_MCCR;
1590 	/* 0x31: Externel ILM/DLM Size */
1591 	volatile uint8_t GCTRL_EIDSR;
1592 	/* 0x32: Reserved_32 */
1593 	volatile uint8_t reserved_32;
1594 	/* 0x33: Pin Multi-function Enable 2 */
1595 	volatile uint8_t gctrl_pmer2;
1596 	/* 0x34-0x36: Reserved_34_36 */
1597 	volatile uint8_t reserved_34_36[3];
1598 	/* 0x37: Eflash Protect Lock */
1599 	volatile uint8_t GCTRL_EPLR;
1600 	/* 0x38-0x40: Reserved_38_40 */
1601 	volatile uint8_t reserved_38_40[9];
1602 	/* 0x41: Interrupt Vector Table Base Address */
1603 	volatile uint8_t GCTRL_IVTBAR;
1604 	/* 0x42-0x43: Reserved_42_43 */
1605 	volatile uint8_t reserved_42_43[2];
1606 	/* 0x44: Memory Controller Configuration 2 */
1607 	volatile uint8_t GCTRL_MCCR2;
1608 	/* 0x45: Reserved_45 */
1609 	volatile uint8_t reserved_45;
1610 	/* 0x46: Pin Multi-function Enable 3 */
1611 	volatile uint8_t GCTRL_PMER3;
1612 	/* 0x47-0x4A: reserved_47_4a */
1613 	volatile uint8_t reserved_47_4a[4];
1614 	/* 0x4B: ETWD and UART Control */
1615 	volatile uint8_t GCTRL_ETWDUARTCR;
1616 	/* 0x4C: Wakeup MCU Control */
1617 	volatile uint8_t GCTRL_WMCR;
1618 	/* 0x4D-0x4F: reserved_4d_4f */
1619 	volatile uint8_t reserved_4d_4f[3];
1620 	/* 0x50: Port 80h/81h Status Register */
1621 	volatile uint8_t GCTRL_P80H81HSR;
1622 	/* 0x51: Port 80h Data Register */
1623 	volatile uint8_t GCTRL_P80HDR;
1624 	/* 0x52: Port 81h Data Register */
1625 	volatile uint8_t GCTRL_P81HDR;
1626 	/* 0x53: H2RAM Offset Register */
1627 	volatile uint8_t GCTRL_H2ROFSR;
1628 	/* 0x54-0x5C: reserved_54_5c */
1629 	volatile uint8_t reserved_54_5c[9];
1630 	/* 0x5D: RISCV ILM Configuration 0 */
1631 	volatile uint8_t GCTRL_RVILMCR0;
1632 	/* 0x5E-0x84: reserved_5e_84 */
1633 	volatile uint8_t reserved_5e_84[39];
1634 	/* 0x85: Chip ID Byte 1 */
1635 	volatile uint8_t GCTRL_ECHIPID1;
1636 	/* 0x86: Chip ID Byte 2 */
1637 	volatile uint8_t GCTRL_ECHIPID2;
1638 	/* 0x87: Chip ID Byte 3 */
1639 	volatile uint8_t GCTRL_ECHIPID3;
1640 };
1641 #endif /* !__ASSEMBLER__ */
1642 
1643 /* GCTRL register fields */
1644 /* 0x03: DBGR Operate Status */
1645 #define IT8XXX2_GCTRL_SMB_DBGR		BIT(0)
1646 /* 0x06: Reset Status */
1647 #define IT8XXX2_GCTRL_LRS		(BIT(1) | BIT(0))
1648 #define IT8XXX2_GCTRL_IWDTR		BIT(1)
1649 /* 0x0B: Wait Next 65K Rising */
1650 #define IT8XXX2_GCTRL_WN65K		0x00
1651 /* 0x10: Reset Control DMM */
1652 #define IT8XXX2_GCTRL_UART1SD		BIT(3)
1653 #define IT8XXX2_GCTRL_UART2SD		BIT(2)
1654 /* 0x11: Reset Control 4 */
1655 #define IT8XXX2_GCTRL_RPECI		BIT(4)
1656 #define IT8XXX2_GCTRL_RUART2		BIT(2)
1657 #define IT8XXX2_GCTRL_RUART1		BIT(1)
1658 /* 0x1C: Special Control 4 */
1659 #define IT8XXX2_GCTRL_LRSIWR		BIT(2)
1660 #define IT8XXX2_GCTRL_LRSIPWRSWTR	BIT(1)
1661 #define IT8XXX2_GCTRL_LRSIPGWR		BIT(0)
1662 /* 0x20: Memory Controller Configuration 3 */
1663 #define IT8XXX2_GCTRL_SPISLVPFE		BIT(6)
1664 /* 0x30: Memory Controller Configuration */
1665 #define IT8XXX2_GCTRL_USB_DEBUG_EN      BIT(7)
1666 #define IT8XXX2_GCTRL_ICACHE_RESET	BIT(4)
1667 /* 0x37: Eflash Protect Lock */
1668 #define IT8XXX2_GCTRL_EPLR_ENABLE	BIT(0)
1669 /* 0x46: Pin Multi-function Enable 3 */
1670 #define IT8XXX2_GCTRL_SMB3PSEL		BIT(6)
1671 #define IT8XXX2_GCTRL_SRAM_CRYPTO_USED	BIT(5)
1672 /* 0x4B: ETWD and UART Control */
1673 #define IT8XXX2_GCTRL_ETWD_HW_RST_EN	BIT(0)
1674 /* 0x5D: RISCV ILM Configuration 0 */
1675 #define IT8XXX2_GCTRL_ILM0_ENABLE	BIT(0)
1676 /* Accept Port 80h Cycle */
1677 #define IT8XXX2_GCTRL_ACP80		BIT(6)
1678 /* Accept Port 81h Cycle */
1679 #define IT8XXX2_GCTRL_ACP81		BIT(3)
1680 /* USB Debug Enable */
1681 #define IT8XXX2_GCTRL_MCCR_USB_EN	BIT(7)
1682 /* USB Pad Power-On Enable */
1683 #define IT8XXX2_GCTRL_PMER2_USB_PAD_EN	BIT(7)
1684 
1685 /*
1686  * VCC Detector Option.
1687  * bit[7-6] = 1: The VCC power status is treated as power-on.
1688  * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
1689  * PECI). It means VCC should be logic high before using these
1690  * functions, or firmware treats VCC logic high.
1691  */
1692 #define IT8XXX2_GCTRL_VCCDO_MASK	(BIT(6) | BIT(7))
1693 #define IT8XXX2_GCTRL_VCCDO_VCC_ON	BIT(6)
1694 /*
1695  * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
1696  * register and WRST#.
1697  */
1698 #define IT8XXX2_GCTRL_HGRST		BIT(3)
1699 /* bit[2] = 1: Enable global reset. */
1700 #define IT8XXX2_GCTRL_GRST		BIT(2)
1701 
1702 /**
1703  *
1704  * (22xxh) Battery-backed SRAM (BRAM) registers
1705  *
1706  */
1707 #ifndef __ASSEMBLER__
1708 /* Battery backed RAM indices. */
1709 #define BRAM_MAGIC_FIELD_OFFSET 0xbc
1710 enum bram_indices {
1711 
1712 	/* This field is used to indicate BRAM is valid or not. */
1713 	BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET,
1714 	BRAM_IDX_VALID_FLAGS1,
1715 	BRAM_IDX_VALID_FLAGS2,
1716 	BRAM_IDX_VALID_FLAGS3
1717 };
1718 #endif /* !__ASSEMBLER__ */
1719 
1720 #ifndef __ASSEMBLER__
1721 /*
1722  * EC2I bridge registers
1723  */
1724 struct ec2i_regs {
1725 	/* 0x00: Indirect Host I/O Address Register */
1726 	volatile uint8_t IHIOA;
1727 	/* 0x01: Indirect Host Data Register */
1728 	volatile uint8_t IHD;
1729 	/* 0x02: Lock Super I/O Host Access Register */
1730 	volatile uint8_t LSIOHA;
1731 	/* 0x03: Super I/O Access Lock Violation Register */
1732 	volatile uint8_t SIOLV;
1733 	/* 0x04: EC to I-Bus Modules Access Enable Register */
1734 	volatile uint8_t IBMAE;
1735 	/* 0x05: I-Bus Control Register */
1736 	volatile uint8_t IBCTL;
1737 };
1738 
1739 /* Index list of the host interface registers of PNPCFG */
1740 enum host_pnpcfg_index {
1741 	/* Logical Device Number */
1742 	HOST_INDEX_LDN = 0x07,
1743 	/* Chip ID Byte 1 */
1744 	HOST_INDEX_CHIPID1 = 0x20,
1745 	/* Chip ID Byte 2 */
1746 	HOST_INDEX_CHIPID2 = 0x21,
1747 	/* Chip Version */
1748 	HOST_INDEX_CHIPVER = 0x22,
1749 	/* Super I/O Control */
1750 	HOST_INDEX_SIOCTRL = 0x23,
1751 	/* Super I/O IRQ Configuration */
1752 	HOST_INDEX_SIOIRQ = 0x25,
1753 	/* Super I/O General Purpose */
1754 	HOST_INDEX_SIOGP = 0x26,
1755 	/* Super I/O Power Mode */
1756 	HOST_INDEX_SIOPWR = 0x2D,
1757 	/* Depth 2 I/O Address */
1758 	HOST_INDEX_D2ADR = 0x2E,
1759 	/* Depth 2 I/O Data */
1760 	HOST_INDEX_D2DAT = 0x2F,
1761 	/* Logical Device Activate Register */
1762 	HOST_INDEX_LDA = 0x30,
1763 	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
1764 	HOST_INDEX_IOBAD0_MSB = 0x60,
1765 	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
1766 	HOST_INDEX_IOBAD0_LSB = 0x61,
1767 	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
1768 	HOST_INDEX_IOBAD1_MSB = 0x62,
1769 	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
1770 	HOST_INDEX_IOBAD1_LSB = 0x63,
1771 	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
1772 	HOST_INDEX_IRQNUMX = 0x70,
1773 	/* Interrupt Request Type Select */
1774 	HOST_INDEX_IRQTP = 0x71,
1775 	/* DMA Channel Select 0 */
1776 	HOST_INDEX_DMAS0 = 0x74,
1777 	/* DMA Channel Select 1 */
1778 	HOST_INDEX_DMAS1 = 0x75,
1779 	/* Device Specific Logical Device Configuration 1 to 10 */
1780 	HOST_INDEX_DSLDC1 = 0xF0,
1781 	HOST_INDEX_DSLDC2 = 0xF1,
1782 	HOST_INDEX_DSLDC3 = 0xF2,
1783 	HOST_INDEX_DSLDC4 = 0xF3,
1784 	HOST_INDEX_DSLDC5 = 0xF4,
1785 	HOST_INDEX_DSLDC6 = 0xF5,
1786 	HOST_INDEX_DSLDC7 = 0xF6,
1787 	HOST_INDEX_DSLDC8 = 0xF7,
1788 	HOST_INDEX_DSLDC9 = 0xF8,
1789 	HOST_INDEX_DSLDC10 = 0xF9,
1790 };
1791 
1792 /* List of logical device number (LDN) assignments */
1793 enum logical_device_number {
1794 	/* Serial Port 1 */
1795 	LDN_UART1 = 0x01,
1796 	/* Serial Port 2 */
1797 	LDN_UART2 = 0x02,
1798 	/* System Wake-Up Control */
1799 	LDN_SWUC = 0x04,
1800 	/* KBC/Mouse Interface */
1801 	LDN_KBC_MOUSE = 0x05,
1802 	/* KBC/Keyboard Interface */
1803 	LDN_KBC_KEYBOARD = 0x06,
1804 	/* Consumer IR */
1805 	LDN_CIR = 0x0A,
1806 	/* Shared Memory/Flash Interface */
1807 	LDN_SMFI = 0x0F,
1808 	/* RTC-like Timer */
1809 	LDN_RTCT = 0x10,
1810 	/* Power Management I/F Channel 1 */
1811 	LDN_PMC1 = 0x11,
1812 	/* Power Management I/F Channel 2 */
1813 	LDN_PMC2 = 0x12,
1814 	/* Serial Peripheral Interface */
1815 	LDN_SSPI = 0x13,
1816 	/* Platform Environment Control Interface */
1817 	LDN_PECI = 0x14,
1818 	/* Power Management I/F Channel 3 */
1819 	LDN_PMC3 = 0x17,
1820 	/* Power Management I/F Channel 4 */
1821 	LDN_PMC4 = 0x18,
1822 	/* Power Management I/F Channel 5 */
1823 	LDN_PMC5 = 0x19,
1824 };
1825 
1826 /* Structure for initializing PNPCFG via ec2i. */
1827 struct ec2i_t {
1828 	/* index port */
1829 	enum host_pnpcfg_index index_port;
1830 	/* data port */
1831 	uint8_t data_port;
1832 };
1833 
1834 /* EC2I access index/data port */
1835 enum ec2i_access {
1836 	/* index port */
1837 	EC2I_ACCESS_INDEX = 0,
1838 	/* data port */
1839 	EC2I_ACCESS_DATA = 1,
1840 };
1841 
1842 /* EC to I-Bus Access Enabled */
1843 #define EC2I_IBCTL_CSAE  BIT(0)
1844 /* EC Read from I-Bus */
1845 #define EC2I_IBCTL_CRIB  BIT(1)
1846 /* EC Write to I-Bus */
1847 #define EC2I_IBCTL_CWIB  BIT(2)
1848 #define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
1849 
1850 /* PNPCFG Register EC Access Enable */
1851 #define EC2I_IBMAE_CFGAE BIT(0)
1852 
1853 /*
1854  * KBC registers
1855  */
1856 struct kbc_regs {
1857 	/* 0x00: KBC Host Interface Control Register */
1858 	volatile uint8_t KBHICR;
1859 	/* 0x01: Reserved1 */
1860 	volatile uint8_t reserved1;
1861 	/* 0x02: KBC Interrupt Control Register */
1862 	volatile uint8_t KBIRQR;
1863 	/* 0x03: Reserved2 */
1864 	volatile uint8_t reserved2;
1865 	/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
1866 	volatile uint8_t KBHISR;
1867 	/* 0x05: Reserved3 */
1868 	volatile uint8_t reserved3;
1869 	/* 0x06: KBC Host Interface Keyboard Data Output Register */
1870 	volatile uint8_t KBHIKDOR;
1871 	/* 0x07: Reserved4 */
1872 	volatile uint8_t reserved4;
1873 	/* 0x08: KBC Host Interface Mouse Data Output Register */
1874 	volatile uint8_t KBHIMDOR;
1875 	/* 0x09: Reserved5 */
1876 	volatile uint8_t reserved5;
1877 	/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
1878 	volatile uint8_t KBHIDIR;
1879 };
1880 
1881 /* Output Buffer Full */
1882 #define KBC_KBHISR_OBF      BIT(0)
1883 /* Input Buffer Full */
1884 #define KBC_KBHISR_IBF      BIT(1)
1885 /* A2 Address (A2) */
1886 #define KBC_KBHISR_A2_ADDR  BIT(3)
1887 #define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \
1888 						| KBC_KBHISR_A2_ADDR)
1889 
1890 /* Clear Output Buffer Full */
1891 #define KBC_KBHICR_COBF      BIT(6)
1892 /* IBF/OBF Clear Mode Enable */
1893 #define KBC_KBHICR_IBFOBFCME BIT(5)
1894 /* Input Buffer Full CPU Interrupt Enable */
1895 #define KBC_KBHICR_IBFCIE    BIT(3)
1896 /* Output Buffer Empty CPU Interrupt Enable */
1897 #define KBC_KBHICR_OBECIE    BIT(2)
1898 /* Output Buffer Full Mouse Interrupt Enable */
1899 #define KBC_KBHICR_OBFMIE    BIT(1)
1900 /* Output Buffer Full Keyboard Interrupt Enable */
1901 #define KBC_KBHICR_OBFKIE    BIT(0)
1902 
1903 /*
1904  * PMC registers
1905  */
1906 struct pmc_regs {
1907 	/* 0x00: Host Interface PM Channel 1 Status */
1908 	volatile uint8_t PM1STS;
1909 	/* 0x01: Host Interface PM Channel 1 Data Out Port */
1910 	volatile uint8_t PM1DO;
1911 	/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
1912 	volatile uint8_t PM1DOSCI;
1913 	/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
1914 	volatile uint8_t PM1DOSMI;
1915 	/* 0x04: Host Interface PM Channel 1 Data In Port */
1916 	volatile uint8_t PM1DI;
1917 	/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
1918 	volatile uint8_t PM1DISCI;
1919 	/* 0x06: Host Interface PM Channel 1 Control */
1920 	volatile uint8_t PM1CTL;
1921 	/* 0x07: Host Interface PM Channel 1 Interrupt Control */
1922 	volatile uint8_t PM1IC;
1923 	/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
1924 	volatile uint8_t PM1IE;
1925 	/* 0x09-0x0f: Reserved1 */
1926 	volatile uint8_t reserved1[7];
1927 	/* 0x10: Host Interface PM Channel 2 Status */
1928 	volatile uint8_t PM2STS;
1929 	/* 0x11: Host Interface PM Channel 2 Data Out Port */
1930 	volatile uint8_t PM2DO;
1931 	/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
1932 	volatile uint8_t PM2DOSCI;
1933 	/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
1934 	volatile uint8_t PM2DOSMI;
1935 	/* 0x14: Host Interface PM Channel 2 Data In Port */
1936 	volatile uint8_t PM2DI;
1937 	/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
1938 	volatile uint8_t PM2DISCI;
1939 	/* 0x16: Host Interface PM Channel 2 Control */
1940 	volatile uint8_t PM2CTL;
1941 	/* 0x17: Host Interface PM Channel 2 Interrupt Control */
1942 	volatile uint8_t PM2IC;
1943 	/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
1944 	volatile uint8_t PM2IE;
1945 	/* 0x19: Mailbox Control */
1946 	volatile uint8_t MBXCTRL;
1947 	/* 0x1a-0x1f: Reserved2 */
1948 	volatile uint8_t reserved2[6];
1949 	/* 0x20-0xff: Reserved3 */
1950 	volatile uint8_t reserved3[0xe0];
1951 };
1952 
1953 /* Input Buffer Full Interrupt Enable */
1954 #define PMC_PM1CTL_IBFIE    BIT(0)
1955 /* Output Buffer Full */
1956 #define PMC_PM1STS_OBF      BIT(0)
1957 /* Input Buffer Full */
1958 #define PMC_PM1STS_IBF      BIT(1)
1959 /* General Purpose Flag */
1960 #define PMC_PM1STS_GPF      BIT(2)
1961 /* A2 Address (A2) */
1962 #define PMC_PM1STS_A2_ADDR  BIT(3)
1963 
1964 /* PMC2 Input Buffer Full Interrupt Enable */
1965 #define PMC_PM2CTL_IBFIE    BIT(0)
1966 /* General Purpose Flag */
1967 #define PMC_PM2STS_GPF      BIT(2)
1968 
1969 /*
1970  * Dedicated Interrupt
1971  * 0b:
1972  * INT3: PMC Output Buffer Empty Int
1973  * INT25: PMC Input Buffer Full Int
1974  * 1b:
1975  * INT3: PMC1 Output Buffer Empty Int
1976  * INT25: PMC1 Input Buffer Full Int
1977  * INT26: PMC2 Output Buffer Empty Int
1978  * INT27: PMC2 Input Buffer Full Int
1979  */
1980 #define PMC_MBXCTRL_DINT    BIT(5)
1981 
1982 /*
1983  * eSPI slave registers
1984  */
1985 struct espi_slave_regs {
1986 	/* 0x00-0x03: Reserved1 */
1987 	volatile uint8_t reserved1[4];
1988 
1989 	/* 0x04: General Capabilities and Configuration 0 */
1990 	volatile uint8_t GCAPCFG0;
1991 	/* 0x05: General Capabilities and Configuration 1 */
1992 	volatile uint8_t GCAPCFG1;
1993 	/* 0x06: General Capabilities and Configuration 2 */
1994 	volatile uint8_t GCAPCFG2;
1995 	/* 0x07: General Capabilities and Configuration 3 */
1996 	volatile uint8_t GCAPCFG3;
1997 
1998 	/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
1999 	/* 0x08: Channel 0 Capabilities and Configuration 0 */
2000 	volatile uint8_t CH_PC_CAPCFG0;
2001 	/* 0x09: Channel 0 Capabilities and Configuration 1 */
2002 	volatile uint8_t CH_PC_CAPCFG1;
2003 	/* 0x0A: Channel 0 Capabilities and Configuration 2 */
2004 	volatile uint8_t CH_PC_CAPCFG2;
2005 	/* 0x0B: Channel 0 Capabilities and Configuration 3 */
2006 	volatile uint8_t CH_PC_CAPCFG3;
2007 
2008 	/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
2009 	/* 0x0C: Channel 1 Capabilities and Configuration 0 */
2010 	volatile uint8_t CH_VW_CAPCFG0;
2011 	/* 0x0D: Channel 1 Capabilities and Configuration 1 */
2012 	volatile uint8_t CH_VW_CAPCFG1;
2013 	/* 0x0E: Channel 1 Capabilities and Configuration 2 */
2014 	volatile uint8_t CH_VW_CAPCFG2;
2015 	/* 0x0F: Channel 1 Capabilities and Configuration 3 */
2016 	volatile uint8_t CH_VW_CAPCFG3;
2017 
2018 	/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
2019 	/* 0x10: Channel 2 Capabilities and Configuration 0 */
2020 	volatile uint8_t CH_OOB_CAPCFG0;
2021 	/* 0x11: Channel 2 Capabilities and Configuration 1 */
2022 	volatile uint8_t CH_OOB_CAPCFG1;
2023 	/* 0x12: Channel 2 Capabilities and Configuration 2 */
2024 	volatile uint8_t CH_OOB_CAPCFG2;
2025 	/* 0x13: Channel 2 Capabilities and Configuration 3 */
2026 	volatile uint8_t CH_OOB_CAPCFG3;
2027 
2028 	/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
2029 	/* 0x14: Channel 3 Capabilities and Configuration 0 */
2030 	volatile uint8_t CH_FLASH_CAPCFG0;
2031 	/* 0x15: Channel 3 Capabilities and Configuration 1 */
2032 	volatile uint8_t CH_FLASH_CAPCFG1;
2033 	/* 0x16: Channel 3 Capabilities and Configuration 2 */
2034 	volatile uint8_t CH_FLASH_CAPCFG2;
2035 	/* 0x17: Channel 3 Capabilities and Configuration 3 */
2036 	volatile uint8_t CH_FLASH_CAPCFG3;
2037 	/* Channel 3 Capabilities and Configurations 2 */
2038 	/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
2039 	volatile uint8_t CH_FLASH_CAPCFG2_0;
2040 	/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
2041 	volatile uint8_t CH_FLASH_CAPCFG2_1;
2042 	/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
2043 	volatile uint8_t CH_FLASH_CAPCFG2_2;
2044 	/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
2045 	volatile uint8_t CH_FLASH_CAPCFG2_3;
2046 
2047 	/* 0x1c-0x1f: Reserved2 */
2048 	volatile uint8_t reserved2[4];
2049 	/* 0x20-0x8f: Reserved3 */
2050 	volatile uint8_t reserved3[0x70];
2051 
2052 	/* 0x90: eSPI PC Control 0 */
2053 	volatile uint8_t ESPCTRL0;
2054 	/* 0x91: eSPI PC Control 1 */
2055 	volatile uint8_t ESPCTRL1;
2056 	/* 0x92: eSPI PC Control 2 */
2057 	volatile uint8_t ESPCTRL2;
2058 	/* 0x93: eSPI PC Control 3 */
2059 	volatile uint8_t ESPCTRL3;
2060 	/* 0x94: eSPI PC Control 4 */
2061 	volatile uint8_t ESPCTRL4;
2062 	/* 0x95: eSPI PC Control 5 */
2063 	volatile uint8_t ESPCTRL5;
2064 	/* 0x96: eSPI PC Control 6 */
2065 	volatile uint8_t ESPCTRL6;
2066 	/* 0x97: eSPI PC Control 7 */
2067 	volatile uint8_t ESPCTRL7;
2068 	/* 0x98-0x9f: Reserved4 */
2069 	volatile uint8_t reserved4[8];
2070 
2071 	/* 0xa0: eSPI General Control 0 */
2072 	volatile uint8_t ESGCTRL0;
2073 	/* 0xa1: eSPI General Control 1 */
2074 	volatile uint8_t ESGCTRL1;
2075 	/* 0xa2: eSPI General Control 2 */
2076 	volatile uint8_t ESGCTRL2;
2077 	/* 0xa3: eSPI General Control 3 */
2078 	volatile uint8_t ESGCTRL3;
2079 	/* 0xa4-0xaf: Reserved5 */
2080 	volatile uint8_t reserved5[12];
2081 
2082 	/* 0xb0: eSPI Upstream Control 0 */
2083 	volatile uint8_t ESUCTRL0;
2084 	/* 0xb1: eSPI Upstream Control 1 */
2085 	volatile uint8_t ESUCTRL1;
2086 	/* 0xb2: eSPI Upstream Control 2 */
2087 	volatile uint8_t ESUCTRL2;
2088 	/* 0xb3: eSPI Upstream Control 3 */
2089 	volatile uint8_t ESUCTRL3;
2090 	/* 0xb4-0xb5: Reserved6 */
2091 	volatile uint8_t reserved6[2];
2092 	/* 0xb6: eSPI Upstream Control 6 */
2093 	volatile uint8_t ESUCTRL6;
2094 	/* 0xb7: eSPI Upstream Control 7 */
2095 	volatile uint8_t ESUCTRL7;
2096 	/* 0xb8: eSPI Upstream Control 8 */
2097 	volatile uint8_t ESUCTRL8;
2098 	/* 0xb9-0xbf: Reserved7 */
2099 	volatile uint8_t reserved7[7];
2100 
2101 	/* 0xc0: eSPI OOB Control 0 */
2102 	volatile uint8_t ESOCTRL0;
2103 	/* 0xc1: eSPI OOB Control 1 */
2104 	volatile uint8_t ESOCTRL1;
2105 	/* 0xc2-0xc3: Reserved8 */
2106 	volatile uint8_t reserved8[2];
2107 	/* 0xc4: eSPI OOB Control 4 */
2108 	volatile uint8_t ESOCTRL4;
2109 	/* 0xc5-0xcf: Reserved9 */
2110 	volatile uint8_t reserved9[11];
2111 
2112 	/* 0xd0: eSPI SAFS Control 0 */
2113 	volatile uint8_t ESPISAFSC0;
2114 	/* 0xd1: eSPI SAFS Control 1 */
2115 	volatile uint8_t ESPISAFSC1;
2116 	/* 0xd2: eSPI SAFS Control 2 */
2117 	volatile uint8_t ESPISAFSC2;
2118 	/* 0xd3: eSPI SAFS Control 3 */
2119 	volatile uint8_t ESPISAFSC3;
2120 	/* 0xd4: eSPI SAFS Control 4 */
2121 	volatile uint8_t ESPISAFSC4;
2122 	/* 0xd5: eSPI SAFS Control 5 */
2123 	volatile uint8_t ESPISAFSC5;
2124 	/* 0xd6: eSPI SAFS Control 6 */
2125 	volatile uint8_t ESPISAFSC6;
2126 	/* 0xd7: eSPI SAFS Control 7 */
2127 	volatile uint8_t ESPISAFSC7;
2128 };
2129 
2130 /*
2131  * eSPI VW registers
2132  */
2133 struct espi_vw_regs {
2134 	/* 0x00-0x7f: VW index */
2135 	volatile uint8_t VW_INDEX[0x80];
2136 	/* 0x80-0x8f: Reserved1 */
2137 	volatile uint8_t reserved1[0x10];
2138 	/* 0x90: VW Contrl 0 */
2139 	volatile uint8_t VWCTRL0;
2140 	/* 0x91: VW Contrl 1 */
2141 	volatile uint8_t VWCTRL1;
2142 	/* 0x92: VW Contrl 2 */
2143 	volatile uint8_t VWCTRL2;
2144 	/* 0x93: VW Contrl 3 */
2145 	volatile uint8_t VWCTRL3;
2146 	/* 0x94: Reserved2 */
2147 	volatile uint8_t reserved2;
2148 	/* 0x95: VW Contrl 5 */
2149 	volatile uint8_t VWCTRL5;
2150 	/* 0x96: VW Contrl 6 */
2151 	volatile uint8_t VWCTRL6;
2152 	/* 0x97: VW Contrl 7 */
2153 	volatile uint8_t VWCTRL7;
2154 	/* 0x98-0x99: Reserved3 */
2155 	volatile uint8_t reserved3[2];
2156 };
2157 
2158 #define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
2159 /*
2160  * eSPI Queue 0 registers
2161  */
2162 struct espi_queue0_regs {
2163 	/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
2164 	volatile uint8_t PUT_PC_DATA[0x40];
2165 	/* 0x40-0x7f: Reserved1 */
2166 	volatile uint8_t reserved1[0x40];
2167 	/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
2168 	volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
2169 };
2170 
2171 /*
2172  * eSPI Queue 1 registers
2173  */
2174 struct espi_queue1_regs {
2175 	/* 0x00-0x4f: Upstream Data Byte 0-79 */
2176 	volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
2177 	/* 0x50-0x7f: Reserved1 */
2178 	volatile uint8_t reserved1[0x30];
2179 	/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
2180 	volatile uint8_t PUT_FLASH_NP_DATA[0x40];
2181 };
2182 
2183 #endif /* !__ASSEMBLER__ */
2184 
2185 
2186 /**
2187  *
2188  * (3Axxh) SPI Slave Controller (SPISC) registers
2189  *
2190  */
2191 #ifndef __ASSEMBLER__
2192 struct spisc_it8xxx2_regs {
2193 	/* 0x00: SPI Slave General Control */
2194 	volatile uint8_t SPISC_SPISGCR;
2195 	/* 0x01: Tx/Rx FIFO Access */
2196 	volatile uint8_t SPISC_TXRXFAR;
2197 	/* 0x02: Tx FIFO Control */
2198 	volatile uint8_t SPISC_TXFCR;
2199 	/* 0x03: SPI Slave General Control 2 */
2200 	volatile uint8_t SPISC_SPISGCR2;
2201 	/* 0x04: Interrupt Mask */
2202 	volatile uint8_t SPISC_IMR;
2203 	/* 0x05: Interrupt Status */
2204 	volatile uint8_t SPISC_ISR;
2205 	/* 0x06: Tx FIFO Status */
2206 	volatile uint8_t SPISC_TXFSR;
2207 	/* 0x07: Rx FIFO Status */
2208 	volatile uint8_t SPISC_RXFSR;
2209 	/* 0x08: CPU Write Tx FIFO Data Byte0 */
2210 	volatile uint8_t SPISC_CPUWTXFDB0R;
2211 	/* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */
2212 	volatile uint8_t SPISC_FCR;
2213 	/* 0x0A: CPU Write Tx FIFO Data Byte2 */
2214 	volatile uint8_t SPISC_CPUWTXFDB2R;
2215 	/* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */
2216 	volatile uint8_t SPISC_SPISRDR;
2217 	/* 0x0C: Rx FIFO Readout Data Byte0 */
2218 	volatile uint8_t SPISC_RXFRDRB0;
2219 	/* 0x0D: Rx FIFO Readout Data Byte1 */
2220 	volatile uint8_t SPISC_RXFRDRB1;
2221 	/* 0x0E: Rx FIFO Readout Data Byte2 */
2222 	volatile uint8_t SPISC_RXFRDRB2;
2223 	/* 0x0F: Rx FIFO Readout Data Byte3 */
2224 	volatile uint8_t SPISC_RXFRDRB3;
2225 	/* 0x10-0x17: Reserved1 */
2226 	volatile uint8_t reserved1[8];
2227 	/* 0x18: FIFO Target Count Byte0 */
2228 	volatile uint8_t SPISC_FTCB0R;
2229 	/* 0x19: FIFO Target Count Byte1 */
2230 	volatile uint8_t SPISC_FTCB1R;
2231 	/* 0x1A: Target Count Capture Byte0 */
2232 	volatile uint8_t SPISC_TCCB0;
2233 	/* 0x1B: Target Count Capture Byte1 */
2234 	volatile uint8_t SPISC_TCCB1;
2235 	/* 0x1C-0x1D: Reserved2 */
2236 	volatile uint8_t reserved2[2];
2237 	/* 0x1E: Hardware Parsing 2 */
2238 	volatile uint8_t SPISC_HPR2;
2239 	/* 0x1F-0x25: Reserved3 */
2240 	volatile uint8_t reserved3[7];
2241 	/* 0x26: Rx Valid Length Interrupt Status Mask */
2242 	volatile uint8_t SPISC_RXVLISMR;
2243 	/* 0x27: Rx Valid Length Interrupt Status */
2244 	volatile uint8_t SPISC_RXVLISR;
2245 };
2246 #endif /* !__ASSEMBLER__ */
2247 
2248 /* SPISC register fields */
2249 /* 0x00: SPI Slave General Control */
2250 #define IT8XXX2_SPISC_SPISCEN		BIT(0)
2251 /* 0x01: Tx/Rx FIFO Access */
2252 #define IT8XXX2_SPISC_CPURXF1A		BIT(3)
2253 #define IT8XXX2_SPISC_CPUTFA		BIT(1)
2254 /* 0x02: Tx FIFO Control */
2255 #define IT8XXX2_SPISC_TXFCMR		BIT(2)
2256 #define IT8XXX2_SPISC_TXFR		BIT(1)
2257 #define IT8XXX2_SPISC_TXFS		BIT(0)
2258 /* 0x03: SPI Slave General Control 2 */
2259 #define IT8XXX2_SPISC_RXF2OC		BIT(4)
2260 #define IT8XXX2_SPISC_RXF1OC		BIT(3)
2261 #define IT8XXX2_SPISC_RXFAR		BIT(0)
2262 /* 0x04: Interrupt Mask */
2263 #define IT8XXX2_SPISC_EDIM		BIT(2)
2264 /* 0x06: Tx FIFO Status */
2265 #define IT8XXX2_SPISC_ENDDETECTINT	BIT(2)
2266 /* 0x09: FIFO Control */
2267 #define IT8XXX2_SPISC_SPISRTXF		BIT(2)
2268 #define IT8XXX2_SPISC_RXFR		BIT(1)
2269 #define IT8XXX2_SPISC_RXFCMR		BIT(0)
2270 /* 0x26: Rx Valid Length Interrupt Status Mask */
2271 #define IT8XXX2_SPISC_RVLIM		BIT(0)
2272 /* 0x27: Rx Valid Length Interrupt Status */
2273 #define IT8XXX2_SPISC_RVLI		BIT(0)
2274 
2275 #endif /* CHIP_CHIPREGS_H */
2276