1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * Copyright (c) 2016 BayLibre, SAS 4 * Copyright (c) 2017-2022 Linaro Limited. 5 * Copyright (c) 2017 RnDity Sp. z o.o. 6 * Copyright (c) 2023 STMicroelectronics 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 11 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 12 13 #include <zephyr/drivers/clock_control.h> 14 15 #if defined(CONFIG_SOC_SERIES_STM32C0X) 16 #include <zephyr/dt-bindings/clock/stm32c0_clock.h> 17 #elif defined(CONFIG_SOC_SERIES_STM32F0X) 18 #include <zephyr/dt-bindings/clock/stm32f0_clock.h> 19 #elif defined(CONFIG_SOC_SERIES_STM32F1X) 20 #if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE) 21 #include <zephyr/dt-bindings/clock/stm32f10x_clock.h> 22 #else 23 #include <zephyr/dt-bindings/clock/stm32f1_clock.h> 24 #endif 25 #elif defined(CONFIG_SOC_SERIES_STM32F3X) 26 #include <zephyr/dt-bindings/clock/stm32f3_clock.h> 27 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ 28 defined(CONFIG_SOC_SERIES_STM32F4X) 29 #include <zephyr/dt-bindings/clock/stm32f4_clock.h> 30 #include <zephyr/dt-bindings/clock/stm32f410_clock.h> 31 #elif defined(CONFIG_SOC_SERIES_STM32F7X) 32 #include <zephyr/dt-bindings/clock/stm32f7_clock.h> 33 #elif defined(CONFIG_SOC_SERIES_STM32G0X) 34 #include <zephyr/dt-bindings/clock/stm32g0_clock.h> 35 #elif defined(CONFIG_SOC_SERIES_STM32G4X) 36 #include <zephyr/dt-bindings/clock/stm32g4_clock.h> 37 #elif defined(CONFIG_SOC_SERIES_STM32L0X) 38 #include <zephyr/dt-bindings/clock/stm32l0_clock.h> 39 #elif defined(CONFIG_SOC_SERIES_STM32L1X) 40 #include <zephyr/dt-bindings/clock/stm32l1_clock.h> 41 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \ 42 defined(CONFIG_SOC_SERIES_STM32L5X) 43 #include <zephyr/dt-bindings/clock/stm32l4_clock.h> 44 #elif defined(CONFIG_SOC_SERIES_STM32WBX) 45 #include <zephyr/dt-bindings/clock/stm32wb_clock.h> 46 #elif defined(CONFIG_SOC_SERIES_STM32WB0X) 47 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h> 48 #elif defined(CONFIG_SOC_SERIES_STM32WLX) 49 #include <zephyr/dt-bindings/clock/stm32wl_clock.h> 50 #elif defined(CONFIG_SOC_SERIES_STM32H5X) 51 #include <zephyr/dt-bindings/clock/stm32h5_clock.h> 52 #elif defined(CONFIG_SOC_SERIES_STM32H7X) 53 #include <zephyr/dt-bindings/clock/stm32h7_clock.h> 54 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX) 55 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h> 56 #elif defined(CONFIG_SOC_SERIES_STM32N6X) 57 #include <zephyr/dt-bindings/clock/stm32n6_clock.h> 58 #elif defined(CONFIG_SOC_SERIES_STM32U0X) 59 #include <zephyr/dt-bindings/clock/stm32u0_clock.h> 60 #elif defined(CONFIG_SOC_SERIES_STM32U5X) 61 #include <zephyr/dt-bindings/clock/stm32u5_clock.h> 62 #elif defined(CONFIG_SOC_SERIES_STM32WBAX) 63 #include <zephyr/dt-bindings/clock/stm32wba_clock.h> 64 #else 65 #include <zephyr/dt-bindings/clock/stm32_clock.h> 66 #endif 67 68 /** Common clock control device node for all STM32 chips */ 69 #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc) 70 71 /** RCC node related symbols */ 72 73 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler) 74 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler) 75 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler) 76 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler) 77 #define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler) 78 #define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler) 79 #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler) 80 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 81 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 82 #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1) 83 #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 84 #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler) 85 86 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler) 87 #define STM32_CORE_PRESCALER STM32_AHB_PRESCALER 88 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 89 #define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER 90 #endif 91 92 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 93 #define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER 94 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 95 #define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER 96 #else 97 #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER 98 #endif 99 100 #define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler) 101 #define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler) 102 #define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler) 103 104 /** STM2H7RS specific RCC dividers */ 105 #if defined(CONFIG_SOC_SERIES_STM32H7RSX) 106 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre) 107 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 108 #define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1) 109 #define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2) 110 #define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4) 111 #define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5) 112 #else 113 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre) 114 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 115 #define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1) 116 #define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2) 117 #define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre) 118 #define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre) 119 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */ 120 121 /** STM2WBA specifics RCC dividers */ 122 #define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div) 123 124 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc)) 125 126 /* To enable use of IS_ENABLED utility macro, these symbols 127 * should not be defined directly using DT_SAME_NODE. 128 */ 129 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) 130 #define STM32_SYSCLK_SRC_PLL 1 131 #endif 132 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 133 #define STM32_SYSCLK_SRC_HSI 1 134 #endif 135 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 136 #define STM32_SYSCLK_SRC_HSE 1 137 #endif 138 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 139 #define STM32_SYSCLK_SRC_MSI 1 140 #endif 141 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 142 #define STM32_SYSCLK_SRC_MSIS 1 143 #endif 144 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 145 #define STM32_SYSCLK_SRC_CSI 1 146 #endif 147 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2)) 148 #define STM32_SYSCLK_SRC_IC2 1 149 #endif 150 151 152 /** PLL node related symbols */ 153 154 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ 155 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \ 156 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \ 157 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ 158 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ 159 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ 160 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \ 161 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ 162 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ 163 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \ 164 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \ 165 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) 166 #define STM32_PLL_ENABLED 1 167 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) 168 #define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n) 169 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) 170 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1) 171 #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q) 172 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1) 173 #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r) 174 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1) 175 #define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s) 176 #define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1) 177 #define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn) 178 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1) 179 #endif 180 181 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay) 182 #define STM32_PLLI2S_ENABLED 1 183 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR 184 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 185 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 186 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 187 #endif 188 189 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay) 190 #define STM32_PLLI2S_ENABLED 1 191 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m) 192 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 193 #define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q) 194 #define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1) 195 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 196 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 197 #endif 198 199 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \ 200 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \ 201 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) 202 #define STM32_PLL2_ENABLED 1 203 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) 204 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n) 205 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p) 206 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1) 207 #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q) 208 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1) 209 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r) 210 #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1) 211 #define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s) 212 #define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1) 213 #define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t) 214 #define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1) 215 #define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn) 216 #define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1) 217 #endif 218 219 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \ 220 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \ 221 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) 222 #define STM32_PLL3_ENABLED 1 223 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) 224 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n) 225 #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p) 226 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1) 227 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q) 228 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1) 229 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r) 230 #define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1) 231 #define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s) 232 #define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1) 233 #define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn) 234 #define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1) 235 #endif 236 237 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) 238 #define STM32_PLL_ENABLED 1 239 #define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre) 240 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 241 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre) 242 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \ 243 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \ 244 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay) 245 #define STM32_PLL_ENABLED 1 246 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 247 #define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv) 248 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre) 249 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) 250 #define STM32_PLL_ENABLED 1 251 #define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div) 252 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 253 #endif 254 255 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay) 256 #define STM32_PLL2_ENABLED 1 257 #define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul) 258 #define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv) 259 #endif 260 261 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay) 262 #define STM32_PLL1_ENABLED 1 263 #define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m) 264 #define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n) 265 #define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1) 266 #define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2) 267 #endif 268 269 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay) 270 #define STM32_PLL2_ENABLED 1 271 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) 272 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n) 273 #define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1) 274 #define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2) 275 #endif 276 277 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay) 278 #define STM32_PLL3_ENABLED 1 279 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) 280 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n) 281 #define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1) 282 #define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2) 283 #endif 284 285 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay) 286 #define STM32_PLL4_ENABLED 1 287 #define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m) 288 #define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n) 289 #define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1) 290 #define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2) 291 #endif 292 293 /** PLL/PLL1 clock source */ 294 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \ 295 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) 296 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) 297 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 298 #define STM32_PLL_SRC_MSI 1 299 #endif 300 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 301 #define STM32_PLL_SRC_MSIS 1 302 #endif 303 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 304 #define STM32_PLL_SRC_HSI 1 305 #endif 306 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 307 #define STM32_PLL_SRC_CSI 1 308 #endif 309 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 310 #define STM32_PLL_SRC_HSE 1 311 #endif 312 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2)) 313 #define STM32_PLL_SRC_PLL2 1 314 #endif 315 316 #endif 317 318 /** PLL2 clock source */ 319 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \ 320 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks) 321 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2)) 322 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 323 #define STM32_PLL2_SRC_MSI 1 324 #endif 325 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 326 #define STM32_PLL2_SRC_MSIS 1 327 #endif 328 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 329 #define STM32_PLL2_SRC_HSI 1 330 #endif 331 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 332 #define STM32_PLL2_SRC_HSE 1 333 #endif 334 335 #endif 336 337 /** PLL3 clock source */ 338 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \ 339 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks) 340 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3)) 341 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 342 #define STM32_PLL3_SRC_MSI 1 343 #endif 344 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 345 #define STM32_PLL3_SRC_MSIS 1 346 #endif 347 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 348 #define STM32_PLL3_SRC_HSI 1 349 #endif 350 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 351 #define STM32_PLL3_SRC_HSE 1 352 #endif 353 354 #endif 355 356 /** PLL4 clock source */ 357 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \ 358 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks) 359 #define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4)) 360 #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 361 #define STM32_PLL4_SRC_MSI 1 362 #endif 363 #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 364 #define STM32_PLL4_SRC_HSI 1 365 #endif 366 #if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 367 #define STM32_PLL4_SRC_HSE 1 368 #endif 369 370 #endif 371 372 373 /** Fixed clocks related symbols */ 374 375 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay) 376 #define STM32_LSE_ENABLED 1 377 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 378 #define STM32_LSE_DRIVING 0 379 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 380 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay) 381 #define STM32_LSE_ENABLED 1 382 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 383 #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability) 384 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 385 #else 386 #define STM32_LSE_ENABLED 0 387 #define STM32_LSE_FREQ 0 388 #define STM32_LSE_DRIVING 0 389 #define STM32_LSE_BYPASS 0 390 #endif 391 392 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ 393 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) 394 #define STM32_MSI_ENABLED 1 395 #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) 396 #endif 397 398 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) 399 #define STM32_MSI_ENABLED 1 400 #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode) 401 #endif 402 403 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) 404 #define STM32_MSIS_ENABLED 1 405 #define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range) 406 #define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode) 407 #else 408 #define STM32_MSIS_ENABLED 0 409 #define STM32_MSIS_RANGE 0 410 #define STM32_MSIS_PLL_MODE 0 411 #endif 412 413 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) 414 #define STM32_MSIK_ENABLED 1 415 #define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range) 416 #define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode) 417 #else 418 #define STM32_MSIK_ENABLED 0 419 #define STM32_MSIK_RANGE 0 420 #define STM32_MSIK_PLL_MODE 0 421 #endif 422 423 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay) 424 #define STM32_CSI_ENABLED 1 425 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency) 426 #else 427 #define STM32_CSI_FREQ 0 428 #endif 429 430 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay) 431 #define STM32_LSI_ENABLED 1 432 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency) 433 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay) 434 #define STM32_LSI_ENABLED 1 435 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency) 436 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay) 437 #define STM32_LSI_ENABLED 1 438 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency) 439 #else 440 #define STM32_LSI_FREQ 0 441 #endif 442 443 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay) 444 #define STM32_HSI_DIV_ENABLED 0 445 #define STM32_HSI_ENABLED 1 446 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 447 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \ 448 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \ 449 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) 450 #define STM32_HSI_DIV_ENABLED 1 451 #define STM32_HSI_ENABLED 1 452 #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div) 453 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 454 #else 455 #define STM32_HSI_DIV_ENABLED 0 456 #define STM32_HSI_DIVISOR 1 457 #define STM32_HSI_FREQ 0 458 #endif 459 460 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay) 461 #define STM32_HSE_ENABLED 1 462 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 463 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay) 464 #define STM32_HSE_ENABLED 1 465 #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass) 466 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 467 #define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled) 468 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay) 469 #define STM32_HSE_ENABLED 1 470 #define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo) 471 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 472 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 473 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay) 474 #define STM32_HSE_ENABLED 1 475 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 476 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 477 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay) 478 #define STM32_HSE_ENABLED 1 479 #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass) 480 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 481 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 482 #else 483 #define STM32_HSE_FREQ 0 484 #endif 485 486 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay) 487 #define STM32_HSI48_ENABLED 1 488 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 489 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay) 490 #define STM32_HSI48_ENABLED 1 491 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 492 #define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof) 493 #endif 494 495 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay) 496 #define STM32_CKPER_ENABLED 1 497 #endif 498 499 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay) 500 #define STM32_CPUSW_ENABLED 1 501 #endif 502 503 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay) 504 #define STM32_IC1_ENABLED 1 505 #define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src) 506 #define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div) 507 #endif 508 509 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay) 510 #define STM32_IC2_ENABLED 1 511 #define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src) 512 #define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div) 513 #endif 514 515 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay) 516 #define STM32_IC3_ENABLED 1 517 #define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src) 518 #define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div) 519 #endif 520 521 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay) 522 #define STM32_IC4_ENABLED 1 523 #define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src) 524 #define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div) 525 #endif 526 527 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay) 528 #define STM32_IC5_ENABLED 1 529 #define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src) 530 #define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div) 531 #endif 532 533 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay) 534 #define STM32_IC6_ENABLED 1 535 #define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src) 536 #define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div) 537 #endif 538 539 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay) 540 #define STM32_IC7_ENABLED 1 541 #define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src) 542 #define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div) 543 #endif 544 545 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay) 546 #define STM32_IC8_ENABLED 1 547 #define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src) 548 #define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div) 549 #endif 550 551 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay) 552 #define STM32_IC9_ENABLED 1 553 #define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src) 554 #define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div) 555 #endif 556 557 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay) 558 #define STM32_IC10_ENABLED 1 559 #define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src) 560 #define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div) 561 #endif 562 563 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay) 564 #define STM32_IC11_ENABLED 1 565 #define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src) 566 #define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div) 567 #endif 568 569 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay) 570 #define STM32_IC12_ENABLED 1 571 #define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src) 572 #define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div) 573 #endif 574 575 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay) 576 #define STM32_IC13_ENABLED 1 577 #define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src) 578 #define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div) 579 #endif 580 581 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay) 582 #define STM32_IC14_ENABLED 1 583 #define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src) 584 #define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div) 585 #endif 586 587 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay) 588 #define STM32_IC15_ENABLED 1 589 #define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src) 590 #define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div) 591 #endif 592 593 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay) 594 #define STM32_IC16_ENABLED 1 595 #define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src) 596 #define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div) 597 #endif 598 599 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay) 600 #define STM32_IC17_ENABLED 1 601 #define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src) 602 #define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div) 603 #endif 604 605 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay) 606 #define STM32_IC18_ENABLED 1 607 #define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src) 608 #define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div) 609 #endif 610 611 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay) 612 #define STM32_IC19_ENABLED 1 613 #define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src) 614 #define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div) 615 #endif 616 617 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay) 618 #define STM32_IC20_ENABLED 1 619 #define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src) 620 #define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div) 621 #endif 622 623 /** Driver structure definition */ 624 625 struct stm32_pclken { 626 uint32_t bus : STM32_CLOCK_DIV_SHIFT; 627 uint32_t div : (32 - STM32_CLOCK_DIV_SHIFT); 628 uint32_t enr; 629 }; 630 631 /** Device tree clocks helpers */ 632 633 #define STM32_CLOCK_INFO(clk_index, node_id) \ 634 { \ 635 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \ 636 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \ 637 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \ 638 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \ 639 STM32_CLOCK_DIV_SHIFT, \ 640 } 641 #define STM32_DT_CLOCKS(node_id) \ 642 { \ 643 LISTIFY(DT_NUM_CLOCKS(node_id), \ 644 STM32_CLOCK_INFO, (,), node_id) \ 645 } 646 647 #define STM32_DT_INST_CLOCKS(inst) \ 648 STM32_DT_CLOCKS(DT_DRV_INST(inst)) 649 650 #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || 651 #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \ 652 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0) 653 654 #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || 655 #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \ 656 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0) 657 658 /** Clock source binding accessors */ 659 660 /** 661 * @brief Obtain register field from clock source selection configuration. 662 * 663 * @param clock clock bit field value. 664 */ 665 #define STM32_DT_CLKSEL_REG_GET(clock) \ 666 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK) 667 668 /** 669 * @brief Obtain position field from clock source selection configuration. 670 * 671 * @param clock Clock bit field value. 672 */ 673 #define STM32_DT_CLKSEL_SHIFT_GET(clock) \ 674 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK) 675 676 /** 677 * @brief Obtain mask field from clock source selection configuration. 678 * 679 * @param clock Clock bit field value. 680 */ 681 #define STM32_DT_CLKSEL_MASK_GET(clock) \ 682 (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK) 683 684 /** 685 * @brief Obtain value field from clock source selection configuration. 686 * 687 * @param clock Clock bit field value. 688 */ 689 #define STM32_DT_CLKSEL_VAL_GET(clock) \ 690 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK) 691 692 #if defined(STM32_HSE_CSS) 693 /** 694 * @brief Called if the HSE clock security system detects a clock fault. 695 * 696 * The function is called in interrupt context. 697 * 698 * The default (weakly-linked) implementation does nothing and should be 699 * overridden. 700 */ 701 void stm32_hse_css_callback(void); 702 #endif 703 704 #ifdef CONFIG_SOC_SERIES_STM32WB0X 705 /** 706 * @internal 707 * @brief Type definition for LSI frequency update callbacks 708 */ 709 typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency); 710 711 /** 712 * @internal 713 * @brief Registers a callback to invoke after each runtime measure and 714 * update of the LSI frequency is completed. 715 * 716 * @param cb Callback to invoke 717 * @return 0 Registration successful 718 * @return ENOMEM Too many callbacks registered 719 * 720 * @note Callbacks are NEVER invoked if runtime LSI measurement is disabled 721 */ 722 int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb); 723 #endif /* CONFIG_SOC_SERIES_STM32WB0X */ 724 725 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ 726
