1 /*
2 * Copyright (c) 2016 - 2020 Nordic Semiconductor ASA
3 * Copyright (c) 2016 Vinayak Kariappa Chettimada
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/toolchain.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <soc.h>
11
12 #include <nrfx_gpiote.h>
13
14 #include "util/mem.h"
15
16 #include "hal/cpu.h"
17 #include "hal/ccm.h"
18 #include "hal/radio.h"
19 #include "hal/radio_df.h"
20 #include "hal/ticker.h"
21
22 #include "ll_sw/pdu_df.h"
23 #include "lll/pdu_vendor.h"
24 #include "ll_sw/pdu.h"
25
26 #include "radio_internal.h"
27
28 /* Converts the GPIO controller in a FEM property's GPIO specification
29 * to its nRF register map pointer.
30 *
31 * Make sure to use NRF_DT_CHECK_GPIO_CTLR_IS_SOC to check the GPIO
32 * controller has the right compatible wherever you use this.
33 */
34 #define NRF_FEM_GPIO(prop) \
35 ((NRF_GPIO_Type *)DT_REG_ADDR(DT_GPIO_CTLR(FEM_NODE, prop)))
36
37 /* Converts GPIO specification to a PSEL value. */
38 #define NRF_FEM_PSEL(prop) NRF_DT_GPIOS_TO_PSEL(FEM_NODE, prop)
39
40 /* Check if GPIO flags are active low. */
41 #define ACTIVE_LOW(flags) ((flags) & GPIO_ACTIVE_LOW)
42
43 /* Check if GPIO flags contain unsupported values. */
44 #define BAD_FLAGS(flags) ((flags) & ~GPIO_ACTIVE_LOW)
45
46 /* GPIOTE OUTINIT setting for a pin's inactive level, from its
47 * devicetree flags.
48 */
49 #define OUTINIT_INACTIVE(flags) \
50 (ACTIVE_LOW(flags) ? \
51 GPIOTE_CONFIG_OUTINIT_High : \
52 GPIOTE_CONFIG_OUTINIT_Low)
53
54 #if defined(FEM_NODE)
55 BUILD_ASSERT(!HAL_RADIO_GPIO_PA_OFFSET_MISSING,
56 "fem node " DT_NODE_PATH(FEM_NODE) " has property "
57 HAL_RADIO_GPIO_PA_PROP_NAME " set, so you must also set "
58 HAL_RADIO_GPIO_PA_OFFSET_PROP_NAME);
59
60 BUILD_ASSERT(!HAL_RADIO_GPIO_LNA_OFFSET_MISSING,
61 "fem node " DT_NODE_PATH(FEM_NODE) " has property "
62 HAL_RADIO_GPIO_LNA_PROP_NAME " set, so you must also set "
63 HAL_RADIO_GPIO_LNA_OFFSET_PROP_NAME);
64 #endif /* FEM_NODE */
65
66 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
67 static const nrfx_gpiote_t gpiote_palna = NRFX_GPIOTE_INSTANCE(
68 NRF_DT_GPIOTE_INST(FEM_NODE, HAL_RADIO_GPIO_PA_PROP));
69 static uint8_t gpiote_ch_palna;
70
71 BUILD_ASSERT(NRF_DT_GPIOTE_INST(FEM_NODE, HAL_RADIO_GPIO_PA_PROP) ==
72 NRF_DT_GPIOTE_INST(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP),
73 HAL_RADIO_GPIO_PA_PROP_NAME " and " HAL_RADIO_GPIO_LNA_PROP_NAME
74 " GPIOs must use the same GPIOTE instance.");
75 #endif
76
77 #if defined(HAL_RADIO_FEM_IS_NRF21540)
78 static const nrfx_gpiote_t gpiote_pdn = NRFX_GPIOTE_INSTANCE(
79 NRF_DT_GPIOTE_INST(FEM_NODE, pdn_gpios));
80 static uint8_t gpiote_ch_pdn;
81 static const nrfx_gpiote_t gpiote_csn = NRFX_GPIOTE_INSTANCE(
82 NRF_DT_GPIOTE_INST(DT_BUS(FEM_SPI_DEV_NODE), cs_gpios));
83 static uint8_t gpiote_ch_csn;
84 #endif
85
86 /* These headers require the above gpiote-related variables to be declared. */
87 #if defined(PPI_PRESENT)
88 #include "radio_nrf5_ppi_gpiote.h"
89 #elif defined(DPPI_PRESENT)
90 #include "radio_nrf5_dppi_gpiote.h"
91 #endif
92
93 /*
94 * "Manual" conversions of devicetree values to register bits. We
95 * can't use the Zephyr GPIO API here, so we need this extra
96 * boilerplate.
97 */
98
99 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
100 #define NRF_GPIO_PA NRF_FEM_GPIO(HAL_RADIO_GPIO_PA_PROP)
101 #define NRF_GPIO_PA_PIN DT_GPIO_PIN(FEM_NODE, HAL_RADIO_GPIO_PA_PROP)
102 #define NRF_GPIO_PA_FLAGS DT_GPIO_FLAGS(FEM_NODE, HAL_RADIO_GPIO_PA_PROP)
103 #define NRF_GPIO_PA_PSEL NRF_FEM_PSEL(HAL_RADIO_GPIO_PA_PROP)
104 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, HAL_RADIO_GPIO_PA_PROP,
105 HAL_RADIO_GPIO_PA_PROP_NAME);
106 BUILD_ASSERT(!BAD_FLAGS(NRF_GPIO_PA_FLAGS),
107 "fem node " DT_NODE_PATH(FEM_NODE) " has invalid GPIO flags in "
108 HAL_RADIO_GPIO_PA_PROP_NAME
109 "; only GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH are supported");
110 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
111
112 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
113 #define NRF_GPIO_LNA NRF_FEM_GPIO(HAL_RADIO_GPIO_LNA_PROP)
114 #define NRF_GPIO_LNA_PIN DT_GPIO_PIN(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP)
115 #define NRF_GPIO_LNA_FLAGS DT_GPIO_FLAGS(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP)
116 #define NRF_GPIO_LNA_PSEL NRF_FEM_PSEL(HAL_RADIO_GPIO_LNA_PROP)
117 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP,
118 HAL_RADIO_GPIO_LNA_PROP_NAME);
119 BUILD_ASSERT(!BAD_FLAGS(NRF_GPIO_LNA_FLAGS),
120 "fem node " DT_NODE_PATH(FEM_NODE) " has invalid GPIO flags in "
121 HAL_RADIO_GPIO_LNA_PROP_NAME
122 "; only GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH are supported");
123 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
124
125 #if defined(HAL_RADIO_FEM_IS_NRF21540)
126
127 #if DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios)
128 #define NRF_GPIO_PDN NRF_FEM_GPIO(pdn_gpios)
129 #define NRF_GPIO_PDN_PIN DT_GPIO_PIN(FEM_NODE, pdn_gpios)
130 #define NRF_GPIO_PDN_FLAGS DT_GPIO_FLAGS(FEM_NODE, pdn_gpios)
131 #define NRF_GPIO_PDN_PSEL NRF_FEM_PSEL(pdn_gpios)
132 #define NRF_GPIO_PDN_OFFSET DT_PROP(FEM_NODE, pdn_settle_time_us)
133 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, pdn_gpios, "pdn-gpios");
134 #endif /* DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios) */
135
136 /* CSN is special because it comes from the spi-if property. */
137 #if defined(HAL_RADIO_FEM_NRF21540_HAS_CSN)
138 #define NRF_GPIO_CSN_CTLR DT_SPI_DEV_CS_GPIOS_CTLR(FEM_SPI_DEV_NODE)
139 #define NRF_GPIO_CSN ((NRF_GPIO_Type *)DT_REG_ADDR(NRF_GPIO_CSN_CTLR))
140 #define NRF_GPIO_CSN_PIN DT_SPI_DEV_CS_GPIOS_PIN(FEM_SPI_DEV_NODE)
141 #define NRF_GPIO_CSN_FLAGS DT_SPI_DEV_CS_GPIOS_FLAGS(FEM_SPI_DEV_NODE)
142 #define NRF_GPIO_CSN_PSEL (NRF_GPIO_CSN_PIN + \
143 (DT_PROP(NRF_GPIO_CSN_CTLR, port) << 5))
144 BUILD_ASSERT(DT_NODE_HAS_COMPAT(NRF_GPIO_CSN_CTLR, nordic_nrf_gpio),
145 "fem node " DT_NODE_PATH(FEM_NODE) " has a spi-if property, "
146 " but the chip select pin is not on the SoC. Check cs-gpios in "
147 DT_NODE_PATH(DT_BUS(FEM_SPI_DEV_NODE)));
148 #endif /* HAL_RADIO_FEM_NRF21540_HAS_CSN */
149
150 #endif /* HAL_RADIO_FEM_IS_NRF21540 */
151
152 /* CTEINLINE S0_MASK for periodic advertising PUDs. It allows to accept all types of extended
153 * advertising PDUs to have CTE included.
154 */
155 #define DF_S0_ALLOW_ALL_PER_ADV_PDU 0x0
156 /* CTEINLINE S0_MASK for data channel PDUs. It points to CP bit in S0 byte to check if is it set
157 * to 0x1. In that is true then S1 byte (CTEInfo) is considered as present in a PDU.
158 */
159 #define DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU 0x20
160
161 static radio_isr_cb_t isr_cb;
162 static void *isr_cb_param;
163
isr_radio(void)164 void isr_radio(void)
165 {
166 if (radio_has_disabled()) {
167 isr_cb(isr_cb_param);
168 }
169 }
170
radio_isr_set(radio_isr_cb_t cb,void * param)171 void radio_isr_set(radio_isr_cb_t cb, void *param)
172 {
173 irq_disable(HAL_RADIO_IRQn);
174
175 isr_cb_param = param;
176 isr_cb = cb;
177
178 nrf_radio_int_enable(NRF_RADIO, HAL_RADIO_INTENSET_DISABLED_Msk);
179
180 NVIC_ClearPendingIRQ(HAL_RADIO_IRQn);
181 irq_enable(HAL_RADIO_IRQn);
182 }
183
radio_setup(void)184 void radio_setup(void)
185 {
186 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
187 NRF_GPIO_PA->DIRSET = BIT(NRF_GPIO_PA_PIN);
188 if (ACTIVE_LOW(NRF_GPIO_PA_FLAGS)) {
189 NRF_GPIO_PA->OUTSET = BIT(NRF_GPIO_PA_PIN);
190 } else {
191 NRF_GPIO_PA->OUTCLR = BIT(NRF_GPIO_PA_PIN);
192 }
193 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
194
195 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
196 NRF_GPIO_LNA->DIRSET = BIT(NRF_GPIO_LNA_PIN);
197
198 radio_gpio_lna_off();
199 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
200
201 #if defined(NRF_GPIO_PDN_PIN)
202 NRF_GPIO_PDN->DIRSET = BIT(NRF_GPIO_PDN_PIN);
203 if (ACTIVE_LOW(NRF_GPIO_PDN_FLAGS)) {
204 NRF_GPIO_PDN->OUTSET = BIT(NRF_GPIO_PDN_PIN);
205 } else {
206 NRF_GPIO_PDN->OUTCLR = BIT(NRF_GPIO_PDN_PIN);
207 }
208 #endif /* NRF_GPIO_PDN_PIN */
209
210 #if defined(NRF_GPIO_CSN_PIN)
211 NRF_GPIO_CSN->DIRSET = BIT(NRF_GPIO_CSN_PIN);
212 if (ACTIVE_LOW(NRF_GPIO_CSN_FLAGS)) {
213 NRF_GPIO_CSN->OUTSET = BIT(NRF_GPIO_CSN_PIN);
214 } else {
215 NRF_GPIO_CSN->OUTCLR = BIT(NRF_GPIO_CSN_PIN);
216 }
217 #endif /* NRF_GPIO_CSN_PIN */
218
219 hal_radio_ram_prio_setup();
220 }
221
radio_reset(void)222 void radio_reset(void)
223 {
224 irq_disable(HAL_RADIO_IRQn);
225
226 /* nRF SoC generic radio reset/initializations
227 * Note: Only registers whose bits are partially modified across
228 * functions are assigned back the power-on reset values.
229 * Ignore other registers for reset which will have all bits
230 * explicitly assigned by functions in this file.
231 */
232 NRF_RADIO->PCNF1 = HAL_RADIO_RESET_VALUE_PCNF1;
233
234 #if defined(CONFIG_BT_CTLR_DF) && !defined(CONFIG_ZTEST)
235 radio_df_reset();
236 #endif /* CONFIG_BT_CTLR_DF && !CONFIG_ZTEST */
237
238 /* nRF SoC specific reset/initializations, if any */
239 hal_radio_reset();
240
241 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
242 hal_radio_sw_switch_ppi_group_setup();
243 #endif
244
245 #if defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
246 NRF_RADIO->TIMING = (0U << RADIO_TIMING_RU_Pos) &
247 RADIO_TIMING_RU_Msk;
248
249 NRF_POWER->TASKS_CONSTLAT = 1U;
250 #endif /* CONFIG_SOC_COMPATIBLE_NRF54LX */
251
252 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
253 hal_palna_ppi_setup();
254 #endif
255 #if defined(HAL_RADIO_FEM_IS_NRF21540)
256 hal_fem_ppi_setup();
257 #endif
258 }
259
radio_stop(void)260 void radio_stop(void)
261 {
262 /* nRF SoC specific radio stop/cleanup, if any */
263 hal_radio_stop();
264
265 /* nRF SoC generic radio stop/cleanup
266 * TODO: Initialize NRF_RADIO registers used by Controller to power-on
267 * reset values.
268 * This is required in case NRF_RADIO is share/used between
269 * Bluetooth radio events by application defined radio protocols.
270 * The application too shall restore the registers it uses to the
271 * power-on reset values once it has stopped using the radio.
272 *
273 * Registers used for Bluetooth Low Energy Controller:
274 * - MODE
275 * - MODECNF0
276 * - TXPOWER
277 * - FREQUENCY
278 * - DATAWHITEIV
279 * - PCNF0
280 * - PCNF1
281 * - TXADDRESS
282 * - RXADDRESSES
283 * - PREFIX0
284 * - BASE0
285 * - PACKETPTR
286 * - CRCCNF
287 * - CRCPOLY
288 * - CRCINIT
289 * - DAB
290 * - DAP
291 * - DACNF
292 * - BCC
293 * - TIFS
294 * - SHORTS
295 *
296 * Additional registers used for Direction Finding feature:
297 * - SWITCHPATTERN
298 * - DFEMODE
299 * - CTEINLINECONF
300 * - DFECTRL1
301 * - DEFCTRL2
302 * - CLEARPATTERN
303 * - PSEL.DFEGPIO[n]
304 * - DFEPACKET.PTR
305 */
306 }
307
radio_phy_set(uint8_t phy,uint8_t flags)308 void radio_phy_set(uint8_t phy, uint8_t flags)
309 {
310 uint32_t mode;
311
312 mode = hal_radio_phy_mode_get(phy, flags);
313
314 NRF_RADIO->MODE = (mode << RADIO_MODE_MODE_Pos) & RADIO_MODE_MODE_Msk;
315
316 #if !defined(CONFIG_SOC_SERIES_NRF51X) && !defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
317 #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST)
318 NRF_RADIO->MODECNF0 = ((RADIO_MODECNF0_DTX_Center <<
319 RADIO_MODECNF0_DTX_Pos) &
320 RADIO_MODECNF0_DTX_Msk) |
321 ((RADIO_MODECNF0_RU_Fast <<
322 RADIO_MODECNF0_RU_Pos) &
323 RADIO_MODECNF0_RU_Msk);
324 #else /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
325 NRF_RADIO->MODECNF0 = (RADIO_MODECNF0_DTX_Center <<
326 RADIO_MODECNF0_DTX_Pos) &
327 RADIO_MODECNF0_DTX_Msk;
328 #endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
329 #endif /* !CONFIG_SOC_SERIES_NRF51X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
330 }
331
radio_tx_power_set(int8_t power)332 void radio_tx_power_set(int8_t power)
333 {
334 #if defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
335 uint32_t value;
336
337 value = hal_radio_tx_power_value(power);
338 NRF_RADIO->TXPOWER = value;
339
340 #elif defined(CONFIG_SOC_COMPATIBLE_NRF53X)
341 uint32_t value;
342
343 /* NOTE: TXPOWER register only accepts upto 0dBm, hence use the HAL
344 * floor value for the TXPOWER register. Permit +3dBm by using high
345 * voltage being set for radio.
346 */
347 value = hal_radio_tx_power_floor(power);
348 NRF_RADIO->TXPOWER = value;
349 hal_radio_tx_power_high_voltage_set(power);
350
351 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
352
353 /* NOTE: valid value range is passed by Kconfig define. */
354 NRF_RADIO->TXPOWER = (uint32_t)power;
355
356 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
357 }
358
radio_tx_power_max_set(void)359 void radio_tx_power_max_set(void)
360 {
361 int8_t power;
362
363 power = radio_tx_power_max_get();
364 radio_tx_power_set(power);
365 }
366
radio_tx_power_min_get(void)367 int8_t radio_tx_power_min_get(void)
368 {
369 return (int8_t)hal_radio_tx_power_min_get();
370 }
371
radio_tx_power_max_get(void)372 int8_t radio_tx_power_max_get(void)
373 {
374 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
375 return RADIO_TXPOWER_TXPOWER_Pos3dBm;
376
377 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
378 return (int8_t)hal_radio_tx_power_max_get();
379
380 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
381 }
382
radio_tx_power_floor(int8_t power)383 int8_t radio_tx_power_floor(int8_t power)
384 {
385 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
386 /* NOTE: TXPOWER register only accepts upto 0dBm, +3dBm permitted by
387 * use of high voltage being set for radio when TXPOWER register is set.
388 */
389 if (power >= (int8_t)RADIO_TXPOWER_TXPOWER_Pos3dBm) {
390 return RADIO_TXPOWER_TXPOWER_Pos3dBm;
391 }
392 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
393
394 return (int8_t)hal_radio_tx_power_floor(power);
395 }
396
radio_freq_chan_set(uint32_t chan)397 void radio_freq_chan_set(uint32_t chan)
398 {
399 NRF_RADIO->FREQUENCY = chan;
400 }
401
radio_whiten_iv_set(uint32_t iv)402 void radio_whiten_iv_set(uint32_t iv)
403 {
404 nrf_radio_datawhiteiv_set(NRF_RADIO, iv);
405
406 NRF_RADIO->PCNF1 &= ~RADIO_PCNF1_WHITEEN_Msk;
407 NRF_RADIO->PCNF1 |= ((1UL) << RADIO_PCNF1_WHITEEN_Pos) &
408 RADIO_PCNF1_WHITEEN_Msk;
409 }
410
radio_aa_set(const uint8_t * aa)411 void radio_aa_set(const uint8_t *aa)
412 {
413 NRF_RADIO->TXADDRESS =
414 (((0UL) << RADIO_TXADDRESS_TXADDRESS_Pos) &
415 RADIO_TXADDRESS_TXADDRESS_Msk);
416 NRF_RADIO->RXADDRESSES =
417 ((RADIO_RXADDRESSES_ADDR0_Enabled) << RADIO_RXADDRESSES_ADDR0_Pos);
418 NRF_RADIO->PREFIX0 = aa[3];
419 NRF_RADIO->BASE0 = (((uint32_t) aa[2]) << 24) | (aa[1] << 16) | (aa[0] << 8);
420 }
421
radio_pkt_configure(uint8_t bits_len,uint8_t max_len,uint8_t flags)422 void radio_pkt_configure(uint8_t bits_len, uint8_t max_len, uint8_t flags)
423 {
424 const uint8_t pdu_type = RADIO_PKT_CONF_PDU_TYPE_GET(flags); /* Adv or Data channel */
425 uint8_t bits_s1;
426 uint32_t extra;
427 uint8_t phy;
428
429 #if defined(CONFIG_SOC_SERIES_NRF51X)
430 ARG_UNUSED(phy);
431
432 extra = 0U;
433
434 /* nRF51 supports only 27 byte PDU when using h/w CCM for encryption. */
435 if (!IS_ENABLED(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR) &&
436 pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) {
437 bits_len = RADIO_PKT_CONF_LENGTH_5BIT;
438 }
439 bits_s1 = RADIO_PKT_CONF_LENGTH_8BIT - bits_len;
440
441 #elif defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
442 defined(CONFIG_SOC_COMPATIBLE_NRF53X) || \
443 defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
444 extra = 0U;
445
446 phy = RADIO_PKT_CONF_PHY_GET(flags);
447 switch (phy) {
448 case PHY_1M:
449 default:
450 extra |= (RADIO_PCNF0_PLEN_8bit << RADIO_PCNF0_PLEN_Pos) &
451 RADIO_PCNF0_PLEN_Msk;
452 break;
453
454 case PHY_2M:
455 extra |= (RADIO_PCNF0_PLEN_16bit << RADIO_PCNF0_PLEN_Pos) &
456 RADIO_PCNF0_PLEN_Msk;
457 break;
458
459 #if defined(CONFIG_BT_CTLR_PHY_CODED)
460 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
461 case PHY_CODED:
462 extra |= (RADIO_PCNF0_PLEN_LongRange << RADIO_PCNF0_PLEN_Pos) &
463 RADIO_PCNF0_PLEN_Msk;
464 extra |= (2UL << RADIO_PCNF0_CILEN_Pos) & RADIO_PCNF0_CILEN_Msk;
465 extra |= (3UL << RADIO_PCNF0_TERMLEN_Pos) &
466 RADIO_PCNF0_TERMLEN_Msk;
467 break;
468 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
469 #endif /* CONFIG_BT_CTLR_PHY_CODED */
470 }
471
472 /* To use same Data Channel PDU structure with nRF5 specific overhead
473 * byte, include the S1 field in radio packet configuration.
474 */
475 if ((pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) ||
476 (pdu_type == RADIO_PKT_CONF_PDU_TYPE_BIS) ||
477 (pdu_type == RADIO_PKT_CONF_PDU_TYPE_CIS)) {
478 extra |= (RADIO_PCNF0_S1INCL_Include <<
479 RADIO_PCNF0_S1INCL_Pos) & RADIO_PCNF0_S1INCL_Msk;
480 #if defined(CONFIG_BT_CTLR_DF)
481 if (RADIO_PKT_CONF_CTE_GET(flags) == RADIO_PKT_CONF_CTE_ENABLED) {
482 bits_s1 = RADIO_PKT_CONF_S1_8BIT;
483 } else
484 #endif /* CONFIG_BT_CTLR_DF */
485 {
486 bits_s1 = 0U;
487 }
488 } else {
489 bits_s1 = 0U;
490 }
491 #endif /* CONFIG_SOC_COMPATIBLE_NRF52X */
492
493 NRF_RADIO->PCNF0 =
494 (((1UL) << RADIO_PCNF0_S0LEN_Pos) & RADIO_PCNF0_S0LEN_Msk) |
495 ((((uint32_t)bits_len) << RADIO_PCNF0_LFLEN_Pos) & RADIO_PCNF0_LFLEN_Msk) |
496 ((((uint32_t)bits_s1) << RADIO_PCNF0_S1LEN_Pos) & RADIO_PCNF0_S1LEN_Msk) | extra;
497
498 NRF_RADIO->PCNF1 &= ~(RADIO_PCNF1_MAXLEN_Msk | RADIO_PCNF1_STATLEN_Msk |
499 RADIO_PCNF1_BALEN_Msk | RADIO_PCNF1_ENDIAN_Msk);
500 NRF_RADIO->PCNF1 |=
501 ((((uint32_t)max_len) << RADIO_PCNF1_MAXLEN_Pos) & RADIO_PCNF1_MAXLEN_Msk) |
502 (((0UL) << RADIO_PCNF1_STATLEN_Pos) & RADIO_PCNF1_STATLEN_Msk) |
503 (((3UL) << RADIO_PCNF1_BALEN_Pos) & RADIO_PCNF1_BALEN_Msk) |
504 (((RADIO_PCNF1_ENDIAN_Little) << RADIO_PCNF1_ENDIAN_Pos) & RADIO_PCNF1_ENDIAN_Msk);
505 }
506
radio_pkt_rx_set(void * rx_packet)507 void radio_pkt_rx_set(void *rx_packet)
508 {
509 NRF_RADIO->PACKETPTR = (uint32_t)rx_packet;
510 }
511
radio_pkt_tx_set(void * tx_packet)512 void radio_pkt_tx_set(void *tx_packet)
513 {
514 NRF_RADIO->PACKETPTR = (uint32_t)tx_packet;
515 }
516
radio_tx_ready_delay_get(uint8_t phy,uint8_t flags)517 uint32_t radio_tx_ready_delay_get(uint8_t phy, uint8_t flags)
518 {
519 return hal_radio_tx_ready_delay_us_get(phy, flags);
520 }
521
radio_tx_chain_delay_get(uint8_t phy,uint8_t flags)522 uint32_t radio_tx_chain_delay_get(uint8_t phy, uint8_t flags)
523 {
524 return hal_radio_tx_chain_delay_us_get(phy, flags);
525 }
526
radio_rx_ready_delay_get(uint8_t phy,uint8_t flags)527 uint32_t radio_rx_ready_delay_get(uint8_t phy, uint8_t flags)
528 {
529 return hal_radio_rx_ready_delay_us_get(phy, flags);
530 }
531
radio_rx_chain_delay_get(uint8_t phy,uint8_t flags)532 uint32_t radio_rx_chain_delay_get(uint8_t phy, uint8_t flags)
533 {
534 return hal_radio_rx_chain_delay_us_get(phy, flags);
535 }
536
radio_rx_enable(void)537 void radio_rx_enable(void)
538 {
539 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
540 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
541 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
542 * because of calls to radio_disable() and
543 * radio_switch_complete_and_disable() inside a radio event call
544 * hal_radio_sw_switch_disable(), which in the case of nRF53
545 * cancels the task subscription.
546 */
547 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
548 * event. Consider a new interface to only set the task, or
549 * change the design to not clear task subscription inside a
550 * radio event but when the radio event is done.
551 */
552 hal_sw_switch_timer_clear_ppi_config();
553 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X || CONFIG_SOC_COMPATIBLE_NRF54LX */
554 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
555
556 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_RXEN);
557 }
558
radio_tx_enable(void)559 void radio_tx_enable(void)
560 {
561 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
562 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
563 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
564 * because of calls to radio_disable() and
565 * radio_switch_complete_and_disable() inside a radio event call
566 * hal_radio_sw_switch_disable(), which in the case of nRF53
567 * cancels the task subscription.
568 */
569 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
570 * event. Consider a new interface to only set the task, or
571 * change the design to not clear task subscription inside a
572 * radio event but when the radio event is done.
573 */
574 hal_sw_switch_timer_clear_ppi_config();
575 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X || CONFIG_SOC_COMPATIBLE_NRF54LX */
576 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
577
578 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_TXEN);
579 }
580
radio_disable(void)581 void radio_disable(void)
582 {
583 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
584 hal_radio_sw_switch_cleanup();
585 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
586
587 NRF_RADIO->SHORTS = 0;
588 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_DISABLE);
589 }
590
radio_status_reset(void)591 void radio_status_reset(void)
592 {
593 /* NOTE: Only EVENTS_* registers read (checked) by software needs reset
594 * between Radio IRQs. In PPI use, irrespective of stored EVENT_*
595 * register value, PPI task will be triggered. Hence, other
596 * EVENT_* registers are not reset to save code and CPU time.
597 */
598 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_READY);
599 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_END);
600 #if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST)
601 /* Clear it only for SoCs supporting DF extension */
602 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_PHYEND);
603 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_CTEPRESENT);
604 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH);
605 #endif /* CONFIG_BT_CTLR_DF_SUPPORT && !CONFIG_ZTEST */
606 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_DISABLED);
607 #if defined(CONFIG_BT_CTLR_PHY_CODED)
608 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
609 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_RATEBOOST);
610 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
611 #endif /* CONFIG_BT_CTLR_PHY_CODED */
612 }
613
radio_is_ready(void)614 uint32_t radio_is_ready(void)
615 {
616 return (NRF_RADIO->EVENTS_READY != 0);
617 }
618
619 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
620 static uint32_t last_pdu_end_us;
621
radio_is_done(void)622 uint32_t radio_is_done(void)
623 {
624 if (NRF_RADIO->NRF_RADIO_TRX_END_EVENT != 0) {
625 /* On packet END event increment last packet end time value.
626 * Note: this depends on the function being called exactly once
627 * in the ISR function.
628 */
629 last_pdu_end_us += EVENT_TIMER->CC[2];
630 return 1;
631 } else {
632 return 0;
633 }
634 }
635
636 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
radio_is_done(void)637 uint32_t radio_is_done(void)
638 {
639 return (NRF_RADIO->NRF_RADIO_TRX_END_EVENT != 0);
640 }
641 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
642
radio_has_disabled(void)643 uint32_t radio_has_disabled(void)
644 {
645 return (NRF_RADIO->EVENTS_DISABLED != 0);
646 }
647
radio_is_idle(void)648 uint32_t radio_is_idle(void)
649 {
650 return (NRF_RADIO->STATE == 0);
651 }
652
radio_crc_configure(uint32_t polynomial,uint32_t iv)653 void radio_crc_configure(uint32_t polynomial, uint32_t iv)
654 {
655 nrf_radio_crc_configure(NRF_RADIO,
656 RADIO_CRCCNF_LEN_Three,
657 NRF_RADIO_CRC_ADDR_SKIP,
658 polynomial);
659 NRF_RADIO->CRCINIT = iv;
660 }
661
radio_crc_is_valid(void)662 uint32_t radio_crc_is_valid(void)
663 {
664 return (NRF_RADIO->CRCSTATUS != 0);
665 }
666
667 static uint8_t MALIGN(4) _pkt_empty[PDU_EM_LL_SIZE_MAX];
668 static uint8_t MALIGN(4) _pkt_scratch[MAX((HAL_RADIO_PDU_LEN_MAX + 3),
669 PDU_AC_LL_SIZE_MAX)];
670
radio_pkt_empty_get(void)671 void *radio_pkt_empty_get(void)
672 {
673 return _pkt_empty;
674 }
675
radio_pkt_scratch_get(void)676 void *radio_pkt_scratch_get(void)
677 {
678 return _pkt_scratch;
679 }
680
681 #if defined(CONFIG_SOC_NRF52832) && \
682 defined(CONFIG_BT_CTLR_LE_ENC) && \
683 defined(HAL_RADIO_PDU_LEN_MAX) && \
684 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
685 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < (HAL_RADIO_PDU_LEN_MAX - 4)))
686 static uint8_t MALIGN(4) _pkt_decrypt[MAX((HAL_RADIO_PDU_LEN_MAX + 3),
687 PDU_AC_LL_SIZE_MAX)];
688
radio_pkt_decrypt_get(void)689 void *radio_pkt_decrypt_get(void)
690 {
691 return _pkt_decrypt;
692 }
693 #elif !defined(HAL_RADIO_PDU_LEN_MAX)
694 #error "Undefined HAL_RADIO_PDU_LEN_MAX."
695 #endif
696
697 #if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_SYNC_ISO)
698 /* Dedicated Rx PDU Buffer for Control PDU independent of node_rx with BIS Data
699 * PDU buffer. Note this buffer will be used to store whole PDUs, not just the BIG control payload.
700 */
701 static uint8_t pkt_big_ctrl[offsetof(struct pdu_bis, payload) + sizeof(struct pdu_big_ctrl)];
702
radio_pkt_big_ctrl_get(void)703 void *radio_pkt_big_ctrl_get(void)
704 {
705 return pkt_big_ctrl;
706 }
707 #endif /* CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_SYNC_ISO */
708
709 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
710 static uint8_t sw_tifs_toggle;
711 /**
712 * @brief Implementation of Radio operation software switch.
713 *
714 * In case the switch is from RX to TX or from RX to RX and CTEINLINE is enabled then PDU end event
715 * (EVENTS_PHYEND) may be delayed after actual PDU end. The delay occurs when received PDU does not
716 * include CTE. To maintain TIFS the delay must be compensated.
717 * To handle that, two timer EVENTS_COMPARE are prepared: without and without delay compensation.
718 * If EVENTS_CTEPRESENT is fired then EVENTS_COMPARE for delayed EVENTS_PHYEND event is cancelled.
719 * In other case EVENTS_COMPARE for delayed compensation will timeout first and disable group of
720 * PPIs related with the Radio operation switch.
721 * Enable of end event compensation is controller by @p end_evt_delay_en.
722 *
723 * @param dir_curr Current direction the Radio is working: SW_SWITCH_TX or SW_SWITCH_RX
724 * @param dir_next Next direction the Radio is preparing for: SW_SWITCH_TX or SW_SWITCH_RX
725 * @param phy_curr PHY the Radio is working on.
726 * @param flags_curr Flags related with current PHY, the Radio is working on.
727 * @param phy_next Next PHY the Radio is preparing for.
728 * @param flags_next Flags related with next PHY, the Radio is preparing for.
729 * @param end_evt_delay_en Enable end event delay compensation for TIFS after switch from current
730 * direction to next direction.
731 */
sw_switch(uint8_t dir_curr,uint8_t dir_next,uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next,enum radio_end_evt_delay_state end_evt_delay_en)732 void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t flags_curr,
733 uint8_t phy_next, uint8_t flags_next,
734 enum radio_end_evt_delay_state end_evt_delay_en)
735 {
736 uint8_t ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(sw_tifs_toggle);
737 uint8_t cc = SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle);
738 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
739 uint8_t phyend_delay_cc =
740 SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_EVTS_COMP(sw_tifs_toggle);
741 uint8_t radio_enable_ppi =
742 HAL_SW_SWITCH_RADIO_ENABLE_PHYEND_DELAY_COMPENSATION_PPI(sw_tifs_toggle);
743 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
744 uint32_t delay;
745
746 hal_radio_sw_switch_setup(sw_tifs_toggle);
747
748 /* NOTE: As constants are passed to dir_curr and dir_next, the
749 * compiler should optimize out the redundant code path
750 * during the optimization.
751 */
752 if (dir_next == SW_SWITCH_TX) {
753 /* TX */
754
755 /* Calculate delay with respect to current and next PHY.
756 */
757 if (dir_curr == SW_SWITCH_TX) {
758 delay = HAL_RADIO_NS2US_ROUND(
759 hal_radio_tx_ready_delay_ns_get(phy_next,
760 flags_next) +
761 hal_radio_tx_chain_delay_ns_get(phy_curr,
762 flags_curr));
763
764 hal_radio_b2b_txen_on_sw_switch(cc, ppi);
765 } else {
766 /* If RX PHY is LE Coded, calculate for S8 coding.
767 * Assumption being, S8 has higher delay.
768 */
769 delay = HAL_RADIO_NS2US_ROUND(
770 hal_radio_tx_ready_delay_ns_get(phy_next,
771 flags_next) +
772 hal_radio_rx_chain_delay_ns_get(phy_curr, 1));
773
774 hal_radio_txen_on_sw_switch(cc, ppi);
775 }
776
777 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
778 if (dir_curr == SW_SWITCH_RX && end_evt_delay_en == END_EVT_DELAY_ENABLED &&
779 !(phy_curr & PHY_CODED)) {
780 nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc,
781 SW_SWITCH_TIMER->CC[cc] - RADIO_EVENTS_PHYEND_DELAY_US);
782 if (delay < SW_SWITCH_TIMER->CC[cc]) {
783 nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc,
784 (SW_SWITCH_TIMER->CC[phyend_delay_cc] - delay));
785 } else {
786 nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc, 1);
787 }
788
789 hal_radio_sw_switch_phyend_delay_compensation_config_set(radio_enable_ppi,
790 phyend_delay_cc);
791 } else {
792 hal_radio_sw_switch_phyend_delay_compensation_config_clear(radio_enable_ppi,
793 phyend_delay_cc);
794 }
795 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
796
797 #if defined(CONFIG_BT_CTLR_PHY_CODED)
798 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
799 uint8_t ppi_en =
800 HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(sw_tifs_toggle);
801 uint8_t ppi_dis =
802 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(sw_tifs_toggle);
803
804 if (dir_curr == SW_SWITCH_RX && (phy_curr & PHY_CODED)) {
805 /* Switching to TX after RX on LE Coded PHY. */
806
807 uint8_t cc_s2 =
808 SW_SWITCH_TIMER_S2_EVTS_COMP(sw_tifs_toggle);
809
810 uint32_t delay_s2;
811 uint32_t new_cc_s2_value;
812
813 /* Calculate assuming reception on S2 coding scheme. */
814 delay_s2 = HAL_RADIO_NS2US_ROUND(
815 hal_radio_tx_ready_delay_ns_get(phy_next,
816 flags_next) +
817 hal_radio_rx_chain_delay_ns_get(phy_curr, 0));
818
819 new_cc_s2_value = SW_SWITCH_TIMER->CC[cc];
820
821 if (delay_s2 < new_cc_s2_value) {
822 new_cc_s2_value -= delay_s2;
823 } else {
824 new_cc_s2_value = 1;
825 }
826 nrf_timer_cc_set(SW_SWITCH_TIMER, cc_s2,
827 new_cc_s2_value);
828
829 /* Setup the Tx start for S2 using a dedicated compare,
830 * setup a PPI to disable PPI group on that compare
831 * event, and then importantly setup a capture PPI to
832 * disable the Tx start for S8 on RATEBOOST event.
833 */
834 hal_radio_sw_switch_coded_tx_config_set(ppi_en, ppi_dis,
835 cc_s2, sw_tifs_toggle);
836
837 } else {
838 /* Switching to TX after RX on LE 1M/2M PHY.
839 *
840 * NOTE: PHYEND delay compensation and switching between Coded S2 and S8 PHY
841 * may not happen at once. PHYEND delay may not happen when Code PHY
842 * is used. Both functionalities use the same EVENTS_COMPARE channels,
843 * hence when PHYEND delay is applied, coded config clear may not be
844 * called.
845 *
846 * TODO: This has to be refactored. It is temporarily implemented this way
847 * because the code is very fragile and hard to debug.
848 */
849 if (end_evt_delay_en != END_EVT_DELAY_ENABLED) {
850 hal_radio_sw_switch_coded_config_clear(ppi_en, ppi_dis, cc,
851 sw_tifs_toggle);
852 }
853
854 hal_radio_sw_switch_disable_group_clear(ppi_dis, cc, sw_tifs_toggle);
855 }
856 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
857 #endif /* CONFIG_BT_CTLR_PHY_CODED */
858 } else {
859 /* RX */
860
861 /* Calculate delay with respect to current and next PHY. */
862 if (dir_curr) {
863 delay = HAL_RADIO_NS2US_CEIL(
864 hal_radio_rx_ready_delay_ns_get(phy_next,
865 flags_next) +
866 hal_radio_tx_chain_delay_ns_get(phy_curr,
867 flags_curr)) +
868 (EVENT_CLOCK_JITTER_US << 1);
869
870 hal_radio_rxen_on_sw_switch(cc, ppi);
871 } else {
872 delay = HAL_RADIO_NS2US_CEIL(
873 hal_radio_rx_ready_delay_ns_get(phy_next,
874 flags_next) +
875 hal_radio_rx_chain_delay_ns_get(phy_curr,
876 flags_curr)) +
877 (EVENT_CLOCK_JITTER_US << 1);
878
879 hal_radio_b2b_rxen_on_sw_switch(cc, ppi);
880 }
881
882
883 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
884 hal_radio_sw_switch_phyend_delay_compensation_config_clear(radio_enable_ppi,
885 phyend_delay_cc);
886 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
887
888 #if defined(CONFIG_BT_CTLR_PHY_CODED)
889 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
890 if (1) {
891 uint8_t ppi_en = HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(
892 sw_tifs_toggle);
893 uint8_t ppi_dis = HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(
894 sw_tifs_toggle);
895
896 hal_radio_sw_switch_coded_config_clear(ppi_en,
897 ppi_dis, cc, sw_tifs_toggle);
898 hal_radio_sw_switch_disable_group_clear(ppi_dis, cc, sw_tifs_toggle);
899 }
900 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
901 #endif /* CONFIG_BT_CTLR_PHY_CODED */
902 }
903
904 if (delay < SW_SWITCH_TIMER->CC[cc]) {
905 nrf_timer_cc_set(SW_SWITCH_TIMER,
906 cc,
907 (SW_SWITCH_TIMER->CC[cc] - delay));
908 } else {
909 nrf_timer_cc_set(SW_SWITCH_TIMER, cc, 1);
910 }
911
912 hal_radio_nrf_ppi_channels_enable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
913 BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
914
915 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
916 /* NOTE: For single timer configuration nRF5340 shares the DPPI channel being
917 * triggered by Radio End for End time capture and sw_switch DPPI channel toggling
918 * hence always need to capture End time. Or when using single event timer since
919 * the timer is cleared on Radio End, we always need to capture the Radio End
920 * time-stamp.
921 */
922 hal_radio_end_time_capture_ppi_config();
923 #if !defined(CONFIG_SOC_COMPATIBLE_NRF53X)
924 /* The function is not called for nRF5340 single timer configuration because
925 * HAL_SW_SWITCH_TIMER_CLEAR_PPI is equal to HAL_RADIO_END_TIME_CAPTURE_PPI,
926 * so channel is already enabled.
927 */
928 hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
929 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
930 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
931
932 sw_tifs_toggle += 1U;
933 sw_tifs_toggle &= 1U;
934 }
935 #endif /* CONFIG_BT_CTLR_TIFS_HW */
936
radio_switch_complete_and_rx(uint8_t phy_rx)937 void radio_switch_complete_and_rx(uint8_t phy_rx)
938 {
939 #if defined(CONFIG_BT_CTLR_TIFS_HW)
940 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
941 NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
942 RADIO_SHORTS_DISABLED_RXEN_Msk;
943 #else /* !CONFIG_BT_CTLR_TIFS_HW */
944 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
945
946 /* NOTE: As Tx chain delays are negligible constant values (~1 us)
947 * across nRF5x radios, sw_switch assumes the 1M chain delay for
948 * calculations.
949 */
950 sw_switch(SW_SWITCH_TX, SW_SWITCH_RX, SW_SWITCH_PHY_1M, SW_SWITCH_FLAGS_DONTCARE, phy_rx,
951 SW_SWITCH_FLAGS_DONTCARE, END_EVT_DELAY_DISABLED);
952 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
953 }
954
radio_switch_complete_and_tx(uint8_t phy_rx,uint8_t flags_rx,uint8_t phy_tx,uint8_t flags_tx)955 void radio_switch_complete_and_tx(uint8_t phy_rx, uint8_t flags_rx,
956 uint8_t phy_tx, uint8_t flags_tx)
957 {
958 #if defined(CONFIG_BT_CTLR_TIFS_HW)
959 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
960 NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
961 RADIO_SHORTS_DISABLED_TXEN_Msk;
962 #else /* !CONFIG_BT_CTLR_TIFS_HW */
963 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
964
965 sw_switch(SW_SWITCH_RX, SW_SWITCH_TX, phy_rx, flags_rx, phy_tx, flags_tx,
966 END_EVT_DELAY_DISABLED);
967 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
968 }
969
radio_switch_complete_with_delay_compensation_and_tx(uint8_t phy_rx,uint8_t flags_rx,uint8_t phy_tx,uint8_t flags_tx,enum radio_end_evt_delay_state end_delay_en)970 void radio_switch_complete_with_delay_compensation_and_tx(
971 uint8_t phy_rx, uint8_t flags_rx, uint8_t phy_tx, uint8_t flags_tx,
972 enum radio_end_evt_delay_state end_delay_en)
973 {
974 #if defined(CONFIG_BT_CTLR_TIFS_HW)
975 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
976 RADIO_SHORTS_DISABLED_TXEN_Msk;
977 #else /* !CONFIG_BT_CTLR_TIFS_HW */
978 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
979
980 sw_switch(SW_SWITCH_RX, SW_SWITCH_TX, phy_rx, flags_rx, phy_tx, flags_tx, end_delay_en);
981 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
982 }
983
radio_switch_complete_and_b2b_tx(uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next)984 void radio_switch_complete_and_b2b_tx(uint8_t phy_curr, uint8_t flags_curr,
985 uint8_t phy_next, uint8_t flags_next)
986 {
987 #if defined(CONFIG_BT_CTLR_TIFS_HW)
988 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
989 NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
990 RADIO_SHORTS_DISABLED_TXEN_Msk;
991 #else /* !CONFIG_BT_CTLR_TIFS_HW */
992 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
993
994 sw_switch(SW_SWITCH_TX, SW_SWITCH_TX, phy_curr, flags_curr, phy_next, flags_next,
995 END_EVT_DELAY_DISABLED);
996 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
997 }
998
radio_switch_complete_and_b2b_rx(uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next)999 void radio_switch_complete_and_b2b_rx(uint8_t phy_curr, uint8_t flags_curr,
1000 uint8_t phy_next, uint8_t flags_next)
1001 {
1002 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1003 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
1004 NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
1005 RADIO_SHORTS_DISABLED_RXEN_Msk;
1006 #else /* !CONFIG_BT_CTLR_TIFS_HW */
1007 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
1008
1009 sw_switch(SW_SWITCH_RX, SW_SWITCH_RX, phy_curr, flags_curr, phy_next, flags_next,
1010 END_EVT_DELAY_DISABLED);
1011 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1012 }
1013
radio_switch_complete_and_b2b_tx_disable(void)1014 void radio_switch_complete_and_b2b_tx_disable(void)
1015 {
1016 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1017 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1018 #else /* CONFIG_BT_CTLR_TIFS_HW */
1019 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1020 hal_radio_sw_switch_b2b_tx_disable(sw_tifs_toggle);
1021 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1022 }
1023
radio_switch_complete_and_b2b_rx_disable(void)1024 void radio_switch_complete_and_b2b_rx_disable(void)
1025 {
1026 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1027 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1028 #else /* CONFIG_BT_CTLR_TIFS_HW */
1029 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1030 hal_radio_sw_switch_b2b_rx_disable(sw_tifs_toggle);
1031 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1032 }
1033
radio_switch_complete_and_disable(void)1034 void radio_switch_complete_and_disable(void)
1035 {
1036 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1037 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1038 #else /* CONFIG_BT_CTLR_TIFS_HW */
1039 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk);
1040 hal_radio_sw_switch_disable();
1041 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1042 }
1043
radio_phy_flags_rx_get(void)1044 uint8_t radio_phy_flags_rx_get(void)
1045 {
1046 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1047 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1048 return (NRF_RADIO->EVENTS_RATEBOOST) ? 0U : 1U;
1049 #else /* !CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1050 return 0;
1051 #endif /* !CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1052 #else /* !CONFIG_BT_CTLR_PHY_CODED */
1053 return 0;
1054 #endif /* !CONFIG_BT_CTLR_PHY_CODED */
1055 }
1056
radio_rssi_measure(void)1057 void radio_rssi_measure(void)
1058 {
1059 NRF_RADIO->SHORTS |=
1060 (RADIO_SHORTS_ADDRESS_RSSISTART_Msk |
1061 #if defined(CONFIG_SOC_SERIES_NRF51X) || \
1062 defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
1063 defined(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET)
1064 RADIO_SHORTS_DISABLED_RSSISTOP_Msk |
1065 #endif
1066 0);
1067 }
1068
radio_rssi_get(void)1069 uint32_t radio_rssi_get(void)
1070 {
1071 return NRF_RADIO->RSSISAMPLE;
1072 }
1073
radio_rssi_status_reset(void)1074 void radio_rssi_status_reset(void)
1075 {
1076 #if defined(CONFIG_SOC_SERIES_NRF51X) || \
1077 defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
1078 defined(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET)
1079 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_RSSIEND);
1080 #endif
1081 }
1082
radio_rssi_is_ready(void)1083 uint32_t radio_rssi_is_ready(void)
1084 {
1085 #if defined(CONFIG_SOC_SERIES_NRF51X) || \
1086 defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
1087 defined(CONFIG_SOC_COMPATIBLE_NRF5340_CPUNET)
1088 return (NRF_RADIO->EVENTS_RSSIEND != 0);
1089 #else
1090 return 1U;
1091 #endif
1092 }
1093
radio_filter_configure(uint8_t bitmask_enable,uint8_t bitmask_addr_type,uint8_t * bdaddr)1094 void radio_filter_configure(uint8_t bitmask_enable, uint8_t bitmask_addr_type,
1095 uint8_t *bdaddr)
1096 {
1097 uint8_t index;
1098
1099 for (index = 0U; index < 8; index++) {
1100 NRF_RADIO->DAB[index] = ((uint32_t)bdaddr[3] << 24) |
1101 ((uint32_t)bdaddr[2] << 16) |
1102 ((uint32_t)bdaddr[1] << 8) |
1103 bdaddr[0];
1104 NRF_RADIO->DAP[index] = ((uint32_t)bdaddr[5] << 8) | bdaddr[4];
1105 bdaddr += 6;
1106 }
1107
1108 NRF_RADIO->DACNF = ((uint32_t)bitmask_addr_type << 8) | bitmask_enable;
1109 }
1110
radio_filter_disable(void)1111 void radio_filter_disable(void)
1112 {
1113 NRF_RADIO->DACNF &= ~(0x000000FF);
1114 }
1115
radio_filter_status_reset(void)1116 void radio_filter_status_reset(void)
1117 {
1118 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_DEVMATCH);
1119 }
1120
radio_filter_has_match(void)1121 uint32_t radio_filter_has_match(void)
1122 {
1123 return (NRF_RADIO->EVENTS_DEVMATCH != 0);
1124 }
1125
radio_filter_match_get(void)1126 uint32_t radio_filter_match_get(void)
1127 {
1128 return NRF_RADIO->DAI;
1129 }
1130
radio_bc_configure(uint32_t n)1131 void radio_bc_configure(uint32_t n)
1132 {
1133 NRF_RADIO->BCC = n;
1134 NRF_RADIO->SHORTS |= RADIO_SHORTS_ADDRESS_BCSTART_Msk;
1135 }
1136
radio_bc_status_reset(void)1137 void radio_bc_status_reset(void)
1138 {
1139 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH);
1140 }
1141
radio_bc_has_match(void)1142 uint32_t radio_bc_has_match(void)
1143 {
1144 return (NRF_RADIO->EVENTS_BCMATCH != 0);
1145 }
1146
radio_tmr_status_reset(void)1147 void radio_tmr_status_reset(void)
1148 {
1149 nrf_rtc_event_disable(NRF_RTC, RTC_EVTENCLR_COMPARE2_Msk);
1150
1151 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1152 hal_trigger_crypt_ppi_disable();
1153 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1154
1155 hal_radio_nrf_ppi_channels_disable(
1156 BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) |
1157 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) |
1158 BIT(HAL_EVENT_TIMER_START_PPI) |
1159 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1160 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1161 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1162 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1163 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1164 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1165 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1166 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1167 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1168 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1169 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1170 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1171 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1172 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1173 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1174 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1175 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1176 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1177 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1178 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1179 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1180 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1181 BIT(HAL_TRIGGER_CRYPT_PPI) |
1182 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1183 0);
1184 }
1185
radio_tmr_tx_status_reset(void)1186 void radio_tmr_tx_status_reset(void)
1187 {
1188 nrf_rtc_event_disable(NRF_RTC, RTC_EVTENCLR_COMPARE2_Msk);
1189
1190 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1191 hal_trigger_crypt_ppi_disable();
1192 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1193
1194 hal_radio_nrf_ppi_channels_disable(
1195 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI != HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && \
1196 !defined(DPPI_PRESENT)
1197 BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) |
1198 #endif /* (HAL_RADIO_ENABLE_TX_ON_TICK_PPI !=
1199 * HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && !DPPI_PRESENT
1200 */
1201 BIT(HAL_EVENT_TIMER_START_PPI) |
1202 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1203 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1204 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1205 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1206 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1207 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1208 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1209 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1210 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1211 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1212 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1213 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1214 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1215 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1216 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1217 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1218 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1219 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1220 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1221 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1222 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1223 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1224 BIT(HAL_TRIGGER_CRYPT_PPI) |
1225 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1226 0);
1227 }
1228
radio_tmr_rx_status_reset(void)1229 void radio_tmr_rx_status_reset(void)
1230 {
1231 nrf_rtc_event_disable(NRF_RTC, RTC_EVTENCLR_COMPARE2_Msk);
1232
1233 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1234 hal_trigger_crypt_ppi_disable();
1235 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1236
1237 hal_radio_nrf_ppi_channels_disable(
1238 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI != HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && \
1239 !defined(DPPI_PRESENT)
1240 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) |
1241 #endif /* (HAL_RADIO_ENABLE_TX_ON_TICK_PPI !=
1242 * HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && !DPPI_PRESENT
1243 */
1244 BIT(HAL_EVENT_TIMER_START_PPI) |
1245 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1246 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1247 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1248 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1249 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1250 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1251 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1252 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1253 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1254 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1255 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1256 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1257 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1258 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1259 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1260 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1261 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1262 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1263 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1264 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1265 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1266 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1267 BIT(HAL_TRIGGER_CRYPT_PPI) |
1268 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
1269 0);
1270 }
1271
radio_tmr_tx_enable(void)1272 void radio_tmr_tx_enable(void)
1273 {
1274 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1275 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1276 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI)
1277 hal_radio_enable_on_tick_ppi_config_and_enable(1U);
1278 #endif /* HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI */
1279 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1280 }
1281
radio_tmr_rx_enable(void)1282 void radio_tmr_rx_enable(void)
1283 {
1284 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1285 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1286 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI)
1287 hal_radio_enable_on_tick_ppi_config_and_enable(0U);
1288 #endif /* HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI */
1289 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1290 }
1291
radio_tmr_tx_disable(void)1292 void radio_tmr_tx_disable(void)
1293 {
1294 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1295 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_TXEN);
1296 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1297 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1298 }
1299
radio_tmr_rx_disable(void)1300 void radio_tmr_rx_disable(void)
1301 {
1302 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1303 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_RXEN);
1304 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1305 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_SOC_COMPATIBLE_NRF54LX */
1306 }
1307
radio_tmr_tifs_set(uint32_t tifs)1308 void radio_tmr_tifs_set(uint32_t tifs)
1309 {
1310 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1311 NRF_RADIO->TIFS = tifs;
1312 #else /* !CONFIG_BT_CTLR_TIFS_HW */
1313 nrf_timer_cc_set(SW_SWITCH_TIMER,
1314 SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle), tifs);
1315 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1316 }
1317
radio_tmr_start(uint8_t trx,uint32_t ticks_start,uint32_t remainder)1318 uint32_t radio_tmr_start(uint8_t trx, uint32_t ticks_start, uint32_t remainder)
1319 {
1320 hal_ticker_remove_jitter(&ticks_start, &remainder);
1321
1322 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_CLEAR);
1323 EVENT_TIMER->MODE = 0;
1324 EVENT_TIMER->PRESCALER = HAL_EVENT_TIMER_PRESCALER_VALUE;
1325 EVENT_TIMER->BITMODE = 2; /* 24 - bit */
1326
1327 nrf_timer_cc_set(EVENT_TIMER, 0, remainder);
1328
1329 nrf_rtc_cc_set(NRF_RTC, 2, ticks_start);
1330 nrf_rtc_event_enable(NRF_RTC, RTC_EVTENSET_COMPARE2_Msk);
1331
1332 hal_event_timer_start_ppi_config();
1333 hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI));
1334
1335 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1336
1337 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1338 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1339 last_pdu_end_us = 0U;
1340
1341 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1342 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_CLEAR);
1343 SW_SWITCH_TIMER->MODE = 0;
1344 SW_SWITCH_TIMER->PRESCALER = HAL_EVENT_TIMER_PRESCALER_VALUE;
1345 SW_SWITCH_TIMER->BITMODE = 0; /* 16 bit */
1346 /* FIXME: start along with EVENT_TIMER, to save power */
1347 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_START);
1348 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1349
1350 hal_sw_switch_timer_clear_ppi_config();
1351
1352 #if !defined(CONFIG_BT_CTLR_PHY_CODED) || \
1353 !defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1354 /* Software switch group's disable PPI can be configured one time here
1355 * at timer setup when only 1M and/or 2M is supported.
1356 */
1357 hal_radio_group_task_disable_ppi_setup();
1358
1359 #else /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1360 /* Software switch group's disable PPI needs to be configured at every
1361 * sw_switch() as they depend on the actual PHYs used in TX/RX mode.
1362 */
1363 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1364 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1365
1366 return remainder;
1367 }
1368
radio_tmr_start_tick(uint8_t trx,uint32_t tick)1369 uint32_t radio_tmr_start_tick(uint8_t trx, uint32_t tick)
1370 {
1371 uint32_t remainder_us;
1372
1373 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_STOP);
1374 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_CLEAR);
1375
1376 /* Setup compare event with min. 1 us offset */
1377 remainder_us = 1;
1378 nrf_timer_cc_set(EVENT_TIMER, 0, remainder_us);
1379
1380 nrf_rtc_cc_set(NRF_RTC, 2, tick);
1381 nrf_rtc_event_enable(NRF_RTC, RTC_EVTENSET_COMPARE2_Msk);
1382
1383 hal_event_timer_start_ppi_config();
1384 hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI));
1385
1386 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1387
1388 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1389 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1390 last_pdu_end_us = 0U;
1391 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1392 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1393 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
1394 * because of calls to radio_disable() and
1395 * radio_switch_complete_and_disable() inside a radio event call
1396 * hal_radio_sw_switch_disable(), which in the case of nRF53
1397 * cancels the task subscription.
1398 */
1399 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
1400 * event. Consider a new interface to only set the task, or
1401 * change the design to not clear task subscription inside a
1402 * radio event but when the radio event is done.
1403 */
1404 hal_sw_switch_timer_clear_ppi_config();
1405 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X || CONFIG_SOC_COMPATIBLE_NRF54LX */
1406 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1407
1408 return remainder_us;
1409 }
1410
radio_tmr_start_us(uint8_t trx,uint32_t start_us)1411 uint32_t radio_tmr_start_us(uint8_t trx, uint32_t start_us)
1412 {
1413 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1414
1415 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1416 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1417 last_pdu_end_us = 0U;
1418 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1419 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X) || defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1420 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
1421 * because of calls to radio_disable() and
1422 * radio_switch_complete_and_disable() inside a radio event call
1423 * hal_radio_sw_switch_disable(), which in the case of nRF53
1424 * cancels the task subscription.
1425 */
1426 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
1427 * event. Consider a new interface to only set the task, or
1428 * change the design to not clear task subscription inside a
1429 * radio event but when the radio event is done.
1430 */
1431 hal_sw_switch_timer_clear_ppi_config();
1432 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X || CONFIG_SOC_COMPATIBLE_NRF54LX */
1433 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1434
1435 /* start_us could be the current count in the timer */
1436 uint32_t now_us = start_us;
1437
1438 /* Setup PPI while determining the latency in doing so */
1439 do {
1440 /* Set start to be, now plus the determined latency */
1441 start_us = (now_us << 1) - start_us;
1442
1443 /* Setup compare event with min. 1 us offset */
1444 nrf_timer_event_clear(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE0);
1445 nrf_timer_cc_set(EVENT_TIMER, 0, start_us + 1U);
1446
1447 /* Capture the current time */
1448 nrf_timer_task_trigger(EVENT_TIMER,
1449 HAL_EVENT_TIMER_SAMPLE_TASK);
1450
1451 now_us = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1452 } while ((now_us > start_us) && (EVENT_TIMER->EVENTS_COMPARE[0] == 0U));
1453
1454 return start_us + 1U;
1455 }
1456
radio_tmr_start_now(uint8_t trx)1457 uint32_t radio_tmr_start_now(uint8_t trx)
1458 {
1459 uint32_t start_us;
1460
1461 /* PPI/DPPI configuration will be done in radio_tmr_start_us() */
1462
1463 /* Capture the current time */
1464 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1465 start_us = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1466
1467 /* Setup radio start at current time */
1468 start_us = radio_tmr_start_us(trx, start_us);
1469
1470 return start_us;
1471 }
1472
radio_tmr_start_get(void)1473 uint32_t radio_tmr_start_get(void)
1474 {
1475 return nrf_rtc_cc_get(NRF_RTC, 2);
1476 }
1477
radio_tmr_stop(void)1478 void radio_tmr_stop(void)
1479 {
1480 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_STOP);
1481 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_SHUTDOWN);
1482
1483 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1484 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_STOP);
1485 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_SHUTDOWN);
1486 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1487
1488 #if defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1489 NRF_POWER->TASKS_LOWPWR = 1U;
1490 #endif /* CONFIG_SOC_COMPATIBLE_NRF54LX */
1491 }
1492
radio_tmr_hcto_configure(uint32_t hcto)1493 void radio_tmr_hcto_configure(uint32_t hcto)
1494 {
1495 nrf_timer_cc_set(EVENT_TIMER, 1, hcto);
1496
1497 hal_radio_recv_timeout_cancel_ppi_config();
1498 hal_radio_disable_on_hcto_ppi_config();
1499 hal_radio_nrf_ppi_channels_enable(
1500 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1501 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI));
1502 }
1503
radio_tmr_aa_capture(void)1504 void radio_tmr_aa_capture(void)
1505 {
1506 hal_radio_ready_time_capture_ppi_config();
1507 hal_radio_recv_timeout_cancel_ppi_config();
1508 hal_radio_nrf_ppi_channels_enable(
1509 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1510 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI));
1511 }
1512
radio_tmr_aa_get(void)1513 uint32_t radio_tmr_aa_get(void)
1514 {
1515 return EVENT_TIMER->CC[1];
1516 }
1517
1518 static uint32_t radio_tmr_aa;
1519
radio_tmr_aa_save(uint32_t aa)1520 void radio_tmr_aa_save(uint32_t aa)
1521 {
1522 radio_tmr_aa = aa;
1523 }
1524
radio_tmr_aa_restore(void)1525 uint32_t radio_tmr_aa_restore(void)
1526 {
1527 /* NOTE: we dont need to restore for now, but return the saved value. */
1528 return radio_tmr_aa;
1529 }
1530
radio_tmr_ready_get(void)1531 uint32_t radio_tmr_ready_get(void)
1532 {
1533 return EVENT_TIMER->CC[0];
1534 }
1535
1536 static uint32_t radio_tmr_ready;
1537
radio_tmr_ready_save(uint32_t ready)1538 void radio_tmr_ready_save(uint32_t ready)
1539 {
1540 radio_tmr_ready = ready;
1541 }
1542
radio_tmr_ready_restore(void)1543 uint32_t radio_tmr_ready_restore(void)
1544 {
1545 return radio_tmr_ready;
1546 }
1547
radio_tmr_end_capture(void)1548 void radio_tmr_end_capture(void)
1549 {
1550 /* NOTE: nRF5340 for single timer configuration shares the DPPI channel being triggered
1551 * by Radio End for End time capture and sw_switch DPPI channel toggling hence
1552 * always need to capture End time. Hence, the below code is present in
1553 * hal_sw_switch_timer_clear_ppi_config() and sw_switch(). There is no need to
1554 * configure the channel again in this function.
1555 */
1556 #if !defined(CONFIG_SOC_COMPATIBLE_NRF53X) || \
1557 (defined(CONFIG_SOC_COMPATIBLE_NRF53X) && !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER))
1558 hal_radio_end_time_capture_ppi_config();
1559 hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
1560 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X ||
1561 * (CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1562 */
1563 }
1564
radio_tmr_end_get(void)1565 uint32_t radio_tmr_end_get(void)
1566 {
1567 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1568 return last_pdu_end_us;
1569 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1570 return EVENT_TIMER->CC[2];
1571 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1572 }
1573
radio_tmr_tifs_base_get(void)1574 uint32_t radio_tmr_tifs_base_get(void)
1575 {
1576 return radio_tmr_end_get();
1577 }
1578
1579 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1580 static uint32_t tmr_sample_val;
1581 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1582
radio_tmr_sample(void)1583 void radio_tmr_sample(void)
1584 {
1585 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1586 uint32_t cc;
1587
1588 cc = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1589 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1590
1591 tmr_sample_val = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1592 nrf_timer_cc_set(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_CC_OFFSET, cc);
1593
1594 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1595 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1596 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1597 }
1598
radio_tmr_sample_get(void)1599 uint32_t radio_tmr_sample_get(void)
1600 {
1601 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1602 return tmr_sample_val;
1603 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1604 return EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1605 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1606 }
1607
1608 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || \
1609 defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
radio_gpio_pa_lna_init(void)1610 int radio_gpio_pa_lna_init(void)
1611 {
1612 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
1613 if (nrfx_gpiote_channel_alloc(&gpiote_palna, &gpiote_ch_palna) != NRFX_SUCCESS) {
1614 return -ENOMEM;
1615 }
1616 #endif
1617
1618 #if defined(NRF_GPIO_PDN_PIN)
1619 if (nrfx_gpiote_channel_alloc(&gpiote_pdn, &gpiote_ch_pdn) != NRFX_SUCCESS) {
1620 return -ENOMEM;
1621 }
1622 #endif
1623
1624 #if defined(NRF_GPIO_CSN_PIN)
1625 if (nrfx_gpiote_channel_alloc(&gpiote_csn, &gpiote_ch_csn) != NRFX_SUCCESS) {
1626 return -ENOMEM;
1627 }
1628 #endif
1629
1630 return 0;
1631 }
1632
radio_gpio_pa_lna_deinit(void)1633 void radio_gpio_pa_lna_deinit(void)
1634 {
1635 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
1636 (void)nrfx_gpiote_channel_free(&gpiote_palna, gpiote_ch_palna);
1637 #endif
1638
1639 #if defined(NRF_GPIO_PDN_PIN)
1640 (void)nrfx_gpiote_channel_free(&gpiote_pdn, gpiote_ch_pdn);
1641 #endif
1642
1643 #if defined(NRF_GPIO_CSN_PIN)
1644 (void)nrfx_gpiote_channel_free(&gpiote_csn, gpiote_ch_csn);
1645 #endif
1646 }
1647
1648 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
radio_gpio_pa_setup(void)1649 void radio_gpio_pa_setup(void)
1650 {
1651 gpiote_palna.p_reg->CONFIG[gpiote_ch_palna] =
1652 (GPIOTE_CONFIG_MODE_Task <<
1653 GPIOTE_CONFIG_MODE_Pos) |
1654 (NRF_GPIO_PA_PSEL <<
1655 GPIOTE_CONFIG_PSEL_Pos) |
1656 (GPIOTE_CONFIG_POLARITY_Toggle <<
1657 GPIOTE_CONFIG_POLARITY_Pos) |
1658 (OUTINIT_INACTIVE(NRF_GPIO_PA_FLAGS) <<
1659 GPIOTE_CONFIG_OUTINIT_Pos);
1660
1661 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1662 hal_pa_ppi_setup();
1663 radio_gpio_pdn_setup();
1664 radio_gpio_csn_setup();
1665 #endif
1666 }
1667 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
1668
1669 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
radio_gpio_lna_setup(void)1670 void radio_gpio_lna_setup(void)
1671 {
1672 gpiote_palna.p_reg->CONFIG[gpiote_ch_palna] =
1673 (GPIOTE_CONFIG_MODE_Task <<
1674 GPIOTE_CONFIG_MODE_Pos) |
1675 (NRF_GPIO_LNA_PSEL <<
1676 GPIOTE_CONFIG_PSEL_Pos) |
1677 (GPIOTE_CONFIG_POLARITY_Toggle <<
1678 GPIOTE_CONFIG_POLARITY_Pos) |
1679 (OUTINIT_INACTIVE(NRF_GPIO_LNA_FLAGS) <<
1680 GPIOTE_CONFIG_OUTINIT_Pos);
1681
1682 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1683 hal_lna_ppi_setup();
1684 radio_gpio_pdn_setup();
1685 radio_gpio_csn_setup();
1686 #endif
1687 }
1688
radio_gpio_pdn_setup(void)1689 void radio_gpio_pdn_setup(void)
1690 {
1691 /* Note: the pdn-gpios property is optional. */
1692 #if defined(NRF_GPIO_PDN)
1693 gpiote_pdn.p_reg->CONFIG[gpiote_ch_pdn] =
1694 (GPIOTE_CONFIG_MODE_Task <<
1695 GPIOTE_CONFIG_MODE_Pos) |
1696 (NRF_GPIO_PDN_PSEL <<
1697 GPIOTE_CONFIG_PSEL_Pos) |
1698 (GPIOTE_CONFIG_POLARITY_Toggle <<
1699 GPIOTE_CONFIG_POLARITY_Pos) |
1700 (OUTINIT_INACTIVE(NRF_GPIO_PDN_FLAGS) <<
1701 GPIOTE_CONFIG_OUTINIT_Pos);
1702 #endif /* NRF_GPIO_PDN_PIN */
1703 }
1704
radio_gpio_csn_setup(void)1705 void radio_gpio_csn_setup(void)
1706 {
1707 /* Note: the spi-if property is optional. */
1708 #if defined(NRF_GPIO_CSN_PIN)
1709 gpiote_csn.p_reg->CONFIG[gpiote_ch_csn] =
1710 (GPIOTE_CONFIG_MODE_Task <<
1711 GPIOTE_CONFIG_MODE_Pos) |
1712 (NRF_GPIO_CSN_PSEL <<
1713 GPIOTE_CONFIG_PSEL_Pos) |
1714 (GPIOTE_CONFIG_POLARITY_Toggle <<
1715 GPIOTE_CONFIG_POLARITY_Pos) |
1716 (OUTINIT_INACTIVE(NRF_GPIO_CSN_FLAGS) <<
1717 GPIOTE_CONFIG_OUTINIT_Pos);
1718 #endif /* NRF_GPIO_CSN_PIN */
1719 }
1720
radio_gpio_lna_on(void)1721 void radio_gpio_lna_on(void)
1722 {
1723 if (ACTIVE_LOW(NRF_GPIO_LNA_FLAGS)) {
1724 NRF_GPIO_LNA->OUTCLR = BIT(NRF_GPIO_LNA_PIN);
1725 } else {
1726 NRF_GPIO_LNA->OUTSET = BIT(NRF_GPIO_LNA_PIN);
1727 }
1728 }
1729
radio_gpio_lna_off(void)1730 void radio_gpio_lna_off(void)
1731 {
1732 if (ACTIVE_LOW(NRF_GPIO_LNA_FLAGS)) {
1733 NRF_GPIO_LNA->OUTSET = BIT(NRF_GPIO_LNA_PIN);
1734 } else {
1735 NRF_GPIO_LNA->OUTCLR = BIT(NRF_GPIO_LNA_PIN);
1736 }
1737 }
1738 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
1739
radio_gpio_pa_lna_enable(uint32_t trx_us)1740 void radio_gpio_pa_lna_enable(uint32_t trx_us)
1741 {
1742 nrf_timer_cc_set(EVENT_TIMER, 2, trx_us);
1743 #if defined(HAL_RADIO_FEM_IS_NRF21540) && DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios)
1744 nrf_timer_cc_set(EVENT_TIMER, 3, (trx_us - NRF_GPIO_PDN_OFFSET));
1745 hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1746 BIT(HAL_DISABLE_PALNA_PPI) |
1747 BIT(HAL_ENABLE_FEM_PPI) |
1748 BIT(HAL_DISABLE_FEM_PPI));
1749 #else
1750 hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1751 BIT(HAL_DISABLE_PALNA_PPI));
1752 #endif
1753 }
1754
radio_gpio_pa_lna_disable(void)1755 void radio_gpio_pa_lna_disable(void)
1756 {
1757 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1758 hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1759 BIT(HAL_DISABLE_PALNA_PPI) |
1760 BIT(HAL_ENABLE_FEM_PPI) |
1761 BIT(HAL_DISABLE_FEM_PPI));
1762 gpiote_palna.p_reg->CONFIG[gpiote_ch_palna] = 0;
1763 gpiote_pdn.p_reg->CONFIG[gpiote_ch_pdn] = 0;
1764 gpiote_csn.p_reg->CONFIG[gpiote_ch_csn] = 0;
1765 #else
1766 hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1767 BIT(HAL_DISABLE_PALNA_PPI));
1768 gpiote_palna.p_reg->CONFIG[gpiote_ch_palna] = 0;
1769 #endif
1770 }
1771 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN || HAL_RADIO_GPIO_HAVE_LNA_PIN */
1772
1773 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
1774 static uint8_t MALIGN(4) _ccm_scratch[(HAL_RADIO_PDU_LEN_MAX - 4) + 16];
1775
1776 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_SYNC_ISO)
radio_ccm_ext_rx_pkt_set(struct ccm * cnf,uint8_t phy,uint8_t pdu_type,void * pkt)1777 static void *radio_ccm_ext_rx_pkt_set(struct ccm *cnf, uint8_t phy, uint8_t pdu_type, void *pkt)
1778 {
1779 uint32_t mode;
1780
1781 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Disabled;
1782 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Enabled;
1783 mode = (CCM_MODE_MODE_Decryption << CCM_MODE_MODE_Pos) &
1784 CCM_MODE_MODE_Msk;
1785
1786 #if !defined(CONFIG_SOC_SERIES_NRF51X)
1787 /* Enable CCM support for 8-bit length field PDUs. */
1788 mode |= (CCM_MODE_LENGTH_Extended << CCM_MODE_LENGTH_Pos) &
1789 CCM_MODE_LENGTH_Msk;
1790
1791 /* Select CCM data rate based on current PHY in use. */
1792 switch (phy) {
1793 default:
1794 case PHY_1M:
1795 mode |= (CCM_MODE_DATARATE_1Mbit <<
1796 CCM_MODE_DATARATE_Pos) &
1797 CCM_MODE_DATARATE_Msk;
1798
1799 if (false) {
1800
1801 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1802 } else if (pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) {
1803 /* When direction finding CTE receive feature is enabled then on-the-fly
1804 * PDU parsing for CTEInfo is always done. In such situation, the CCM
1805 * TASKS_CRYPT must be started with short delay. That give the Radio time
1806 * to store received bits in shared memory.
1807 */
1808 radio_bc_configure(CCM_TASKS_CRYPT_DELAY_BITS);
1809 radio_bc_status_reset();
1810 hal_trigger_crypt_by_bcmatch_ppi_config();
1811 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_DELAY_PPI));
1812 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1813 } else {
1814 hal_trigger_crypt_ppi_config();
1815 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1816 }
1817 break;
1818
1819 case PHY_2M:
1820 mode |= (CCM_MODE_DATARATE_2Mbit <<
1821 CCM_MODE_DATARATE_Pos) &
1822 CCM_MODE_DATARATE_Msk;
1823
1824 hal_trigger_crypt_ppi_config();
1825 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1826
1827 break;
1828
1829 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1830 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1831 case PHY_CODED:
1832 mode |= (CCM_MODE_DATARATE_125Kbps <<
1833 CCM_MODE_DATARATE_Pos) &
1834 CCM_MODE_DATARATE_Msk;
1835
1836 NRF_CCM->RATEOVERRIDE =
1837 (CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps <<
1838 CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) &
1839 CCM_RATEOVERRIDE_RATEOVERRIDE_Msk;
1840
1841 hal_trigger_rateoverride_ppi_config();
1842 hal_radio_nrf_ppi_channels_enable(
1843 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI));
1844
1845 hal_trigger_crypt_ppi_config();
1846 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1847
1848 break;
1849 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1850 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1851 }
1852 #endif /* !CONFIG_SOC_SERIES_NRF51X */
1853
1854 #if !defined(CONFIG_SOC_SERIES_NRF51X) && \
1855 !defined(CONFIG_SOC_NRF52832) && \
1856 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
1857 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < ((HAL_RADIO_PDU_LEN_MAX) - 4U)))
1858 uint8_t max_len = (NRF_RADIO->PCNF1 & RADIO_PCNF1_MAXLEN_Msk) >>
1859 RADIO_PCNF1_MAXLEN_Pos;
1860
1861 /* MAXPACKETSIZE value 0x001B (27) - 0x00FB (251) bytes */
1862 NRF_CCM->MAXPACKETSIZE = max_len - 4U;
1863 #endif
1864
1865 #if defined(CONFIG_HAS_HW_NRF_CCM_HEADERMASK)
1866 switch (pdu_type) {
1867 case RADIO_PKT_CONF_PDU_TYPE_BIS:
1868 NRF_CCM->HEADERMASK = 0xC3; /* mask CSSN and CSTF */
1869 break;
1870 case RADIO_PKT_CONF_PDU_TYPE_CIS:
1871 NRF_CCM->HEADERMASK = 0xA3; /* mask SN, NESN, CIE and NPI */
1872 break;
1873 default:
1874 /* Using default reset value of HEADERMASK */
1875 NRF_CCM->HEADERMASK = 0xE3; /* mask SN, NESN and MD */
1876 break;
1877 }
1878 #endif /* CONFIG_HAS_HW_NRF_CCM_HEADERMASK */
1879
1880 NRF_CCM->MODE = mode;
1881 NRF_CCM->CNFPTR = (uint32_t)cnf;
1882 NRF_CCM->INPTR = (uint32_t)_pkt_scratch;
1883 NRF_CCM->OUTPTR = (uint32_t)pkt;
1884 NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
1885 NRF_CCM->SHORTS = 0;
1886 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDKSGEN);
1887 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDCRYPT);
1888 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ERROR);
1889
1890 nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
1891
1892 return _pkt_scratch;
1893 }
1894
radio_ccm_rx_pkt_set(struct ccm * cnf,uint8_t phy,void * pkt)1895 void *radio_ccm_rx_pkt_set(struct ccm *cnf, uint8_t phy, void *pkt)
1896 {
1897 return radio_ccm_ext_rx_pkt_set(cnf, phy, RADIO_PKT_CONF_PDU_TYPE_DC, pkt);
1898 }
1899
radio_ccm_iso_rx_pkt_set(struct ccm * cnf,uint8_t phy,uint8_t pdu_type,void * pkt)1900 void *radio_ccm_iso_rx_pkt_set(struct ccm *cnf, uint8_t phy, uint8_t pdu_type, void *pkt)
1901 {
1902 return radio_ccm_ext_rx_pkt_set(cnf, phy, pdu_type, pkt);
1903 }
1904 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_SYNC_ISO */
1905
1906 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_ADV_ISO)
radio_ccm_ext_tx_pkt_set(struct ccm * cnf,uint8_t pdu_type,void * pkt)1907 static void *radio_ccm_ext_tx_pkt_set(struct ccm *cnf, uint8_t pdu_type, void *pkt)
1908 {
1909 uint32_t mode;
1910
1911 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Disabled;
1912 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Enabled;
1913 mode = (CCM_MODE_MODE_Encryption << CCM_MODE_MODE_Pos) &
1914 CCM_MODE_MODE_Msk;
1915 #if defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
1916 defined(CONFIG_SOC_COMPATIBLE_NRF53X) || \
1917 defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
1918 /* Enable CCM support for 8-bit length field PDUs. */
1919 mode |= (CCM_MODE_LENGTH_Extended << CCM_MODE_LENGTH_Pos) &
1920 CCM_MODE_LENGTH_Msk;
1921
1922 /* NOTE: use fastest data rate as tx data needs to be prepared before
1923 * radio Tx on any PHY.
1924 */
1925 mode |= (CCM_MODE_DATARATE_2Mbit << CCM_MODE_DATARATE_Pos) &
1926 CCM_MODE_DATARATE_Msk;
1927 #endif
1928
1929 #if !defined(CONFIG_SOC_SERIES_NRF51X) && \
1930 !defined(CONFIG_SOC_NRF52832) && \
1931 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
1932 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < ((HAL_RADIO_PDU_LEN_MAX) - 4)))
1933 uint8_t max_len = (NRF_RADIO->PCNF1 & RADIO_PCNF1_MAXLEN_Msk) >>
1934 RADIO_PCNF1_MAXLEN_Pos;
1935
1936 /* MAXPACKETSIZE value 0x001B (27) - 0x00FB (251) bytes */
1937 NRF_CCM->MAXPACKETSIZE = max_len - 4U;
1938 #endif
1939
1940 #if defined(CONFIG_HAS_HW_NRF_CCM_HEADERMASK)
1941 switch (pdu_type) {
1942 case RADIO_PKT_CONF_PDU_TYPE_BIS:
1943 NRF_CCM->HEADERMASK = 0xC3; /* mask CSSN and CSTF */
1944 break;
1945 case RADIO_PKT_CONF_PDU_TYPE_CIS:
1946 NRF_CCM->HEADERMASK = 0xA3; /* mask SN, NESN, CIE and NPI */
1947 break;
1948 default:
1949 /* Using default reset value of HEADERMASK */
1950 NRF_CCM->HEADERMASK = 0xE3; /* mask SN, NESN and MD */
1951 break;
1952 }
1953 #endif /* CONFIG_HAS_HW_NRF_CCM_HEADERMASK */
1954
1955 NRF_CCM->MODE = mode;
1956 NRF_CCM->CNFPTR = (uint32_t)cnf;
1957 NRF_CCM->INPTR = (uint32_t)pkt;
1958 NRF_CCM->OUTPTR = (uint32_t)_pkt_scratch;
1959 NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
1960 NRF_CCM->SHORTS = CCM_SHORTS_ENDKSGEN_CRYPT_Msk;
1961 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDKSGEN);
1962 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDCRYPT);
1963 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ERROR);
1964
1965 nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
1966
1967 return _pkt_scratch;
1968 }
1969
radio_ccm_tx_pkt_set(struct ccm * cnf,void * pkt)1970 void *radio_ccm_tx_pkt_set(struct ccm *cnf, void *pkt)
1971 {
1972 return radio_ccm_ext_tx_pkt_set(cnf, RADIO_PKT_CONF_PDU_TYPE_DC, pkt);
1973 }
1974
radio_ccm_iso_tx_pkt_set(struct ccm * cnf,uint8_t pdu_type,void * pkt)1975 void *radio_ccm_iso_tx_pkt_set(struct ccm *cnf, uint8_t pdu_type, void *pkt)
1976 {
1977 return radio_ccm_ext_tx_pkt_set(cnf, pdu_type, pkt);
1978 }
1979 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_ADV_ISO */
1980
radio_ccm_is_done(void)1981 uint32_t radio_ccm_is_done(void)
1982 {
1983 nrf_ccm_int_enable(NRF_CCM, CCM_INTENSET_ENDCRYPT_Msk);
1984 while (NRF_CCM->EVENTS_ENDCRYPT == 0) {
1985 cpu_sleep();
1986 }
1987 nrf_ccm_int_disable(NRF_CCM, CCM_INTENCLR_ENDCRYPT_Msk);
1988 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_CCM));
1989
1990 return (NRF_CCM->EVENTS_ERROR == 0);
1991 }
1992
radio_ccm_mic_is_valid(void)1993 uint32_t radio_ccm_mic_is_valid(void)
1994 {
1995 return (NRF_CCM->MICSTATUS != 0);
1996 }
1997
1998 #if defined(CONFIG_BT_CTLR_PRIVACY)
1999 static uint8_t MALIGN(4) _aar_scratch[3];
2000
radio_ar_configure(uint32_t nirk,void * irk,uint8_t flags)2001 void radio_ar_configure(uint32_t nirk, void *irk, uint8_t flags)
2002 {
2003 uint32_t addrptr;
2004 uint8_t bcc;
2005 uint8_t phy;
2006
2007 /* Flags provide hint on how to setup AAR:
2008 * ....Xb - legacy PDU
2009 * ...X.b - extended PDU
2010 * XXX..b = RX PHY
2011 * 00000b = default case mapped to 00101b (legacy, 1M)
2012 *
2013 * If neither legacy not extended bit is set, legacy PDU is selected for
2014 * 1M PHY and extended PDU otherwise.
2015 */
2016
2017 phy = flags >> 2;
2018
2019 /* Check if extended PDU or non-1M and not legacy PDU */
2020 if (IS_ENABLED(CONFIG_BT_CTLR_ADV_EXT) &&
2021 ((flags & BIT(1)) || (!(flags & BIT(0)) && (phy > PHY_1M)))) {
2022 addrptr = NRF_RADIO->PACKETPTR + 1;
2023 bcc = 80;
2024 } else {
2025 addrptr = NRF_RADIO->PACKETPTR - 1;
2026 bcc = 64;
2027 }
2028
2029 /* For Coded PHY adjust for CI and TERM1 */
2030 if (IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && (phy == PHY_CODED)) {
2031 bcc += 5;
2032 }
2033
2034 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Enabled << AAR_ENABLE_ENABLE_Pos) &
2035 AAR_ENABLE_ENABLE_Msk;
2036 NRF_AAR->NIRK = nirk;
2037 NRF_AAR->IRKPTR = (uint32_t)irk;
2038 NRF_AAR->ADDRPTR = addrptr;
2039 NRF_AAR->SCRATCHPTR = (uint32_t)&_aar_scratch[0];
2040
2041 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_END);
2042 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_RESOLVED);
2043 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_NOTRESOLVED);
2044
2045 radio_bc_configure(bcc);
2046 radio_bc_status_reset();
2047
2048 hal_trigger_aar_ppi_config();
2049 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_AAR_PPI));
2050 }
2051
radio_ar_match_get(void)2052 uint32_t radio_ar_match_get(void)
2053 {
2054 return NRF_AAR->STATUS;
2055 }
2056
radio_ar_status_reset(void)2057 void radio_ar_status_reset(void)
2058 {
2059 radio_bc_status_reset();
2060
2061 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos) &
2062 AAR_ENABLE_ENABLE_Msk;
2063
2064 hal_radio_nrf_ppi_channels_disable(BIT(HAL_TRIGGER_AAR_PPI));
2065 }
2066
radio_ar_has_match(void)2067 uint32_t radio_ar_has_match(void)
2068 {
2069 if (!radio_bc_has_match()) {
2070 return 0U;
2071 }
2072
2073 nrf_aar_int_enable(NRF_AAR, AAR_INTENSET_END_Msk);
2074
2075 while (NRF_AAR->EVENTS_END == 0U) {
2076 cpu_sleep();
2077 }
2078
2079 nrf_aar_int_disable(NRF_AAR, AAR_INTENCLR_END_Msk);
2080
2081 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
2082
2083 if (NRF_AAR->EVENTS_RESOLVED && !NRF_AAR->EVENTS_NOTRESOLVED) {
2084 return 1U;
2085 }
2086
2087 return 0U;
2088 }
2089
radio_ar_resolve(const uint8_t * addr)2090 uint8_t radio_ar_resolve(const uint8_t *addr)
2091 {
2092 uint8_t retval;
2093
2094 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Enabled << AAR_ENABLE_ENABLE_Pos) &
2095 AAR_ENABLE_ENABLE_Msk;
2096
2097 NRF_AAR->ADDRPTR = (uint32_t)addr - 3;
2098
2099 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_END);
2100 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_RESOLVED);
2101 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_NOTRESOLVED);
2102
2103 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
2104
2105 nrf_aar_int_enable(NRF_AAR, AAR_INTENSET_END_Msk);
2106
2107 nrf_aar_task_trigger(NRF_AAR, NRF_AAR_TASK_START);
2108
2109 while (NRF_AAR->EVENTS_END == 0) {
2110 cpu_sleep();
2111 }
2112
2113 nrf_aar_int_disable(NRF_AAR, AAR_INTENCLR_END_Msk);
2114
2115 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
2116
2117 retval = (NRF_AAR->EVENTS_RESOLVED && !NRF_AAR->EVENTS_NOTRESOLVED) ?
2118 1U : 0U;
2119
2120 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos) &
2121 AAR_ENABLE_ENABLE_Msk;
2122
2123 return retval;
2124
2125 }
2126 #endif /* CONFIG_BT_CTLR_PRIVACY */
2127 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
2128
2129 #if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST)
2130 /* @brief Function configures CTE inline register to start sampling of CTE
2131 * according to information parsed from CTEInfo field of received PDU.
2132 *
2133 * @param[in] cte_info_in_s1 Informs where to expect CTEInfo field in PDU:
2134 * in S1 for data pdu, not in S1 for adv. PDU
2135 */
radio_df_cte_inline_set_enabled(bool cte_info_in_s1)2136 void radio_df_cte_inline_set_enabled(bool cte_info_in_s1)
2137 {
2138 const nrf_radio_cteinline_conf_t inline_conf = {
2139 .enable = true,
2140 /* Indicates whether CTEInfo is in S1 byte or not. */
2141 .info_in_s1 = cte_info_in_s1,
2142 /* Enable or disable switching and sampling when CRC is not OK. */
2143 #if defined(CONFIG_BT_CTLR_DF_SAMPLE_CTE_FOR_PDU_WITH_BAD_CRC)
2144 .err_handling = true,
2145 #else
2146 .err_handling = false,
2147 #endif /* CONFIG_BT_CTLR_DF_SAMPLE_CTE_FOR_PDU_WITH_BAD_CRC */
2148 /* Maximum range of CTE time. 20 * 8us according to BT spec.*/
2149 .time_range = NRF_RADIO_CTEINLINE_TIME_RANGE_20,
2150 /* Spacing between samples for 1us AoD or AoA is set to 2us. */
2151 .rx1us = NRF_RADIO_CTEINLINE_RX_MODE_2US,
2152 /* Spacing between samples for 2us AoD or AoA is set to 4us. */
2153 .rx2us = NRF_RADIO_CTEINLINE_RX_MODE_4US,
2154 /* S0 bit pattern to match all types of adv. PDUs or CP bit in conn PDU*/
2155 .s0_pattern = (cte_info_in_s1 ? DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU :
2156 DF_S0_ALLOW_ALL_PER_ADV_PDU),
2157 /* S0 bit mask set to don't match any bit in SO octet or match CP bit in conn PDU */
2158 .s0_mask = (cte_info_in_s1 ? DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU :
2159 DF_S0_ALLOW_ALL_PER_ADV_PDU)
2160 };
2161
2162 nrf_radio_cteinline_configure(NRF_RADIO, &inline_conf);
2163 }
2164 #endif /* CONFIG_BT_CTLR_DF_SUPPORT && !CONFIG_ZTEST */
2165
