1 /*
2  * Copyright 2021 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <common/debug.h>
11 #include <dcfg.h>
12 #include <lib/mmio.h>
13 #include <pmu.h>
14 
enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr)15 void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr)
16 {
17 	uint32_t *cltbenr = NULL;
18 	uint32_t cltbenr_val = 0U;
19 
20 	cltbenr = (uint32_t *)(nxp_pmu_addr
21 				+ CLUST_TIMER_BASE_ENBL_OFFSET);
22 
23 	cltbenr_val = mmio_read_32((uintptr_t)cltbenr);
24 
25 	cltbenr_val = cltbenr_val
26 			| (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
27 
28 	mmio_write_32((uintptr_t)cltbenr, cltbenr_val);
29 
30 	VERBOSE("Enable cluster time base\n");
31 }
32 
33 /*
34  * Enable core timebase.  In certain Layerscape SoCs, the clock for each core's
35  * has an enable bit in the PMU Physical Core Time Base Enable
36  * Register (PCTBENR), which allows the watchdog to operate.
37  */
38 
enable_core_tb(uintptr_t nxp_pmu_addr)39 void enable_core_tb(uintptr_t nxp_pmu_addr)
40 {
41 	uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr +
42 					  CORE_TIMEBASE_ENBL_OFFSET);
43 
44 	mmio_write_32((uintptr_t)pctbenr, 0xff);
45 }
46