1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2018 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 */ 8 9 /** 10 * \file include/ipc/dai-intel.h 11 * \brief IPC definitions 12 * \author Liam Girdwood <liam.r.girdwood@linux.intel.com> 13 * \author Keyon Jie <yang.jie@linux.intel.com> 14 */ 15 16 #ifndef __IPC_DAI_INTEL_H__ 17 #define __IPC_DAI_INTEL_H__ 18 19 #include <ipc/header.h> 20 #include <stdint.h> 21 22 /* ssc1: TINTE */ 23 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) 24 /* ssc1: PINTE */ 25 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) 26 /* ssc2: SMTATF */ 27 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) 28 /* ssc2: MMRATF */ 29 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) 30 /* ssc2: PSPSTWFDFD */ 31 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) 32 /* ssc2: PSPSRWFDFD */ 33 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) 34 /* ssc1: LBM */ 35 #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) 36 37 /* here is the possibility to define others aux macros */ 38 39 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 40 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 41 42 /* SSP clocks control settings 43 * 44 * Macros for clks_control field in sof_ipc_dai_ssp_params struct. 45 */ 46 47 /* mclk 0 disable */ 48 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) 49 /* mclk 1 disable */ 50 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) 51 /* mclk keep active */ 52 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) 53 /* bclk keep active */ 54 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) 55 /* fs keep active */ 56 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) 57 /* bclk idle */ 58 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 59 /* mclk early start */ 60 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) 61 /* bclk early start */ 62 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) 63 64 /* DMIC max. four controllers for eight microphone channels */ 65 #define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 66 67 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ 68 struct sof_ipc_dai_ssp_params { 69 uint32_t reserved0; 70 uint16_t reserved1; 71 uint16_t mclk_id; 72 73 uint32_t mclk_rate; /* mclk frequency in Hz */ 74 uint32_t fsync_rate; /* fsync frequency in Hz */ 75 uint32_t bclk_rate; /* bclk frequency in Hz */ 76 77 /* TDM */ 78 uint32_t tdm_slots; 79 uint32_t rx_slots; 80 uint32_t tx_slots; 81 82 /* data */ 83 uint32_t sample_valid_bits; 84 uint16_t tdm_slot_width; 85 uint16_t reserved2; /* alignment */ 86 87 /* MCLK */ 88 uint32_t mclk_direction; 89 90 uint16_t frame_pulse_width; 91 uint16_t tdm_per_slot_padding_flag; 92 uint32_t clks_control; 93 uint32_t quirks; 94 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 95 * will be driven, before sending data 96 */ 97 } __attribute__((packed, aligned(4))); 98 99 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ 100 struct sof_ipc_dai_hda_params { 101 uint32_t reserved0; 102 uint32_t link_dma_ch; 103 uint32_t rate; 104 uint32_t channels; 105 } __attribute__((packed, aligned(4))); 106 107 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 108 struct sof_ipc_dai_alh_params { 109 uint32_t reserved0; 110 uint32_t stream_id; 111 uint32_t rate; 112 uint32_t channels; 113 114 /* reserved for future use */ 115 uint32_t reserved[13]; 116 } __attribute__((packed, aligned(4))); 117 118 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ 119 120 /* This struct is defined per 2ch PDM controller available in the platform. 121 * Normally it is sufficient to set the used microphone specific enables to 1 122 * and keep other parameters as zero. The customizations are: 123 * 124 * 1. If a device mixes different microphones types with different polarity 125 * and/or the absolute polarity matters the PCM signal from a microphone 126 * can be inverted with the controls. 127 * 128 * 2. If the microphones in a stereo pair do not appear in captured stream 129 * in desired order due to board schematics choises they can be swapped with 130 * the clk_edge parameter. 131 * 132 * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter 133 * that delays the sampling time of data by half cycles of DMIC source clock 134 * can be tried for improvement. However there is no guarantee for this to fix 135 * data integrity problems. 136 */ 137 struct sof_ipc_dai_dmic_pdm_ctrl { 138 uint32_t reserved0; 139 uint16_t id; /**< PDM controller ID */ 140 141 uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ 142 uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ 143 144 uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ 145 uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ 146 147 uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ 148 uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ 149 150 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ 151 } __attribute__((packed, aligned(4))); 152 153 /* This struct contains the global settings for all 2ch PDM controllers. The 154 * version number used in configuration data is checked vs. version used by 155 * device driver src/drivers/dmic.c need to match. It is incremented from 156 * initial value 1 if updates done for the to driver would alter the operation 157 * of the microphone. 158 * 159 * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) 160 * parameters need to be set as defined in microphone data sheet. E.g. clock 161 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are 162 * multi-mode capable and there may be denied mic clock frequencies between 163 * the modes. In such case set the clock range limits of the desired mode to 164 * avoid the driver to set clock to an illegal rate. 165 * 166 * The duty cycle could be set to 48-52% if not known. Generally these 167 * parameters can be altered within data sheet specified limits to match 168 * required audio application performance power. 169 * 170 * The microphone clock needs to be usually about 50-80 times the used audio 171 * sample rate. With highest sample rates above 48 kHz this can relaxed 172 * somewhat. 173 * 174 * The parameter wake_up_time describes how long time the microphone needs 175 * for the data line to produce valid output from mic clock start. The driver 176 * will mute the captured audio for the given time. The min_clock_on_time 177 * parameter is used to prevent too short clock bursts to happen. The driver 178 * will keep the clock active after capture stop if this time is not yet 179 * met. The unit for both is microseconds (us). Exceed of 100 ms will be 180 * treated as an error. 181 */ 182 183 struct sof_ipc_dai_dmic_params { 184 uint32_t reserved0; 185 uint32_t driver_ipc_version; /**< Version (1..N) */ 186 187 uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ 188 uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ 189 190 uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ 191 uint32_t reserved_1; /**< Reserved */ 192 uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ 193 uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ 194 195 uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ 196 uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ 197 198 uint32_t num_pdm_active; /**< Number of active pdm controllers. */ 199 /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ 200 201 uint32_t wake_up_time; /**< Time from clock start to data (us) */ 202 uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ 203 uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ 204 205 /* reserved for future use */ 206 uint32_t reserved[5]; 207 208 /**< PDM controllers configuration */ 209 struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; 210 } __attribute__((packed, aligned(4))); 211 212 #endif /* __IPC_DAI_INTEL_H__ */ 213
