1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright (c) 2016, NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_SPM_H_
11 #define _FSL_SPM_H_
12
13 #include "fsl_common.h"
14
15 /*! @addtogroup spm */
16 /*! @{ */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief SPM driver version */
25 #define FSL_SPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
26 /*@}*/
27
28 /*!
29 * @brief IP version ID definition.
30 */
31 typedef struct _spm_version_id
32 {
33 uint16_t feature; /*!< Feature Specification Number. */
34 uint8_t minor; /*!< Minor version number. */
35 uint8_t major; /*!< Major version number. */
36 } spm_version_id_t;
37
38 /*!
39 * @brief Status of last RADIO Power Mode Configuration.
40 */
41 typedef enum _spm_radio_low_power_mode_status
42 {
43 kSPM_RadioLowPowerModeReserved = 0x0, /*!< Reserved. */
44 kSPM_RadioLowPowerModeVLPS = 0x1, /*!< Current Power mode is VLPS. */
45 kSPM_RadioLowPowerModeLLS = 0x2, /*!< Current Power mode is LLS. */
46 kSPM_RadioLowPowerModeVLLS = 0x4, /*!< Current Power mode is VLLS. */
47 } spm_radio_low_power_mode_status_t;
48
49 /*!
50 * @brief Status of last MCU STOP Mode Power Configuration.
51 */
52 typedef enum _spm_mcu_low_power_mode_status
53 {
54 kSPM_McuLowPowerModeReserved = 0U, /*!< Reserved. */
55 kSPM_McuLowPowerModeSTOP = 1U, /*!< Last Low Power mode is STOP. */
56 kSPM_McuLowPowerModeVLPS = (1U << 1), /*!< Last Low Power mode is VLPS. */
57 kSPM_McuLowPowerModeLLS = (1U << 2), /*!< Last Low Power mode is LLS. */
58 kSPM_McuLowPowerModeVLLS23 = (1U << 3), /*!< Last Low Power mode is VLLS23. */
59 kSPM_McuLowPowerModeVLLS01 = (1U << 4), /*!< Last Low Power mode is VLLS01. */
60 } spm_mcu_low_power_mode_status_t;
61
62 /*!
63 * @brief define the mask code for LDO regulators.
64 *
65 * These mask can be combined with 'or' as a parameter to any function.
66 */
67 enum _spm_ldo_regulator
68 {
69 kSPM_CoreLdo = 1U, /*!< Mask code for CORE LDO. */
70 kSPM_RfLdo = (1U << 1), /*!< Mask code for RF LDO. */
71 kSPM_DcdcLdo = (1U << 2), /*!< Mask code for DCDC LDO. */
72 };
73
74 /*!
75 * @brief Keep the regulator status information.
76 */
77 typedef struct _spm_regulator_status
78 {
79 bool isRadioRunForcePowerModeOn; /*!< RADIO Run Force Power Mode Status. */
80 spm_radio_low_power_mode_status_t radioLowPowerModeStatus; /*!< Status of last RADIO Power Mode Configuration. */
81 spm_mcu_low_power_mode_status_t mcuLowPowerModeStatus; /*!< Status of last MCU STOP Mode Power Configuration. */
82 bool isDcdcLdoOn; /*!< DCDC LDO regulator enabled. */
83 bool isRfLdoOn; /*!< RF LDO regulator enabled. */
84 bool isCoreLdoOn; /*!< Core LDO regulator enabled. */
85 } spm_regulator_status_t;
86
87 /*!
88 * @brief Configure the CORE LDO in run modes.
89 */
90 enum _spm_core_ldo_run_mode_config
91 {
92 kSPM_CoreLdoRunModeEnableRtcPowerMonitor =
93 SPM_CORERCNFG_RTCVDDMEN_MASK, /*!< RTC power monitor enabled in run modes. */
94 kSPM_CoreLdoRunModeEnableUsbPowerMonitor =
95 SPM_CORERCNFG_USBVDDMEN_MASK, /*!< USB power monitor enabled in run modes. */
96 kSPM_CoreLdoRunModeEnableVddioPowerMonitor =
97 SPM_CORERCNFG_VDDIOVDDMEN_MASK, /*!< VDDIO power monitor enabled in run modes. */
98 };
99
100 /*!
101 * @brief Configure the CORE LDO in low power modes.
102 */
103 enum _spm_core_ldo_low_power_mode_config
104 {
105 kSPM_CoreLdoLowPowerModeEnableRtcPowerMonitor =
106 SPM_CORELPCNFG_RTCVDDMEN_MASK, /*!< RTC power monitor enabled in LP modes. */
107 kSPM_CoreLdoLowPowerModeEnableUsbPowerMonitor =
108 SPM_CORELPCNFG_USBVDDMEN_MASK, /*!< USB power monitor enabled in LP modes. */
109 kSPM_CoreLdoLowPowerModeEnableVddioPowerMonitor =
110 SPM_CORELPCNFG_VDDIOVDDMEN_MASK, /*!< VDDIO power monitor enabled in LP modes. */
111 kSPM_CoreLdoLowPowerModeEnableAllReference =
112 SPM_CORELPCNFG_ALLREFEN_MASK, /*!< Enable all reference (bandgap, WELL
113 BIAS, 1k clk and LP 25na) in VLLS. */
114 kSPM_CoreLdoLowPowerModeEnableHighDrive = SPM_CORELPCNFG_LPHIDRIVE_MASK, /*!< Enable high driver in low power. */
115 kSPM_CoreLdoLowPowerModeEnableLVD =
116 SPM_CORELPCNFG_LVDEN_MASK, /*!< Enable level voltage detect in VLP/STOP modes. */
117 kSPM_CoreLdoLowPowerModeEnablePOR = SPM_CORELPCNFG_POREN_MASK, /*!< POR brownout remains enabled in VLLS mode. */
118 kSPM_CoreLdoLowPowerModeEnableLPO = SPM_CORELPCNFG_LPOEN_MASK, /*!< LPO remains enabled in VLLS modes. */
119 kSPM_CoreLdoLowPowerModeEnableBandgapBufferHightDrive =
120 SPM_CORELPCNFG_BGBDS_MASK, /*!< Enable the high drive for Bandgap Buffer. */
121 kSPM_CoreLdoLowPowerModeEnableBandgapBuffer = SPM_CORELPCNFG_BGBEN_MASK, /*!< Enable Bandgap Buffer. */
122 kSPM_CoreLdoLowPowerModeEnableBandgapInVLPx = SPM_CORELPCNFG_BGEN_MASK, /*!< Enable Bandgap in VLPx mode. */
123 kSPM_CoreLdoLowPowerModeRemainInHighPower =
124 SPM_CORELPCNFG_LPSEL_MASK, /*!< Core LDO remains in high power state in VLP/Stop modes. */
125 };
126
127 /*!
128 * @brief Sets the Core LDO voltage level.
129 */
130 typedef enum _spm_core_ldo_voltage_select
131 {
132 kSPM_CoreLdoVoltLevel1P2 = 0U, /*!< Regulate to 1.2V set by the CORETRIM[VTRIM1P2] register. */
133 kSPM_CoreLdoVoltLevel1P1 = 1U, /*!< Regulate to 1.1V set by the CORETRIM[VTRIM1P1] register. */
134 kSPM_CoreLdoVoltLevelOffset = 3U, /*!< Regulate to Offset Voltage set by CORETRIM[OFFVTRIM] register. */
135 } spm_core_ldo_volt_select_t;
136
137 /*!
138 * @brief Low-voltage Detect Voltage Select
139 */
140 typedef enum _spm_low_volt_detect_volt_select
141 {
142 kSPM_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/
143 kSPM_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/
144 } spm_low_volt_detect_volt_select_t;
145
146 /*!
147 * @brief Low-voltage Detect Configuration Structure.
148 *
149 * This structure reuses the configuration structure from legacy PMC module.
150 */
151 typedef struct _spm_low_volt_detect_config
152 {
153 /* VDD voltage detection. */
154 bool enableIntOnVddLowVolt; /*!< Enable interrupt when VDD Low-voltage detect. */
155 bool enableResetOnVddLowVolt; /*!< Enable forcing a system reset when VDD Low-voltage detect. */
156 spm_low_volt_detect_volt_select_t vddLowVoltDetectSelect; /*!< Low-voltage detect trip point voltage selection. */
157
158 /* CORE voltage detection. */
159 bool enableIntOnCoreLowVolt; /*!< Enable interrupt when Core Low-voltage detect. */
160 bool enableResetOnCoreLowVolt; /*!< Enable forcing a system reset when Core Low-voltage detect. */
161 } spm_low_volt_detect_config_t;
162
163 /*!
164 * @brief Low-voltage Warning Voltage Select.
165 */
166 typedef enum _spm_low_volt_warning_volt_select
167 {
168 kSPM_LowVoltWarningLowTrip = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/
169 kSPM_LowVoltWarningMID1Trip = 1U, /*!< Mid1-trip point selected (VLVW = VLVW2)*/
170 kSPM_LowVoltWarningMID2Trip = 2U, /*!< Mid2-trip point selected (VLVW = VLVW3)*/
171 kSPM_LowVoltWarningHighTrip = 3U /*!< High-trip point selected (VLVW = VLVW4)*/
172 } spm_low_volt_warning_volt_select_t;
173
174 /*!
175 * @brief Low-voltage Warning Configuration Structure
176 */
177 typedef struct _spm_low_volt_warning_config
178 {
179 bool enableIntOnVddLowVolt; /*!< Enable interrupt when low-voltage warning*/
180 spm_low_volt_warning_volt_select_t vddLowVoltDetectSelect; /*!< Low-voltage warning trip point voltage selection*/
181 } spm_low_volt_warning_config_t;
182
183 /*!
184 * @brief High-voltage Detect Voltage Select.
185 */
186 typedef enum _spm_high_volt_detect_volt_select
187 {
188 kSPM_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/
189 kSPM_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/
190 } spm_high_volt_detect_volt_select_t;
191
192 /*!
193 * @brief High-voltage Detect Configuration Structure.
194 *
195 * This structure reuses the configuration structure from legacy PMC module.
196 */
197 typedef struct _spm_high_volt_detect_config
198 {
199 bool enableIntOnVddHighVolt; /*!< Enable interrupt when high-voltage detect*/
200 bool enableResetOnVddHighVolt; /*!< Enable system reset when high-voltage detect*/
201 spm_high_volt_detect_volt_select_t vddHighVoltDetectSelect; /*!< High-voltage detect trip point voltage selection*/
202 } spm_high_volt_detect_config_t;
203
204 /*!
205 * @brief Defines the RF LDO low power behiavior when in low power modes.
206 */
207 typedef enum _spm_rf_ldo_low_power_mode
208 {
209 kSPM_RfLdoEnterLowPowerInLowPowerModes = 0U, /*!< RF LDO regulator enters low power state in VLP/Stop modes. */
210 kSPM_RfLdoRemainInHighPowerInLowPowerModes =
211 1U, /*!< RF LDO regulator remains in high power state in VLP/Stop modes. */
212 } spm_rf_ldo_low_power_mode_t;
213
214 /*!
215 * @brief Selects the soft start duration delay for the IO 1.8 full power regulator.
216 */
217 typedef enum _spm_rf_ldo_soft_start_duration
218 {
219 kSPM_RfLdoSoftStartDuration110us = 0U, /*!< 110 us. */
220 kSPM_RfLdoSoftStartDuration95us = 1U, /*!< 95 us. */
221 kSPM_RfLdoSoftStartDuration60us = 2U, /*!< 60 us. */
222 kSPM_RfLdoSoftStartDuration48us = 3U, /*!< 48 us. */
223 kSPM_RfLdoSoftStartDuration38us = 4U, /*!< 38 us. */
224 kSPM_RfLdoSoftStartDuration30us = 5U, /*!< 30 us. */
225 kSPM_RfLdoSoftStartDuration24us = 6U, /*!< 24 us. */
226 kSPM_RfLdoSoftStartDuration17us = 7U, /*!< 17 us. */
227 } spm_rf_ldo_soft_start_duration_t;
228
229 /*!
230 * @brief IO Regulator Voltage Select.
231 */
232 typedef enum _spm_rf_io_regulator_volt_select
233 {
234 kSPM_RfIoRegulatorVoltLevel1p8 = 0U, /*!< Regulate to 1.8V. */
235 kSPM_RfIoRegulatorVoltLevel1p5 = 1U, /*!< Regulate to 1.5V. */
236 } spm_rf_io_regulator_volt_select_t;
237
238 /*!
239 * @brief RF LDO configuration structure.
240 */
241 typedef struct _spm_rf_ldo_config
242 {
243 spm_rf_ldo_low_power_mode_t lowPowerMode; /*!< RF LDO low power behaviour when in low power modes. */
244 spm_rf_ldo_soft_start_duration_t
245 softStartDuration; /*!< Selects the soft start duration delay for the IO 1.8 full power regulator. */
246 bool enableCurSink; /*!< Enables current sink feature of low power regulator.*/
247 spm_rf_io_regulator_volt_select_t rfIoRegulatorVolt; /*!< IO Regulator Voltage Select. */
248 } spm_rf_ldo_config_t;
249
250 /*!
251 * @brief Selects which sns 1p8 vdd pin is used.
252 */
253 typedef enum _spm_rf_vdd_1p8_sns_pin_select
254 {
255 kSPM_RfVdd1p8Sns0 = 0U, /*!< VDD1p8_SNS0 selected. */
256 kSPM_RfVdd1p8Sns1 = 1U, /*!< VDD1p8_SNS1 selected. */
257 } spm_rf_vdd_1p8_sns_pin_select_t;
258
259 /*!
260 * @brief Selects the trim point for RF LDO.
261 */
262 typedef enum _spm_rf_ldo_volt_trim_select
263 {
264 kSPM_RfLdoLowPowerVolt1p8Trim, /*!< RF LDO Low Power 1.8V trim point value. */
265 kSPM_RfLdoLowPowerVlot1p5Trim, /*!< RF LDO Low Power 1.5V trim point value. */
266 kSPM_RfLdoHighPowerVolt1p8Trim, /*!< RF LDO High Power 1.8V trim point value. */
267 kSPM_RfLdoHighPowerVolt1p5Trim, /*!< RF LDO High Power 1.5V trim point value/ */
268 kSPM_RfLdoRegulatorOffsetTrim,
269 } spm_rf_ldo_volt_trim_select_t;
270
271 /*!
272 * @brief Configuration for setting DCDC integrator value.
273 */
274 typedef struct _spm_dcdc_integrator_value_config
275 {
276 double vdd1p2Value; /*!< VDD1P2 output voltage value. */
277 double vBatValue; /*!< Battery input voltage value, or the Vdd_dcdcin voltage value. */
278 } spm_dcdc_integrator_config_t;
279
280 /*!
281 * @brief Defines the selection of DCDC vbat voltage divider for ADC measure.
282 */
283 typedef enum _spm_dcdc_vbat_adc_divider
284 {
285 kSPM_DcdcVbatAdcOff = 0U, /*!< OFF. */
286 kSPM_DcdcVbatAdcDivider1 = 1U, /*!< VBAT. */
287 kSPM_DcdcVbatAdcDivider2 = 2U, /*!< VBAT /2. */
288 kSPM_DcdcVbatAdcDivider4 = 3U, /*!< VBAT /4. */
289 } spm_dcdc_vbat_adc_divider_t;
290
291 /*!
292 * @brief Configuration of power switch delay.
293 */
294 typedef struct _spm_power_switch_delay_config
295 {
296 uint32_t coreRegFromDeepPowerDownToIso; /*!< Deep Power Down Wakeup Switch to ISO Delay. <= 0xFF */
297 uint32_t coreRegFromLowPowerToIso; /*!< Low Power Wakeup Switch to ISO Delay. */
298 uint32_t lowPowerToBandgapOn; /*!< Low Power Wake Up Delay. */
299 uint32_t dcdcStartupDelay; /*!< Configures the number of cycles for DCDC startup before the Core
300 LDO or RF LDO can be disabled. */
301 uint32_t ldoCoreSwitchHsrunDelay; /*!< Configures the number of cycles delay for LDO CORE
302 Regulator in and out of HSRUN mode. */
303 } spm_power_switch_delay_config_t;
304
305 /*!
306 * @brief Defines the selection of low power request pin out pin polarity.
307 */
308 typedef enum _spm_low_power_req_out_pin_pol
309 {
310 kSPM_LowPowerReqOutPinHighTruePol = 0U, /*!< High true polarity. */
311 kSPM_LowPowerReqOutPinLowTruePol = 1U, /*!< Low true polarity. */
312 } spm_low_power_req_out_pin_pol_t;
313
314 /*!
315 * @brief Configuration structure of low power request out pin.
316 */
317 typedef struct _spm_low_power_req_out_pin_config
318 {
319 spm_low_power_req_out_pin_pol_t pinOutPol; /*!< ow power request pin out pin polarity. */
320 bool pinOutEnable; /*!< Low Power request output pin is enabled or not. */
321 } spm_low_power_req_out_pin_config_t;
322
323 /*!
324 * @brief Defines the selection of DCDC driver strength.
325 *
326 * The more FETs are enabled, the more drive strength DCDC would provide.
327 */
328 typedef enum _spm_dcdc_drive_strength
329 {
330 kSPM_DcdcDriveStrengthWithNormal = 0U, /*!< No additional FET setting. */
331 kSPM_DcdcDriveStrengthWithHalfFETs = 0x4, /*!< Half FETs. */
332 kSPM_DcdcDriveStrengthWithDoubleFETs = 0x2, /*!< Double FETs. */
333 kSPM_DcdcDriveStrengthWithExtraHalfFETs = 0x1, /*!< Half FETs. */
334 kSPM_DcdcDriveStrengthWithHalfAndDoubleFETs = 0x6, /*!< Half + Double FETs. */
335 kSPM_DcdcDriveStrengthWithHalfAndExtraDoubleFETs = 0x5, /*!< Half + Extra Double FETs. */
336 kSPM_DcdcDriveStrengthWithDoubleAndExtraDoubleFETs = 0x3, /*!< Double + Extra Double FETs. */
337 kSPM_DcdcDriveStrengthWithAllFETs = 7U, /*!< Half + Double + Extra Double FETs. */
338 } spm_dcdc_drive_strength_t;
339
340 /*!
341 * @brief DCDC flags.
342 */
343 enum _spm_dcdc_flags
344 {
345 kSPM_DcdcStableOKFlag = SPM_DCDCSC_DCDC_STS_DC_OK_MASK, /*!< Status flag to indicate DCDC lock. */
346 kSPM_DcdcClockFaultFlag =
347 SPM_DCDCSC_CLKFLT_FAULT_MASK, /*!< Asserts if DCDC detect a clk fault. Will cause a system lvd reset to assert.
348 */
349 };
350
351 /*******************************************************************************
352 * API
353 ******************************************************************************/
354
355 #if defined(__cplusplus)
356 extern "C" {
357 #endif /* __cplusplus*/
358
359 /*! @name System Power Manager. */
360 /*@{*/
361
362 /*!
363 * @brief Gets the SPM version ID.
364 *
365 * This function gets the SPM version ID, including major version number,
366 * minor version number, and a feature specification number.
367 *
368 * @param base SPM peripheral base address.
369 * @param versionId Pointer to version ID structure.
370 */
SPM_GetVersionId(SPM_Type * base,spm_version_id_t * versionId)371 static inline void SPM_GetVersionId(SPM_Type *base, spm_version_id_t *versionId)
372 {
373 *((uint32_t *)versionId) = base->VERID;
374 }
375
376 /*!
377 * @brief Gets the regulators Status.
378 *
379 * @param base SPM peripheral base address.
380 * @param info Pointer to status structure, see to #spm_regulator_status_t.
381 */
382 void SPM_GetRegulatorStatus(SPM_Type *base, spm_regulator_status_t *info);
383
384 /*!
385 * @brief Controls which regulators are enabled in RUN and HSRUN modes.
386 *
387 * This function controls which regulator (CORE LDO, RF LDO, and DCDC) are enabled in RUN and HSRUN
388 * modes. It sets the SPM_RCTRL register.
389 * Note that the RCTRL bits are reset solely on a POR/LVD only event.
390 *
391 * @param base SPM peripheral base address.
392 * @param enable Enable or disable the LDOs list in ldoMask.
393 * @param ldoMask Mask value of LDO list. See to #_spm_ldo_regulator.
394 */
SPM_EnableRegulatorInRunMdoe(SPM_Type * base,bool enable,uint32_t ldoMask)395 static inline void SPM_EnableRegulatorInRunMdoe(SPM_Type *base, bool enable, uint32_t ldoMask)
396 {
397 if (enable)
398 {
399 base->RCTRL |= SPM_RCTRL_REGSEL(ldoMask);
400 }
401 else
402 {
403 base->RCTRL &= ~SPM_RCTRL_REGSEL(ldoMask);
404 }
405 }
406
407 /*!
408 * @brief Controls which regulators are enabled in low power modes.
409 *
410 * This function controls which regulator (CORE LDO, RF LDO, and DCDC) are enabled in low power
411 * modes. It sets the SPM_LPCTRL register.
412 * Note that the SPM_LPCTRL bits are reset solely on a POR/LVD only event.
413 *
414 * @param base SPM peripheral base address.
415 * @param enable Enable or disable the LDOs list in ldoMask.
416 * @param ldoMask Mask value of LDO list.
417 */
SPM_EnableRegulatorInLowPowerMode(SPM_Type * base,bool enable,uint32_t ldoMask)418 static inline void SPM_EnableRegulatorInLowPowerMode(SPM_Type *base, bool enable, uint32_t ldoMask)
419 {
420 if (enable)
421 {
422 base->LPCTRL |= SPM_LPCTRL_REGSEL(ldoMask);
423 }
424 else
425 {
426 base->LPCTRL &= ~SPM_LPCTRL_REGSEL(ldoMask);
427 }
428 }
429
430 /*!
431 * @brief Configures the CORE LDO working in run modes.
432 *
433 * @param base SPM peripheral base address.
434 * @param conifgMask Mask value of configuration items. See to #_spm_core_ldo_run_mode_config.
435 */
SPM_SetCoreLdoRunModeConfig(SPM_Type * base,uint32_t configMask)436 static inline void SPM_SetCoreLdoRunModeConfig(SPM_Type *base, uint32_t configMask)
437 {
438 base->CORERCNFG = configMask;
439 }
440
441 /*!
442 * @brief Configures the CORE LDO working in low power modes.
443 *
444 * @param base SPM peripheral base address.
445 * @param conifgMask Mask value of configuration items. See to #_spm_core_ldo_low_power_mode_config.
446 */
SPM_SetCoreLdoLowPowerModeConfig(SPM_Type * base,uint32_t configMask)447 static inline void SPM_SetCoreLdoLowPowerModeConfig(SPM_Type *base, uint32_t configMask)
448 {
449 base->CORELPCNFG = configMask;
450 }
451
452 /*!
453 * @brief Check if the CORE LDO is in run regulation.
454 *
455 * @param base SPM peripheral base address.
456 * @retval true Regulator is in run regulation.
457 * @retval false Regulator is in stop regulation or in transition to/from it.
458 */
SPM_GetCoreLdoInRunRegulationFlag(SPM_Type * base)459 static inline bool SPM_GetCoreLdoInRunRegulationFlag(SPM_Type *base)
460 {
461 return (SPM_CORESC_REGONS_MASK == (SPM_CORESC_REGONS_MASK & base->CORESC));
462 }
463
464 /*!
465 * @brief Gets the acknowledge Peripherals and I/O pads isolation flag.
466 *
467 * This function reads the Acknowledge Isolation setting that indicates
468 * whether certain peripherals and the I/O pads are in a latched state as
469 * a result of having been in the VLLS mode.
470 *
471 * @param base SPM peripheral base address.
472 * @return ACK isolation
473 * 0 - Peripherals and I/O pads are in a normal run state.
474 * 1 - Certain peripherals and I/O pads are in an isolated and
475 * latched state.
476 */
SPM_GetPeriphIOIsolationFlag(SPM_Type * base)477 static inline bool SPM_GetPeriphIOIsolationFlag(SPM_Type *base)
478 {
479 return (SPM_CORESC_ACKISO_MASK == (base->CORESC & SPM_CORESC_ACKISO_MASK));
480 }
481
482 /*!
483 * @brief Acknowledges the isolation flag to Peripherals and I/O pads.
484 *
485 * This function clears the ACK Isolation flag. Writing one to this setting
486 * when it is set releases the I/O pads and certain peripherals to their normal
487 * run mode state.
488 *
489 * @param base SPM peripheral base address.
490 */
SPM_ClearPeriphIOIsolationFlag(SPM_Type * base)491 static inline void SPM_ClearPeriphIOIsolationFlag(SPM_Type *base)
492 {
493 base->CORESC |= SPM_CORESC_ACKISO_MASK;
494 }
495
496 /*@}*/
497
498 /*! @name VDD Low voltage detection APIs*/
499 /*@{*/
500
501 /*!
502 * @brief Configures the low-voltage detect setting.
503 *
504 * This function configures the low-voltage detect setting, including the trip
505 * point voltage setting, enables or disables the interrupt, enables or disables the system reset.
506 *
507 * @param base SPM peripheral base address.
508 * @param config Pointer to low-voltage detect configuration structure, see to #spm_low_volt_detect_config_t.
509 */
510 void SPM_SetLowVoltDetectConfig(SPM_Type *base, const spm_low_volt_detect_config_t *config);
511
512 /*!
513 * @brief Gets VDD Low-voltage Detect Flag status.
514 *
515 * @param base SPM peripheral base address.
516 * @return Current low-voltage detect flag
517 * - true: Low-voltage detected
518 * - false: Low-voltage not detected
519 */
SPM_GetVddLowVoltDetectFlag(SPM_Type * base)520 static inline bool SPM_GetVddLowVoltDetectFlag(SPM_Type *base)
521 {
522 return (SPM_LVDSC1_VDD_LVDF_MASK == (base->LVDSC1 & SPM_LVDSC1_VDD_LVDF_MASK));
523 }
524
525 /*!
526 * @brief Acknowledges clearing the Low-voltage Detect flag.
527 *
528 * This function acknowledges the low-voltage detection errors.
529 *
530 * @param base SPM peripheral base address.
531 */
SPM_ClearVddLowVoltDetectFlag(SPM_Type * base)532 static inline void SPM_ClearVddLowVoltDetectFlag(SPM_Type *base)
533 {
534 base->LVDSC1 |= SPM_LVDSC1_VDD_LVDACK_MASK; /* W1C. */
535 }
536
537 /*@}*/
538
539 /*! @name CORE LDO Low voltage detection APIs */
540 /*@{*/
541
542 /*!
543 * @brief Gets the COREVdds Low-voltage Detect Flag status.
544 *
545 * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected.
546 *
547 * @param base SPM peripheral base address.
548 * @return Current low-voltage detect flag
549 * - true: Low-voltage detected
550 * - false: Low-voltage not detected
551 */
SPM_GetCoreLowVoltDetectFlag(SPM_Type * base)552 static inline bool SPM_GetCoreLowVoltDetectFlag(SPM_Type *base)
553 {
554 return (SPM_LVDSC1_COREVDD_LVDF_MASK == (base->LVDSC1 & SPM_LVDSC1_COREVDD_LVDF_MASK));
555 }
556
557 /*!
558 * @brief Acknowledges clearing the CORE VDD Low-voltage Detect flag.
559 *
560 * This function acknowledges the CORE VDD low-voltage detection errors.
561 *
562 * @param base SPM peripheral base address.
563 */
SPM_ClearCoreLowVoltDetectFlag(SPM_Type * base)564 static inline void SPM_ClearCoreLowVoltDetectFlag(SPM_Type *base)
565 {
566 base->LVDSC1 |= SPM_LVDSC1_COREVDD_LVDACK_MASK; /* W1C. */
567 }
568
569 /*!
570 * @brief Configures the low-voltage warning setting.
571 *
572 * This function configures the low-voltage warning setting, including the trip
573 * point voltage setting and enabling or disabling the interrupt.
574 *
575 * @param base SPM peripheral base address.
576 * @param config Pointer to Low-voltage warning configuration structure, see to #spm_low_volt_warning_config_t.
577 */
578 void SPM_SetLowVoltWarningConfig(SPM_Type *base, const spm_low_volt_warning_config_t *config);
579
580 /*!
581 * @brief Gets Vdd Low-voltage Warning Flag status.
582 *
583 * This function polls the current LVWF status. When 1 is returned, it
584 * indicates a low-voltage warning event. LVWF is set when V Supply transitions
585 * below the trip point or after reset and V Supply is already below the V LVW.
586 *
587 * @param base SPM peripheral base address.
588 * @return Current LVWF status
589 * - true: Low-voltage Warning Flag is set.
590 * - false: the Low-voltage Warning does not happen.
591 */
SPM_GetVddLowVoltWarningFlag(SPM_Type * base)592 static inline bool SPM_GetVddLowVoltWarningFlag(SPM_Type *base)
593 {
594 return (SPM_LVDSC2_VDD_LVWF_MASK == (base->LVDSC2 & SPM_LVDSC2_VDD_LVWF_MASK));
595 }
596
597 /*!
598 * @brief Acknowledges the Low-voltage Warning flag.
599 *
600 * This function acknowledges the low voltage warning errors (write 1 to
601 * clear LVWF).
602 *
603 * @param base SPM peripheral base address.
604 */
SPM_ClearLowVoltWarningFlag(SPM_Type * base)605 static inline void SPM_ClearLowVoltWarningFlag(SPM_Type *base)
606 {
607 base->LVDSC2 |= SPM_LVDSC2_VDD_LVWACK_MASK; /* W1C. */
608 }
609
610 /*@}*/
611
612 /*! @name VDD high voltage detection APIs. */
613 /*@{*/
614
615 /*!
616 * @brief Configures the high-voltage detect setting.
617 *
618 * This function configures the high-voltage detect setting, including the trip
619 * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset.
620 *
621 * @param base SPM peripheral base address.
622 * @param config High-voltage detect configuration structure, see to #spm_high_volt_detect_config_t.
623 */
624 void SPM_SetHighVoltDetectConfig(SPM_Type *base, const spm_high_volt_detect_config_t *config);
625
626 /*!
627 * @brief Gets the High-voltage Detect Flag status.
628 *
629 * This function reads the current HVDF status. If it returns 1, a low
630 * voltage event is detected.
631 *
632 * @param base SPM peripheral base address.
633 * @return Current high-voltage detect flag
634 * - true: High-voltage detected
635 * - false: High-voltage not detected
636 */
SPM_GetHighVoltDetectFlag(SPM_Type * base)637 static inline bool SPM_GetHighVoltDetectFlag(SPM_Type *base)
638 {
639 return (SPM_HVDSC1_VDD_HVDF_MASK == (base->HVDSC1 & SPM_HVDSC1_VDD_HVDF_MASK));
640 }
641
642 /*!
643 * @brief Acknowledges clearing the High-voltage Detect flag.
644 *
645 * This function acknowledges the high-voltage detection errors (write 1 to
646 * clear HVDF).
647 *
648 * @param base SPM peripheral base address.
649 */
SPM_ClearHighVoltDetectFlag(SPM_Type * base)650 static inline void SPM_ClearHighVoltDetectFlag(SPM_Type *base)
651 {
652 base->HVDSC1 |= SPM_HVDSC1_VDD_HVDACK_MASK; /* W1C. */
653 }
654
655 /*@}*/
656
657 /*! @name RF LDO Low voltage detection APIs */
658 /*@{*/
659
660 /*!
661 * @brief Configures the RF LDO.
662 *
663 * @param base SPM peripheral base address.
664 * @param config Pointer to configuration structure, see to #spm_rf_ldo_config_t.
665 */
666 void SPM_SetRfLdoConfig(SPM_Type *base, const spm_rf_ldo_config_t *config);
667
668 /*!
669 * @brief Selects which SNS 1p8 vdd pin is used.
670 *
671 * @param base SPM peripheral base address.
672 * @param pin Selection of SNS 1p8 Vdd pin to be used, see to #spm_rf_vdd_1p8_sns_pin_select_t.
673 */
SPM_SelectVdd1p8SnsPin(SPM_Type * base,spm_rf_vdd_1p8_sns_pin_select_t pin)674 static inline void SPM_SelectVdd1p8SnsPin(SPM_Type *base, spm_rf_vdd_1p8_sns_pin_select_t pin)
675 {
676 base->RFLDOSC = (base->RFLDOSC & ~SPM_RFLDOSC_VDD1P8SEL_MASK) | SPM_RFLDOSC_VDD1P8SEL(pin);
677 }
678
679 /*! @name DCDC Control APIs*/
680 /*@{*/
681
682 /*!
683 * @brief Sets DCDC battery monitor with its ADC value.
684 *
685 * For better accuracy, software would call this function to set the battery voltage value into DCDC
686 * measured by ADC.
687 *
688 * @param base SPM peripheral base address.
689 * @param batAdcVal ADC measured battery value with an 8mV LSB resolution.
690 * Value 0 would disable the battery monitor.
691 */
692 void SPM_SetDcdcBattMonitor(SPM_Type *base, uint32_t batAdcVal);
693
694 /*!
695 * @brief Sets DCDC VBAT voltage divider.
696 *
697 * The divided VBAT output is input to an ADC channel which allows the battery voltage to be measured.
698 *
699 * @param base SPM peripheral base address.
700 * @param divider Setting divider, see to #spm_dcdc_vbat_adc_divider_t.
701 */
SPM_SetDcdcVbatAdcMeasure(SPM_Type * base,spm_dcdc_vbat_adc_divider_t divider)702 static inline void SPM_SetDcdcVbatAdcMeasure(SPM_Type *base, spm_dcdc_vbat_adc_divider_t divider)
703 {
704 base->DCDCSC = (base->DCDCSC & ~SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK) | SPM_DCDCSC_DCDC_VBAT_DIV_CTRL(divider);
705 }
706
707 /*!
708 * @brief Power down output range comparator.
709 *
710 * @param base SPM peripheral base address.
711 * @param enable Power down the CMP or not.
712 */
SPM_EnablePowerDownCmpOffset(SPM_Type * base,bool enable)713 static inline void SPM_EnablePowerDownCmpOffset(SPM_Type *base, bool enable)
714 {
715 if (enable)
716 {
717 base->DCDCSC |= SPM_DCDCSC_PWD_CMP_OFFSET_MASK;
718 }
719 else
720 {
721 base->DCDCSC &= ~SPM_DCDCSC_PWD_CMP_OFFSET_MASK;
722 }
723 }
724
725 /*!
726 * @brief Get the status flags of DCDC module.
727 *
728 * @param base SPM peripheral base address.
729 * @return Mask value of flags. See to #_spm_dcdc_flags.
730 */
SPM_GetDcdcStatusFlags(SPM_Type * base)731 static inline uint32_t SPM_GetDcdcStatusFlags(SPM_Type *base)
732 {
733 return (base->DCDCSC & (SPM_DCDCSC_DCDC_STS_DC_OK_MASK | SPM_DCDCSC_CLKFLT_FAULT_MASK));
734 }
735
736 /*!
737 * @brief Disable stepping for VDD1P8 and VDD1P2.
738 *
739 * Must lock the step for VDD1P8 and VDD1p2 before enteing low power modes.
740 *
741 * @param base SPM peripheral base address.
742 * @param enable Enable the lock or not to VDDx stepping.
743 */
744 void SPM_EnableVddxStepLock(SPM_Type *base, bool enable);
745
746 /*!
747 * @brief Set the DCDC drive strength.
748 *
749 * Do set the DCDC drive strength according to actuall loading.
750 * The related register bits are:
751 * - DCDCC3[DCDC_MINPWR_HALF_FETS]
752 * - DCDCC3[DCDC_MINPWR_DOUBLE_FETS]
753 * - DCDCC3[DCDC_MINPWR_EXTRA_DOUBLE_FETS]
754 * The more FETs are enabled, the more drive strength DCDC would provide.
755 *
756 * @param base SPM peripheral base address.
757 * @param strength Selection of setting, see to #spm_dcdc_drive_strength_t
758 */
SPM_SetDcdcDriveStrength(SPM_Type * base,spm_dcdc_drive_strength_t strength)759 static inline void SPM_SetDcdcDriveStrength(SPM_Type *base, spm_dcdc_drive_strength_t strength)
760 {
761 base->DCDCC3 = (base->DCDCC3 & ~0xE000000U) | ((uint32_t)(strength) << 25);
762 }
763
764 /*!
765 * @brief Bypasses the ADC measure value
766 *
767 * Forces DCDC to bypass the adc measuring state and loads the user-defined value in this function.
768 *
769 * @param base SPM peripheral base address.
770 * @param enable Enable the bypass or not.
771 * @param value User-setting value to be available instead of ADC measured value.
772 */
773 void SPM_BypassDcdcBattMonitor(SPM_Type *base, bool enable, uint32_t value);
774
775 /*!
776 * @brief Configure the DCDC integrator value.
777 *
778 * Integrator value can be loaded in pulsed mode. Software can program this value according to
779 * battery voltage and VDD1P2 output target value before goes to the pulsed mode.
780 *
781 @code
782 spm_dcdc_integrator_config_t SpmDcdcIntegratorConfigStruct =
783 {
784 .vdd1p2Value = 1.2f,
785 .vBatValue = 3.34f
786 };
787 @endcode
788 *
789 * @param base SPM peripheral base address.
790 * @param config Pointer to configuration structure, see to #spm_dcdc_integrator_config_t.
791 * Passing NULL would clear all user-defined setting and use hardware default setting.
792 */
793 void SPM_SetDcdcIntegratorConfig(SPM_Type *base, const spm_dcdc_integrator_config_t *config);
794
795 /*!
796 * @brief Sets the target value of VDD1P2 in buck HSRUN mode.
797 *
798 * Sets target value of VDD1P2 in buck HSRUN mode. 25 mV each step from 0x00 to 0x0F. This value is
799 * automatically selected on entry into HSRUN. On exit from HSRUN, DCDC VDD1P2 trim values will
800 * default back to values set by DCDC_VDD1P2CTRL_TRG_BUCK register, which is operated with the API of
801 * SPM_SetDcdcVdd1p2ValueBuck().
802 *
803 * @param base SPM peripheral base address.
804 * @param value Setting value of VDD1P2 in buck HSRUN mode.
805 */
SPM_SetDcdcVdd1p2ValueHsrun(SPM_Type * base,uint32_t value)806 static inline void SPM_SetDcdcVdd1p2ValueHsrun(SPM_Type *base, uint32_t value)
807 {
808 base->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) | SPM_DCDCC6_DCDC_HSVDD_TRIM(value);
809 }
810
811 /*!
812 * @brief Sets the target value of VDD1P2 in buck mode.
813 *
814 * Sets the target value of VDD1P2 in buck mode, 25 mV each step from 0x00 to 0x0F.
815 *
816 * @param base SPM peripheral base address.
817 * @param value Setting value of VDD1P2 in buck mode.
818 */
SPM_SetDcdcVdd1p2ValueBuck(SPM_Type * base,uint32_t value)819 static inline void SPM_SetDcdcVdd1p2ValueBuck(SPM_Type *base, uint32_t value)
820 {
821 base->DCDCC6 =
822 (base->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK) | SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(value);
823 }
824
825 /*!
826 * @brief Sets the target value of VDD1P8.
827 *
828 * Sets the target value of VDD1P8 in buck mode, 25 mV each step from 0x00 to 0x3F.
829 *
830 * @param base SPM peripheral base address.
831 * @param value Setting value of VDD1P8 output.
832 */
SPM_SetDcdcVdd1p8Value(SPM_Type * base,uint32_t value)833 static inline void SPM_SetDcdcVdd1p8Value(SPM_Type *base, uint32_t value)
834 {
835 base->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK) | SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(value);
836 }
837
838 /*@}*/
839
840 /*! @name Misc */
841 /*@{*/
842
843 /*!
844 * @brief Configures the low power requeset output pin.
845 *
846 * @param base SPM peripheral base address.
847 * @param config Pointer to the configuration structure, see to #spm_low_power_req_out_pin_config_t.
848 */
849 void SPM_SetLowPowerReqOutPinConfig(SPM_Type *base, const spm_low_power_req_out_pin_config_t *config);
850
851 /*@}*/
852
853 /*@}*/
854
855 #if defined(__cplusplus)
856 }
857 #endif /* __cplusplus*/
858
859 /*! @}*/
860
861 #endif /* _FSL_SPM_H_*/
862
