1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_ADC16_H_
10 #define _FSL_ADC16_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup adc16
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief ADC16 driver version 2.3.0. */
26 #define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
27
28 /*@}*/
29
30 /*!
31 * @brief Channel status flags.
32 */
33 enum _adc16_channel_status_flags
34 {
35 kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */
36 };
37
38 /*!
39 * @brief Converter status flags.
40 */
41 enum _adc16_status_flags
42 {
43 kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */
44 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
45 kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */
46 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
47 };
48
49 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
50 /*!
51 * @brief Channel multiplexer mode for each channel.
52 *
53 * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
54 * are the different channels that share the same channel number.
55 */
56 typedef enum _adc_channel_mux_mode
57 {
58 kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */
59 kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */
60 } adc16_channel_mux_mode_t;
61 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
62
63 /*!
64 * @brief Clock divider for the converter.
65 */
66 typedef enum _adc16_clock_divider
67 {
68 kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */
69 kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */
70 kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */
71 kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */
72 } adc16_clock_divider_t;
73
74 /*!
75 *@brief Converter's resolution.
76 */
77 typedef enum _adc16_resolution
78 {
79 /* This group of enumeration is for internal use which is related to register setting. */
80 kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */
81 kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
82 kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
83
84 /* This group of enumeration is for a public user. */
85 kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */
86 kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
87 kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
88 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
89 kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */
90 kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */
91 kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */
92 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
93
94 #if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
95 /* 16-bit is supported by default. */
96 kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */
97 kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */
98 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
99 kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */
100 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
101 #endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */
102 } adc16_resolution_t;
103
104 /*!
105 * @brief Clock source.
106 */
107 typedef enum _adc16_clock_source
108 {
109 kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */
110 kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */
111 kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */
112 kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */
113
114 /* Chip defined clock source */
115 kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */
116 } adc16_clock_source_t;
117
118 /*!
119 * @brief Long sample mode.
120 */
121 typedef enum _adc16_long_sample_mode
122 {
123 kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */
124 kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */
125 kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */
126 kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */
127 kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */
128 } adc16_long_sample_mode_t;
129
130 /*!
131 * @brief Reference voltage source.
132 */
133 typedef enum _adc16_reference_voltage_source
134 {
135 kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */
136 kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */
137 #if defined(FSL_FEATURE_ADC16_HAS_VREF_BANDGAP) && FSL_FEATURE_ADC16_HAS_VREF_BANDGAP
138 kADC16_ReferenceVoltageSourceBandgap = 2U, /*!< For bandgap voltage from PMC. */
139 #endif /* FSL_FEATURE_ADC16_HAS_VREF_BANDGAP */
140 } adc16_reference_voltage_source_t;
141
142 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
143 /*!
144 * @brief Hardware average mode.
145 */
146 typedef enum _adc16_hardware_average_mode
147 {
148 kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
149 kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
150 kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
151 kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
152 kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/
153 } adc16_hardware_average_mode_t;
154 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
155
156 /*!
157 * @brief Hardware compare mode.
158 */
159 typedef enum _adc16_hardware_compare_mode
160 {
161 kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */
162 kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */
163 kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2;
164 else, value1 > x > value2. */
165 kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2;
166 else x >= value1 || x <= value2. */
167 } adc16_hardware_compare_mode_t;
168
169 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
170 /*!
171 * @brief PGA's Gain mode.
172 */
173 typedef enum _adc16_pga_gain
174 {
175 kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */
176 kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */
177 kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */
178 kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */
179 kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */
180 kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */
181 kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */
182 } adc16_pga_gain_t;
183 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
184
185 /*!
186 * @brief ADC16 converter configuration.
187 */
188 typedef struct _adc16_config
189 {
190 adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
191 adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */
192 bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */
193 adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */
194 adc16_resolution_t resolution; /*!< Select the sample resolution mode. */
195 adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */
196 bool enableHighSpeed; /*!< Enable the high-speed mode. */
197 bool enableLowPower; /*!< Enable low power. */
198 bool enableContinuousConversion; /*!< Enable continuous conversion mode. */
199 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
200 adc16_hardware_average_mode_t hardwareAverageMode; /*!< Set hardware average mode. */
201 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
202 } adc16_config_t;
203
204 /*!
205 * @brief ADC16 Hardware comparison configuration.
206 */
207 typedef struct _adc16_hardware_compare_config
208 {
209 adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
210 See "adc16_hardware_compare_mode_t". */
211 int16_t value1; /*!< Setting value1 for hardware compare mode. */
212 int16_t value2; /*!< Setting value2 for hardware compare mode. */
213 } adc16_hardware_compare_config_t;
214
215 /*!
216 * @brief ADC16 channel conversion configuration.
217 */
218 typedef struct _adc16_channel_config
219 {
220 uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
221 See channel connection information for each chip in Reference
222 Manual document. */
223 bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
224 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
225 bool enableDifferentialConversion; /*!< Using Differential sample mode. */
226 #endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
227 } adc16_channel_config_t;
228
229 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
230 /*!
231 * @brief ADC16 programmable gain amplifier configuration.
232 */
233 typedef struct _adc16_pga_config
234 {
235 adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */
236 bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */
237 #if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
238 bool disablePgaChopping; /*!< Disable the PGA chopping function.
239 The PGA employs chopping to remove/reduce offset and 1/f noise and offers
240 an offset measurement configuration that aids the offset calibration. */
241 #endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
242 #if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
243 bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode.
244 When this feature is enabled, the PGA disconnects itself from the external
245 inputs and auto-configures into offset measurement mode. With this field
246 set, run the ADC in the recommended settings and enable the maximum hardware
247 averaging to get the PGA offset number. The output is the
248 (PGA offset * (64+1)) for the given PGA setting. */
249 #endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
250 } adc16_pga_config_t;
251 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
252
253 #if defined(__cplusplus)
254 extern "C" {
255 #endif
256
257 /*******************************************************************************
258 * API
259 ******************************************************************************/
260
261 /*!
262 * @name Initialization
263 * @{
264 */
265
266 /*!
267 * @brief Initializes the ADC16 module.
268 *
269 * @param base ADC16 peripheral base address.
270 * @param config Pointer to configuration structure. See "adc16_config_t".
271 */
272 void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
273
274 /*!
275 * @brief De-initializes the ADC16 module.
276 *
277 * @param base ADC16 peripheral base address.
278 */
279 void ADC16_Deinit(ADC_Type *base);
280
281 /*!
282 * @brief Gets an available pre-defined settings for the converter's configuration.
283 *
284 * This function initializes the converter configuration structure with available settings. The default values are as
285 * follows.
286 * @code
287 * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
288 * config->clockSource = kADC16_ClockSourceAsynchronousClock;
289 * config->enableAsynchronousClock = false;
290 * config->clockDivider = kADC16_ClockDivider8;
291 * config->resolution = kADC16_ResolutionSE12Bit;
292 * config->longSampleMode = kADC16_LongSampleDisabled;
293 * config->enableHighSpeed = false;
294 * config->enableLowPower = false;
295 * config->enableContinuousConversion = false;
296 * @endcode
297 * @param config Pointer to the configuration structure.
298 */
299 void ADC16_GetDefaultConfig(adc16_config_t *config);
300
301 #if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
302 /*!
303 * @brief Automates the hardware calibration.
304 *
305 * This auto calibration helps to adjust the plus/minus side gain automatically.
306 * Execute the calibration before using the converter. Note that the hardware trigger should be used
307 * during the calibration.
308 *
309 * @param base ADC16 peripheral base address.
310 *
311 * @return Execution status.
312 * @retval kStatus_Success Calibration is done successfully.
313 * @retval kStatus_Fail Calibration has failed.
314 */
315 status_t ADC16_DoAutoCalibration(ADC_Type *base);
316 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
317
318 #if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION
319 /*!
320 * @brief Sets the offset value for the conversion result.
321 *
322 * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result
323 * is subtracted by it. Note, the hardware calibration fills the offset value automatically.
324 *
325 * @param base ADC16 peripheral base address.
326 * @param value Setting offset value.
327 */
ADC16_SetOffsetValue(ADC_Type * base,int16_t value)328 static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
329 {
330 base->OFS = (uint32_t)(value);
331 }
332 #endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */
333
334 /* @} */
335
336 /*!
337 * @name Advanced Features
338 * @{
339 */
340
341 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
342 /*!
343 * @brief Enables generating the DMA trigger when the conversion is complete.
344 *
345 * @param base ADC16 peripheral base address.
346 * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
347 */
ADC16_EnableDMA(ADC_Type * base,bool enable)348 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
349 {
350 if (enable)
351 {
352 base->SC2 |= ADC_SC2_DMAEN_MASK;
353 }
354 else
355 {
356 base->SC2 &= ~ADC_SC2_DMAEN_MASK;
357 }
358 }
359 #endif /* FSL_FEATURE_ADC16_HAS_DMA */
360
361 /*!
362 * @brief Enables the hardware trigger mode.
363 *
364 * @param base ADC16 peripheral base address.
365 * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
366 */
ADC16_EnableHardwareTrigger(ADC_Type * base,bool enable)367 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
368 {
369 if (enable)
370 {
371 base->SC2 |= ADC_SC2_ADTRG_MASK;
372 }
373 else
374 {
375 base->SC2 &= ~ADC_SC2_ADTRG_MASK;
376 }
377 }
378
379 #if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
380 /*!
381 * @brief Sets the channel mux mode.
382 *
383 * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an
384 * indicated channel.
385 *
386 * @param base ADC16 peripheral base address.
387 * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t".
388 */
389 void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
390 #endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
391
392 /*!
393 * @brief Configures the hardware compare mode.
394 *
395 * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
396 * result
397 * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate
398 * reference
399 * manual for more information.
400 *
401 * @param base ADC16 peripheral base address.
402 * @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
403 */
404 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
405
406 #if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
407 /*!
408 * @brief Sets the hardware average mode.
409 *
410 * The hardware average mode provides a way to process the conversion result automatically by using hardware. The
411 * multiple
412 * conversion results are accumulated and averaged internally making them easier to read.
413 *
414 * @param base ADC16 peripheral base address.
415 * @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t".
416 */
417 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
418 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
419
420 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
421 /*!
422 * @brief Configures the PGA for the converter's front end.
423 *
424 * @param base ADC16 peripheral base address.
425 * @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
426 */
427 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
428 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
429
430 /*!
431 * @brief Gets the status flags of the converter.
432 *
433 * @param base ADC16 peripheral base address.
434 *
435 * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags".
436 */
437 uint32_t ADC16_GetStatusFlags(ADC_Type *base);
438
439 /*!
440 * @brief Clears the status flags of the converter.
441 *
442 * @param base ADC16 peripheral base address.
443 * @param mask Mask value for the cleared flags. See "_adc16_status_flags".
444 */
445 void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
446
447 /*!
448 * @brief Enable/disable ADC Asynchronous clock output to other modules.
449 *
450 * @param base ADC16 peripheral base address.
451 * @param enable Used to enable/disable ADC ADACK output.
452 * - \b true Asynchronous clock and clock output is enabled regardless of the state of the ADC.
453 * - \b false Asynchronous clock output disabled, asynchronous clock is enabled only if it is selected as
454 * input clock and a conversion is active.
455 */
ADC16_EnableAsynchronousClockOutput(ADC_Type * base,bool enable)456 static inline void ADC16_EnableAsynchronousClockOutput(ADC_Type *base, bool enable)
457 {
458 if (enable)
459 {
460 base->CFG2 |= ADC_CFG2_ADACKEN_MASK;
461 }
462 else
463 {
464 base->CFG2 &= ~ADC_CFG2_ADACKEN_MASK;
465 }
466 }
467
468 /* @} */
469
470 /*!
471 * @name Conversion Channel
472 * @{
473 */
474
475 /*!
476 * @brief Configures the conversion channel.
477 *
478 * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
479 * configures the channel while the external trigger source helps to trigger the conversion.
480 *
481 * Note that the "Channel Group" has a detailed description.
482 * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
483 * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
484 * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B
485 * registers. The
486 * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
487 * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
488 * hardware
489 * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
490 * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for
491 * the
492 * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used
493 * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
494 * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
495 * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
496 * conversion aborts the current conversion.
497 *
498 * @param base ADC16 peripheral base address.
499 * @param channelGroup Channel group index.
500 * @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel.
501 */
502 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
503
504 /*!
505 * @brief Gets the conversion value.
506 *
507 * @param base ADC16 peripheral base address.
508 * @param channelGroup Channel group index.
509 *
510 * @return Conversion value.
511 */
ADC16_GetChannelConversionValue(ADC_Type * base,uint32_t channelGroup)512 static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
513 {
514 assert(channelGroup < (uint32_t)FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT);
515
516 return base->R[channelGroup];
517 }
518
519 /*!
520 * @brief Gets the status flags of channel.
521 *
522 * @param base ADC16 peripheral base address.
523 * @param channelGroup Channel group index.
524 *
525 * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags".
526 */
527 uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup);
528
529 /* @} */
530
531 #if defined(__cplusplus)
532 }
533 #endif
534 /*!
535 * @}
536 */
537 #endif /* _FSL_ADC16_H_ */
538
