1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <string.h>
7 #include "sdkconfig.h"
8 #include "esp_attr.h"
9 #include "hal/emac_hal.h"
10 #include "hal/emac_ll.h"
11 #include "hal/gpio_ll.h"
12
13 #define ETH_CRC_LENGTH (4)
14
emac_hal_iomux_init_mii(void)15 void emac_hal_iomux_init_mii(void)
16 {
17 /* TX_CLK to GPIO0 */
18 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
19 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
20 /* TX_EN to GPIO21 */
21 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN);
22 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);
23 /* TXD0 to GPIO19 */
24 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
25 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);
26 /* TXD1 to GPIO22 */
27 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1);
28 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);
29 /* TXD2 to MTMS */
30 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTMS_U, FUNC_MTMS_EMAC_TXD2);
31 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[14]);
32 /* TXD3 to MTDI */
33 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTDI_U, FUNC_MTDI_EMAC_TXD3);
34 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[12]);
35
36 /* RX_CLK to GPIO5 */
37 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, FUNC_GPIO5_EMAC_RX_CLK);
38 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[5]);
39 /* RX_DV to GPIO27 */
40 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
41 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);
42 /* RXD0 to GPIO25 */
43 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0);
44 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);
45 /* RXD1 to GPIO26 */
46 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1);
47 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);
48 /* RXD2 to U0TXD */
49 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_EMAC_RXD2);
50 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[1]);
51 /* RXD3 to MTDO */
52 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTDO_U, FUNC_MTDO_EMAC_RXD3);
53 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[15]);
54 }
55
emac_hal_iomux_rmii_clk_input(void)56 void emac_hal_iomux_rmii_clk_input(void)
57 {
58 /* REF_CLK(RMII mode) to GPIO0 */
59 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
60 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
61 }
62
emac_hal_iomux_rmii_clk_ouput(int num)63 void emac_hal_iomux_rmii_clk_ouput(int num)
64 {
65 switch (num) {
66 case 0:
67 /* APLL clock output to GPIO0 (must be configured to 50MHz!) */
68 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
69 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
70 break;
71 case 16:
72 /* RMII CLK (50MHz) output to GPIO16 */
73 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
74 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
75 break;
76 case 17:
77 /* RMII CLK (50MHz) output to GPIO17 */
78 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
79 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
80 break;
81 default:
82 break;
83 }
84 }
85
emac_hal_iomux_init_rmii(void)86 void emac_hal_iomux_init_rmii(void)
87 {
88 /* TX_EN to GPIO21 */
89 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN);
90 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);
91 /* TXD0 to GPIO19 */
92 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
93 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);
94 /* TXD1 to GPIO22 */
95 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1);
96 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);
97
98 /* CRS_DV to GPIO27 */
99 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
100 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);
101 /* RXD0 to GPIO25 */
102 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0);
103 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);
104 /* RXD1 to GPIO26 */
105 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1);
106 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);
107 }
108
emac_hal_iomux_init_tx_er(void)109 void emac_hal_iomux_init_tx_er(void)
110 {
111 /* TX_ER to GPIO4 */
112 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO4_U, FUNC_GPIO4_EMAC_TX_ER);
113 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[4]);
114 }
115
emac_hal_iomux_init_rx_er(void)116 void emac_hal_iomux_init_rx_er(void)
117 {
118 /* RX_ER to MTCK */
119 gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTCK_U, FUNC_MTCK_EMAC_RX_ER);
120 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[13]);
121 }
122
emac_hal_init(emac_hal_context_t * hal,void * descriptors,uint8_t ** rx_buf,uint8_t ** tx_buf)123 void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
124 uint8_t **rx_buf, uint8_t **tx_buf)
125 {
126 hal->dma_regs = &EMAC_DMA;
127 hal->mac_regs = &EMAC_MAC;
128 hal->ext_regs = &EMAC_EXT;
129 hal->descriptors = descriptors;
130 hal->rx_buf = rx_buf;
131 hal->tx_buf = tx_buf;
132 }
133
emac_hal_set_csr_clock_range(emac_hal_context_t * hal,int freq)134 void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
135 {
136 /* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
137 if (freq >= 20000000 && freq < 35000000) {
138 emac_ll_set_csr_clock_division(hal->mac_regs, 2); // CSR clock/16
139 } else if (freq >= 35000000 && freq < 60000000) {
140 emac_ll_set_csr_clock_division(hal->mac_regs, 3); // CSR clock/26
141 } else if (freq >= 60000000 && freq < 100000000) {
142 emac_ll_set_csr_clock_division(hal->mac_regs, 0); // CSR clock/42
143 } else if (freq >= 100000000 && freq < 150000000) {
144 emac_ll_set_csr_clock_division(hal->mac_regs, 1); // CSR clock/62
145 } else if (freq >= 150000000 && freq < 250000000) {
146 emac_ll_set_csr_clock_division(hal->mac_regs, 4); // CSR clock/102
147 } else {
148 emac_ll_set_csr_clock_division(hal->mac_regs, 5); // CSR clock/124
149 }
150 }
151
emac_hal_reset_desc_chain(emac_hal_context_t * hal)152 void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
153 {
154 /* reset DMA descriptors */
155 hal->rx_desc = (eth_dma_rx_descriptor_t *)(hal->descriptors);
156 hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->rx_desc +
157 CONFIG_ETH_DMA_RX_BUFFER_NUM);
158 /* init rx chain */
159 for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
160 /* Set Own bit of the Rx descriptor Status: DMA */
161 hal->rx_desc[i].RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
162 /* Set Buffer1 size and Second Address Chained bit */
163 hal->rx_desc[i].RDES1.SecondAddressChained = 1;
164 hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
165 /* Enable Ethernet DMA Rx Descriptor interrupt */
166 hal->rx_desc[i].RDES1.DisableInterruptOnComplete = 0;
167 /* point to the buffer */
168 hal->rx_desc[i].Buffer1Addr = (uint32_t)(hal->rx_buf[i]);
169 /* point to next descriptor */
170 hal->rx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc + i + 1);
171 }
172 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
173 hal->rx_desc[CONFIG_ETH_DMA_RX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc);
174
175 /* init tx chain */
176 for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
177 /* Set Own bit of the Tx descriptor Status: CPU */
178 hal->tx_desc[i].TDES0.Own = EMAC_LL_DMADESC_OWNER_CPU;
179 hal->tx_desc[i].TDES0.SecondAddressChained = 1;
180 hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
181 /* Enable Ethernet DMA Tx Descriptor interrupt */
182 hal->tx_desc[1].TDES0.InterruptOnComplete = 1;
183 /* Enable Transmit Timestamp */
184 hal->tx_desc[i].TDES0.TransmitTimestampEnable = 1;
185 /* point to the buffer */
186 hal->tx_desc[i].Buffer1Addr = (uint32_t)(hal->tx_buf[i]);
187 /* point to next descriptor */
188 hal->tx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc + i + 1);
189 }
190 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
191 hal->tx_desc[CONFIG_ETH_DMA_TX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc);
192
193 /* set base address of the first descriptor */
194 emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)hal->rx_desc);
195 emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)hal->tx_desc);
196 }
197
emac_hal_init_mac_default(emac_hal_context_t * hal)198 void emac_hal_init_mac_default(emac_hal_context_t *hal)
199 {
200 /* MACCR Configuration */
201 /* Enable the watchdog on the receiver, frame longer than 2048 Bytes is not allowed */
202 emac_ll_watchdog_enable(hal->mac_regs, true);
203 /* Enable the jabber timer on the transmitter, frame longer than 2048 Bytes is not allowed */
204 emac_ll_jabber_enable(hal->mac_regs, true);
205 /* minimum IFG between frames during transmission is 96 bit times */
206 emac_ll_set_inter_frame_gap(hal->mac_regs, EMAC_LL_INTERFRAME_GAP_96BIT);
207 /* Enable Carrier Sense During Transmission */
208 emac_ll_carrier_sense_enable(hal->mac_regs, true);
209 /* Select speed: port: 10/100 Mbps, here set default 100M, afterwards, will reset by auto-negotiation */
210 emac_ll_set_port_speed(hal->mac_regs, ETH_SPEED_100M);;
211 /* Allow the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
212 emac_ll_recv_own_enable(hal->mac_regs, true);
213 /* Disable internal loopback mode */
214 emac_ll_loopback_enable(hal->mac_regs, false);
215 /* Select duplex mode: here set default full duplex, afterwards, will reset by auto-negotiation */
216 emac_ll_set_duplex(hal->mac_regs, ETH_DUPLEX_FULL);
217 /* Select the checksum mode for received frame payload's TCP/UDP/ICMP headers */
218 emac_ll_checksum_offload_mode(hal->mac_regs, ETH_CHECKSUM_HW);
219 /* Enable MAC retry transmission when a colision occurs in half duplex mode */
220 emac_ll_retry_enable(hal->mac_regs, true);
221 /* MAC passes all incoming frames to host, without modifying them */
222 emac_ll_auto_pad_crc_strip_enable(hal->mac_regs, false);
223 /* Set Back-Off limit time before retry a transmittion after a collision */
224 emac_ll_set_back_off_limit(hal->mac_regs, EMAC_LL_BACKOFF_LIMIT_10);
225 /* Disable deferral check, MAC defers until the CRS signal goes inactive */
226 emac_ll_deferral_check_enable(hal->mac_regs, false);
227 /* Set preamble length 7 Bytes */
228 emac_ll_set_preamble_length(hal->mac_regs, EMAC_LL_PREAMBLE_LENGTH_7);
229
230 /* MACFFR Configuration */
231 /* Receiver module passes only those frames to the Application that pass the SA or DA address filter */
232 emac_ll_receive_all_enable(hal->mac_regs, false);
233 /* Disable source address filter */
234 emac_ll_set_src_addr_filter(hal->mac_regs, EMAC_LL_SOURCE_ADDR_FILTER_DISABLE);
235 emac_ll_sa_inverse_filter_enable(hal->mac_regs, false);
236 /* MAC blocks all control frames */
237 emac_ll_set_pass_ctrl_frame_mode(hal->mac_regs, EMAC_LL_CONTROL_FRAME_BLOCKALL);
238 /* AFM module passes all received broadcast frames and multicast frames */
239 emac_ll_broadcast_frame_enable(hal->mac_regs, true);
240 emac_ll_pass_all_multicast_enable(hal->mac_regs, true);
241 /* Address Check block operates in normal filtering mode for the DA address */
242 emac_ll_da_inverse_filter_enable(hal->mac_regs, false);
243 /* Disable Promiscuous Mode */
244 emac_ll_promiscuous_mode_enable(hal->mac_regs, false);
245 }
246
emac_hal_enable_flow_ctrl(emac_hal_context_t * hal,bool enable)247 void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable)
248 {
249 /* MACFCR Configuration */
250 if (enable) {
251 /* Pause time */
252 emac_ll_set_pause_time(hal->mac_regs, EMAC_LL_PAUSE_TIME);
253 /* Enable generation of Zero-Quanta Pause Control frames */
254 emac_ll_zero_quanta_pause_enable(hal->mac_regs, true);
255 /* Threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
256 emac_ll_set_pause_low_threshold(hal->mac_regs, EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_28);
257 /* Don't allow MAC detect Pause frames with MAC address0 unicast address and unique multicast address */
258 emac_ll_unicast_pause_frame_detect_enable(hal->mac_regs, false);
259 /* Enable MAC to decode the received Pause frame and disable its transmitter for a specific time */
260 emac_ll_receive_flow_ctrl_enable(hal->mac_regs, true);
261 /* Enable MAC to transmit Pause frames in full duplex mode or the MAC back-pressure operation in half duplex mode */
262 emac_ll_transmit_flow_ctrl_enable(hal->mac_regs, true);
263 } else {
264 emac_ll_clear(hal->mac_regs);
265 }
266 }
267
emac_hal_init_dma_default(emac_hal_context_t * hal)268 void emac_hal_init_dma_default(emac_hal_context_t *hal)
269 {
270 /* DMAOMR Configuration */
271 /* Enable Dropping of TCP/IP Checksum Error Frames */
272 emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);
273 /* Enable Receive Store Forward */
274 emac_ll_recv_store_forward_enable(hal->dma_regs, true);
275 /* Enable Flushing of Received Frames because of the unavailability of receive descriptors or buffers */
276 emac_ll_flush_recv_frame_enable(hal->dma_regs, true);
277 /* Disable Transmit Store Forward */
278 emac_ll_trans_store_forward_enable(hal->dma_regs, false);
279 /* Flush Transmit FIFO */
280 emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
281 /* Transmit Threshold Control */
282 emac_ll_set_transmit_threshold(hal->dma_regs, EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64);
283 /* Disable Forward Error Frame */
284 emac_ll_forward_err_frame_enable(hal->dma_regs, false);
285 /* Disable forward undersized good frame */
286 emac_ll_forward_undersized_good_frame_enable(hal->dma_regs, false);
287 /* Receive Threshold Control */
288 emac_ll_set_recv_threshold(hal->dma_regs, EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64);
289 /* Allow the DMA to process a second frame of Transmit data even before obtaining the status for the first frame */
290 emac_ll_opt_second_frame_enable(hal->dma_regs, true);;
291
292 /* DMABMR Configuration */
293 /* Enable Mixed Burst */
294 emac_ll_mixed_burst_enable(hal->dma_regs, true);
295 /* Enable Address Aligned Beates */
296 emac_ll_addr_align_enable(hal->dma_regs, true);
297 /* Use Separate PBL */
298 emac_ll_use_separate_pbl_enable(hal->dma_regs, true);
299 /* Set Rx/Tx DMA Burst Length */
300 emac_ll_set_rx_dma_pbl(hal->dma_regs, EMAC_LL_DMA_BURST_LENGTH_32BEAT);
301 emac_ll_set_prog_burst_len(hal->dma_regs, EMAC_LL_DMA_BURST_LENGTH_32BEAT);
302 /* Enable Enhanced Descriptor,8 Words(32 Bytes) */
303 emac_ll_enhance_desc_enable(hal->dma_regs, true);
304 /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
305 emac_ll_set_desc_skip_len(hal->dma_regs, 0);
306 /* DMA Arbitration Scheme */
307 emac_ll_fixed_arbitration_enable(hal->dma_regs, false);
308 /* Set priority ratio in the weighted round-robin arbitration between Rx DMA and Tx DMA */
309 emac_ll_set_priority_ratio(hal->dma_regs, EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1);
310 }
311
emac_hal_set_phy_cmd(emac_hal_context_t * hal,uint32_t phy_addr,uint32_t phy_reg,bool write)312 void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write)
313 {
314 /* Write the result value into the MII Address register */
315 emac_ll_set_phy_addr(hal->mac_regs, phy_addr);
316 /* Set the PHY register address */
317 emac_ll_set_phy_reg(hal->mac_regs, phy_reg);
318 /* Set as write mode */
319 emac_ll_write_enable(hal->mac_regs, write);
320 /* Set MII busy bit */
321 emac_ll_set_busy(hal->mac_regs, true);
322
323 }
324
emac_hal_set_address(emac_hal_context_t * hal,uint8_t * mac_addr)325 void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr)
326 {
327 /* Make sure mac address is unicast type */
328 if (!(mac_addr[0] & 0x01)) {
329 emac_ll_set_addr(hal->mac_regs, mac_addr);
330 }
331 }
332
emac_hal_start(emac_hal_context_t * hal)333 void emac_hal_start(emac_hal_context_t *hal)
334 {
335 /* Enable Ethernet MAC and DMA Interrupt */
336 emac_ll_enable_corresponding_intr(hal->dma_regs, EMAC_LL_CONFIG_ENABLE_INTR_MASK);
337
338 /* Flush Transmit FIFO */
339 emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
340
341 /* Start DMA transmission */
342 emac_ll_start_stop_dma_transmit(hal->dma_regs, true);
343 /* Start DMA reception */
344 emac_ll_start_stop_dma_receive(hal->dma_regs, true);
345
346 /* Enable transmit state machine of the MAC for transmission on the MII */
347 emac_ll_transmit_enable(hal->mac_regs, true);
348 /* Enable receive state machine of the MAC for reception from the MII */
349 emac_ll_receive_enable(hal->mac_regs, true);
350
351 /* Clear all pending interrupts */
352 emac_ll_clear_all_pending_intr(hal->dma_regs);
353 }
354
emac_hal_stop(emac_hal_context_t * hal)355 esp_err_t emac_hal_stop(emac_hal_context_t *hal)
356 {
357 /* Stop DMA transmission */
358 emac_ll_start_stop_dma_transmit(hal->dma_regs, false);
359
360 if (emac_ll_transmit_frame_ctrl_status(hal->mac_regs) != 0x0) {
361 /* Previous transmit in progress */
362 return ESP_ERR_INVALID_STATE;
363 }
364
365 /* Disable transmit state machine of the MAC for transmission on the MII */
366 emac_ll_receive_enable(hal->mac_regs, false);
367 /* Disable receive state machine of the MAC for reception from the MII */
368 emac_ll_transmit_enable(hal->mac_regs, false);
369
370 if (emac_ll_receive_read_ctrl_state(hal->mac_regs) != 0x0) {
371 /* Previous receive copy in progress */
372 return ESP_ERR_INVALID_STATE;
373 }
374
375 /* Stop DMA reception */
376 emac_ll_start_stop_dma_receive(hal->dma_regs, false);
377
378 /* Disable Ethernet MAC and DMA Interrupt */
379 emac_ll_disable_all_intr(hal->dma_regs);
380
381 return ESP_OK;
382 }
383
emac_hal_get_tx_desc_owner(emac_hal_context_t * hal)384 uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal)
385 {
386 return hal->tx_desc->TDES0.Own;
387 }
388
emac_hal_transmit_frame(emac_hal_context_t * hal,uint8_t * buf,uint32_t length)389 uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length)
390 {
391 /* Get the number of Tx buffers to use for the frame */
392 uint32_t bufcount = 0;
393 uint32_t lastlen = length;
394 uint32_t sentout = 0;
395 while (lastlen > CONFIG_ETH_DMA_BUFFER_SIZE) {
396 lastlen -= CONFIG_ETH_DMA_BUFFER_SIZE;
397 bufcount++;
398 }
399 if (lastlen) {
400 bufcount++;
401 }
402 if (bufcount > CONFIG_ETH_DMA_TX_BUFFER_NUM) {
403 goto err;
404 }
405
406 eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;
407 /* A frame is transmitted in multiple descriptor */
408 for (size_t i = 0; i < bufcount; i++) {
409 /* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
410 if (desc_iter->TDES0.Own != EMAC_LL_DMADESC_OWNER_CPU) {
411 goto err;
412 }
413 /* Clear FIRST and LAST segment bits */
414 desc_iter->TDES0.FirstSegment = 0;
415 desc_iter->TDES0.LastSegment = 0;
416 desc_iter->TDES0.InterruptOnComplete = 0;
417 if (i == 0) {
418 /* Setting the first segment bit */
419 desc_iter->TDES0.FirstSegment = 1;
420 }
421 if (i == (bufcount - 1)) {
422 /* Setting the last segment bit */
423 desc_iter->TDES0.LastSegment = 1;
424 /* Enable transmit interrupt */
425 desc_iter->TDES0.InterruptOnComplete = 1;
426 /* Program size */
427 desc_iter->TDES1.TransmitBuffer1Size = lastlen;
428 /* copy data from uplayer stack buffer */
429 memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, lastlen);
430 sentout += lastlen;
431 } else {
432 /* Program size */
433 desc_iter->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
434 /* copy data from uplayer stack buffer */
435 memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, CONFIG_ETH_DMA_BUFFER_SIZE);
436 sentout += CONFIG_ETH_DMA_BUFFER_SIZE;
437 }
438 /* Point to next descriptor */
439 desc_iter = (eth_dma_tx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
440 }
441
442 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
443 for (size_t i = 0; i < bufcount; i++) {
444 hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
445 hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);
446 }
447 emac_ll_transmit_poll_demand(hal->dma_regs, 0);
448 return sentout;
449 err:
450 return 0;
451 }
452
emac_hal_receive_frame(emac_hal_context_t * hal,uint8_t * buf,uint32_t size,uint32_t * frames_remain,uint32_t * free_desc)453 uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain, uint32_t *free_desc)
454 {
455 eth_dma_rx_descriptor_t *desc_iter = NULL;
456 eth_dma_rx_descriptor_t *first_desc = NULL;
457 uint32_t used_descs = 0;
458 uint32_t seg_count = 0;
459 uint32_t ret_len = 0;
460 uint32_t copy_len = 0;
461 uint32_t write_len = 0;
462 uint32_t frame_count = 0;
463
464 first_desc = hal->rx_desc;
465 desc_iter = hal->rx_desc;
466 /* Traverse descriptors owned by CPU */
467 while ((desc_iter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM) && !frame_count) {
468 used_descs++;
469 seg_count++;
470 /* Last segment in frame */
471 if (desc_iter->RDES0.LastDescriptor) {
472 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
473 ret_len = desc_iter->RDES0.FrameLength - ETH_CRC_LENGTH;
474 /* packets larger than expected will be truncated */
475 copy_len = ret_len > size ? size : ret_len;
476 /* update unhandled frame count */
477 frame_count++;
478 }
479 /* First segment in frame */
480 if (desc_iter->RDES0.FirstDescriptor) {
481 first_desc = desc_iter;
482 }
483 /* point to next descriptor */
484 desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
485 }
486 /* there's at least one frame to process */
487 if (frame_count) {
488 /* check how many frames left to handle */
489 while ((desc_iter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM)) {
490 used_descs++;
491 if (desc_iter->RDES0.LastDescriptor) {
492 frame_count++;
493 }
494 /* point to next descriptor */
495 desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
496 }
497 desc_iter = first_desc;
498 for (size_t i = 0; i < seg_count - 1; i++) {
499 used_descs--;
500 write_len = copy_len < CONFIG_ETH_DMA_BUFFER_SIZE ? copy_len : CONFIG_ETH_DMA_BUFFER_SIZE;
501 /* copy data to buffer */
502 memcpy(buf, (void *)(desc_iter->Buffer1Addr), write_len);
503 buf += write_len;
504 copy_len -= write_len;
505 /* Set Own bit in Rx descriptors: gives the buffers back to DMA */
506 desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
507 desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
508 }
509 memcpy(buf, (void *)(desc_iter->Buffer1Addr), copy_len);
510 desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
511 /* update rxdesc */
512 hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
513 /* poll rx demand */
514 emac_ll_receive_poll_demand(hal->dma_regs, 0);
515 frame_count--;
516 used_descs--;
517 }
518 *frames_remain = frame_count;
519 *free_desc = CONFIG_ETH_DMA_RX_BUFFER_NUM - used_descs;
520 return ret_len;
521 }
522
