1 /* 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 #include <stdint.h> 14 #include <stdbool.h> 15 #include "esp_err.h" 16 #include "hal/eth_types.h" 17 #include "soc/emac_dma_struct.h" 18 #include "soc/emac_mac_struct.h" 19 #include "soc/emac_ext_struct.h" 20 21 /** 22 * @brief Ethernet DMA TX Descriptor 23 * 24 */ 25 typedef struct { 26 volatile union { 27 struct { 28 uint32_t Deferred : 1; /*!< MAC defers before transmission */ 29 uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */ 30 uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */ 31 uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */ 32 uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */ 33 uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */ 34 uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */ 35 uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */ 36 uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */ 37 uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */ 38 uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */ 39 uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */ 40 uint32_t ErrSummary : 1; /*!< Error Summary */ 41 uint32_t IPHeadErr : 1; /*!< IP Header Error */ 42 uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */ 43 uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */ 44 uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */ 45 uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */ 46 uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */ 47 uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */ 48 uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 harware timestamping */ 49 uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */ 50 uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */ 51 uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */ 52 uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */ 53 uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */ 54 uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */ 55 }; 56 uint32_t Value; 57 } TDES0; 58 union { 59 struct { 60 uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */ 61 uint32_t Reserved : 3; /*!< Reserved */ 62 uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */ 63 uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */ 64 }; 65 uint32_t Value; 66 } TDES1; 67 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 68 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 69 uint32_t Reserved1; /*!< Reserved */ 70 uint32_t Reserved2; /*!< Reserved */ 71 uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */ 72 uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */ 73 } eth_dma_tx_descriptor_t; 74 #define EMAC_DMATXDESC_CHECKSUM_BYPASS 0 /*!< Checksum engine bypass */ 75 #define EMAC_DMATXDESC_CHECKSUM_IPV4HEADER 1 /*!< IPv4 header checksum insertion */ 76 #define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 77 #define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 78 79 _Static_assert(sizeof(eth_dma_tx_descriptor_t) == 32, "eth_dma_tx_descriptor_t should occupy 32 bytes in memory"); 80 81 /** 82 * @brief Ethernet DMA RX Descriptor 83 * 84 */ 85 typedef struct { 86 volatile union { 87 struct { 88 uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */ 89 uint32_t CRCErr : 1; /*!< CRC error occurred on frame */ 90 uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */ 91 uint32_t ReceiveErr : 1; /*!< Receive error */ 92 uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */ 93 uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */ 94 uint32_t LateCollision : 1; /*!< Late collision occurred during reception */ 95 uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */ 96 uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */ 97 uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */ 98 uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */ 99 uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */ 100 uint32_t LengthErr : 1; /*!< Frame size not matching with length field */ 101 uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */ 102 uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */ 103 uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */ 104 uint32_t FrameLength : 14; /*!< Byte length of received frame */ 105 uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */ 106 uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */ 107 }; 108 uint32_t Value; 109 } RDES0; 110 union { 111 struct { 112 uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */ 113 uint32_t Reserved1 : 1; /*!< Reserved */ 114 uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */ 115 uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */ 116 uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */ 117 uint32_t Reserved : 2; /*!< Reserved */ 118 uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */ 119 }; 120 uint32_t Value; 121 } RDES1; 122 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 123 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 124 volatile union { 125 struct { 126 uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */ 127 uint32_t IPHeadErr : 1; /*!< IP header error */ 128 uint32_t IPPayloadErr : 1; /*!< IP payload error */ 129 uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */ 130 uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */ 131 uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */ 132 uint32_t MessageType : 4; /*!< PTP Message Type */ 133 uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */ 134 uint32_t PTPVersion : 1; /*!< Version of PTP protocol */ 135 uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */ 136 uint32_t Reserved1 : 1; /*!< Reserved */ 137 uint32_t AVPacketReceived : 1; /*!< AV packet is received */ 138 uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */ 139 uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */ 140 uint32_t Reserved2 : 3; /*!< Reserved */ 141 uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */ 142 uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */ 143 uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */ 144 uint32_t Reserved3 : 4; /*!< Reserved */ 145 }; 146 uint32_t Value; 147 } ExtendedStatus; 148 uint32_t Reserved; /*!< Reserved */ 149 uint32_t TimeStampLow; /*!< Receive frame timestamp low */ 150 uint32_t TimeStampHigh; /*!< Receive frame timestamp high */ 151 } eth_dma_rx_descriptor_t; 152 153 _Static_assert(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory"); 154 155 typedef struct { 156 emac_mac_dev_t *mac_regs; 157 emac_dma_dev_t *dma_regs; 158 emac_ext_dev_t *ext_regs; 159 uint8_t **rx_buf; 160 uint8_t **tx_buf; 161 void *descriptors; 162 eth_dma_rx_descriptor_t *rx_desc; 163 eth_dma_tx_descriptor_t *tx_desc; 164 165 } emac_hal_context_t; 166 167 void emac_hal_init(emac_hal_context_t *hal, void *descriptors, 168 uint8_t **rx_buf, uint8_t **tx_buf); 169 170 void emac_hal_iomux_init_mii(void); 171 172 void emac_hal_iomux_init_rmii(void); 173 174 void emac_hal_iomux_rmii_clk_input(void); 175 176 void emac_hal_iomux_rmii_clk_ouput(int num); 177 178 void emac_hal_iomux_init_tx_er(void); 179 180 void emac_hal_iomux_init_rx_er(void); 181 182 void emac_hal_reset_desc_chain(emac_hal_context_t *hal); 183 184 void emac_hal_reset(emac_hal_context_t *hal); 185 186 bool emac_hal_is_reset_done(emac_hal_context_t *hal); 187 188 void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq); 189 190 void emac_hal_init_mac_default(emac_hal_context_t *hal); 191 192 void emac_hal_init_dma_default(emac_hal_context_t *hal); 193 194 void emac_hal_set_speed(emac_hal_context_t *hal, uint32_t speed); 195 196 void emac_hal_set_duplex(emac_hal_context_t *hal, eth_duplex_t duplex); 197 198 void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable); 199 200 /** 201 * @brief Send MAC-CTRL frames to peer (EtherType=0x8808, opcode=0x0001, dest_addr=MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01)) 202 */ 203 void emac_hal_send_pause_frame(emac_hal_context_t *hal, bool enable); 204 205 bool emac_hal_is_mii_busy(emac_hal_context_t *hal); 206 207 void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write); 208 209 void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value); 210 211 uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal); 212 213 void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr); 214 215 /** 216 * @brief Starts EMAC Transmission & Reception 217 * 218 * @param hal EMAC HAL context infostructure 219 */ 220 void emac_hal_start(emac_hal_context_t *hal); 221 222 /** 223 * @brief Stops EMAC Transmission & Reception 224 * 225 * @param hal EMAC HAL context infostructure 226 * @return 227 * - ESP_OK: succeed 228 * - ESP_ERR_INVALID_STATE: previous frame transmission/reception is not completed. When this error occurs, 229 * wait and reapeat the EMAC stop again. 230 */ 231 esp_err_t emac_hal_stop(emac_hal_context_t *hal); 232 233 uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal); 234 235 uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length); 236 237 uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain, uint32_t *free_desc); 238 239 void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable); 240 241 uint32_t emac_hal_get_intr_enable_status(emac_hal_context_t *hal); 242 243 uint32_t emac_hal_get_intr_status(emac_hal_context_t *hal); 244 245 void emac_hal_clear_corresponding_intr(emac_hal_context_t *hal, uint32_t bits); 246 247 void emac_hal_clear_all_intr(emac_hal_context_t *hal); 248 249 #ifdef __cplusplus 250 } 251 #endif 252
