1 /****************************************************************************** 2 * @file rsi_rom_table_si91x.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 /** 31 * Includes 32 */ 33 #ifndef __RSI_ROM_TABLE_RS9116_H__ 34 #define __RSI_ROM_TABLE_RS9116_H__ 35 #include "rsi_ccp_user_config.h" 36 #if defined(A11_ROM) 37 #include <stdint.h> 38 #include "rsi_error.h" 39 #include "rsi_timers.h" 40 #include "rsi_ulpss_clk.h" 41 #include "rsi_pll.h" 42 #include "rsi_power_save.h" 43 #include "rsi_egpio.h" 44 #include "rsi_crc.h" 45 #include "rsi_ulpss_clk.h" 46 #include "rsi_qspi_proto.h" 47 #include "rsi_qspi.h" 48 #include "rsi_rng.h" 49 #include "rsi_gpdma.h" 50 #include "rsi_ct.h" 51 #include "rsi_timers.h" 52 #include "rsi_udma.h" 53 #include "rsi_reg_spi.h" 54 #include "rsi_processor_sensor.h" 55 #include "rsi_retention.h" 56 #include "rsi_temp_sensor.h" 57 #include "rsi_time_period.h" 58 #include "rsi_wwdt.h" 59 #include "rsi_ipmu.h" 60 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 61 #include "rsi_efuse.h" 62 #include "rsi_pwm.h" 63 #endif 64 #include "rsi_udma_wrapper.h" 65 #include "UDMA.h" 66 #include "USART.h" 67 #include "GSPI.h" 68 #include "SAI.h" 69 #include "I2C.h" 70 #include "SPI.h" 71 #ifdef __cplusplus 72 extern "C" { 73 #endif 74 /* @brief ROM indirect function structure */ 75 76 ///////////////////EGPIO////////////////////////// 77 typedef struct { 78 void (*egpio_set_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); 79 void (*egpio_set_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); 80 boolean_t (*egpio_get_pin)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 81 boolean_t (*egpio_get_dir)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 82 void (*egpio_pin_int_sel)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); 83 void (*egpio_set_int_fall_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); 84 void (*egpio_set_int_fall_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); 85 void (*egpio_set_int_rise_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); 86 void (*egpio_set_int_rise_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); 87 void (*egpio_set_int_low_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); 88 void (*egpio_int_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); 89 void (*egpio_int_un_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); 90 void (*egpio_set_int_low_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); 91 void (*egpio_set_int_high_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); 92 void (*egpio_set_int_high_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); 93 uint8_t (*egpio_get_int_stat)(const EGPIO_Type *pEGPIO, uint8_t intCh); 94 void (*egpio_int_clr)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); 95 void (*egpio_set_pin_mux)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux); 96 void (*egpio_ulp_soc_gpio_mode)(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); 97 void (*egpio_set_port_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 98 void (*egpio_set_port_un_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 99 void (*egpio_port_masked_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 100 void (*egpio_set_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 101 void (*egpio_port_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 102 void (*egpio_word_load)(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); 103 void (*egpio_clr_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 104 void (*egpio_toggle_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); 105 uint16_t (*egpio_get_port)(const EGPIO_Type *pEGPIO, uint8_t port); 106 void (*egpio_group_int_one_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 107 void (*egpio_group_int_one_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 108 void (*egpio_group_int_two_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 109 void (*egpio_group_int_mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); 110 void (*egpio_group_int_un_Mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); 111 void (*egpio_group_int_enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); 112 void (*egpio_group_int_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); 113 void (*egpio_group_int_level)(EGPIO_Type *pEGPIO, uint8_t grpInt); 114 void (*egpio_group_int_edge)(EGPIO_Type *pEGPIO, uint8_t grpInt); 115 void (*egpio_group_int_and)(EGPIO_Type *pEGPIO, uint8_t grpInt); 116 void (*egpio_group_int_or)(EGPIO_Type *pEGPIO, uint8_t grpInt); 117 uint32_t (*egpio_group_int_stat)(const EGPIO_Type *pEGPIO, uint8_t grpInt); 118 void (*egpio_group_int_wkeup_Enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); 119 void (*egpio_group_int_wkeup_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); 120 void (*egpio_group_int_clr)(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags); 121 void (*egpio_group_int_two_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); 122 void (*egpio_set_group_int_one_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); 123 void (*egpio_set_group_int_two_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); 124 void (*egpio_host_pads_gpio_mode_enable)(uint8_t u8GpioNum); 125 void (*egpio_host_pads_gpio_mode_disable)(uint8_t u8GpioNum); 126 void (*egpio_pad_selection_enable)(uint8_t padNum); 127 void (*egpio_pad_selection_disable)(uint8_t padNum); 128 void (*egpio_pad_receiver_enable)(uint8_t u8GpioNum); 129 void (*egpio_pad_receiver_disable)(uint8_t u8GpioNum); 130 void (*egpio_pad_sdio_connected)(void); 131 void (*egpio_pad_driver_disable_state)(uint8_t u8GpioNum, en_driver_state_t endstate); 132 void (*egpio_pad_driver_strength_select)(uint8_t u8GpioNum, en_driver_strength_select_t strength); 133 void (*egpio_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); 134 void (*egpio_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); 135 void (*egpio_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); 136 void (*egpio_ulp_pad_receiver_enable)(uint8_t u8GpioNum); 137 void (*egpio_ulp_pad_receiver_disable)(uint8_t u8GpioNum); 138 void (*egpio_ulp_pad_driver_disable_state)(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); 139 void (*egpio_ulp_pad_driver_strength_select)(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); 140 void (*egpio_ulp_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); 141 void (*egpio_ulp_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); 142 void (*egpio_ulp_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); 143 } ROM_EGPIO_API_T; 144 ///////////////////EGPIO END////////////////////////// 145 146 /** @brief CRC ROM indirect function structure */ 147 typedef PRE_PACK struct POST_PACK { 148 void (*crc_set_gen_control)(CRC_Type *pCRC); 149 uint32_t (*crc_get_gen_status)(CRC_Type *pCRC); 150 void (*crc_polynomial)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 151 uint32_t (*crc_polynomial_width)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 152 void (*crc_lfsr_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 153 uint32_t (*crc_use_swapped_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 154 uint32_t (*crc_set_data_width_type)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 155 uint32_t (*crc_set_fifo_thresholds)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 156 uint32_t (*crc_write_data)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams, uint32_t data); 157 uint32_t (*monitor_crc_calc)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); 158 void (*crc_lfsr_dynamic_write)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); 159 void (*crc_reset_fifo)(CRC_Type *pCRC); 160 uint32_t (*crc_get_fifo_status)(CRC_Type *pCRC); 161 } ROM_CRC_API_T; 162 //////////////CRC END///////////////////////////// 163 164 /** @brief RNG ROM indirect function structure */ 165 typedef PRE_PACK struct POST_PACK { 166 uint32_t (*rng_start)(HWRNG_Type *pRNG, uint8_t rngMode); 167 void (*rng_stop)(HWRNG_Type *pRNG); 168 void (*rng_get_bytes)(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes); 169 } ROM_RNG_API_T; 170 ///////////////RNG END////////////////// 171 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 172 /* @brief ROM indirect function structure */ 173 typedef PRE_PACK struct POST_PACK { 174 void (*efuse_enable)(EFUSE_Type *pstcEfuse); 175 void (*efuse_Disable)(EFUSE_Type *pstcEfuse); 176 uint8_t (*efuse_read_data)(EFUSE_Type *pstcEfuse); 177 void (*efuse_write_addr)(EFUSE_Type *pstcEfuse, uint16_t u16Addr); 178 rsi_error_t (*efuse_write_bit)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time); 179 rsi_error_t (*efuse_fsm_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); 180 rsi_error_t (*efuse_mem_map_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); 181 rsi_error_t (*efuse_mem_map_read_word)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk); 182 } ROM_EFUSE_API_T; 183 ///////////////EFUSE END////////////////// 184 #endif 185 typedef PRE_PACK struct POST_PACK { 186 void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); 187 void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); 188 uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 189 void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, 190 uint32_t flash_type, 191 spi_config_t *spi_config, 192 uint32_t cs_no); 193 void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, 194 uint32_t write_value, 195 spi_config_t *spi_config, 196 uint32_t wr_reg_delay_ms); 197 uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); 198 void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, 199 uint32_t reg_write_cmd, 200 uint32_t reg_write_value, 201 uint32_t cs_no, 202 uint32_t wr_reg_delay_ms); 203 void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, 204 uint32_t data_mode, 205 uint32_t cs_no, 206 uint32_t ddr_en, 207 uint32_t flash_type); 208 void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); 209 void (*qspi_manual_read)(qspi_reg_t *qspi_reg, 210 spi_config_t *spi_config, 211 uint32_t addr, 212 uint8_t *data, 213 uint32_t hsize, 214 uint32_t len_in_bytes, 215 uint32_t manual_udma_read, 216 void *udmaHandle, 217 void *gpdmaHandle); 218 void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); 219 void (*qspi_auto_read)(uint32_t cs_no, 220 uint32_t addr, 221 uint8_t *data, 222 uint32_t hsize, 223 uint32_t len_in_bytes, 224 spi_config_t *spi_config, 225 uint32_t dma_flags); 226 void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 227 void (*qspi_spi_init)(qspi_reg_t *qspi_reg, 228 spi_config_t *spi_config, 229 uint32_t flash_init_req, 230 uint32_t wr_reg_delay_ms, 231 uint8_t fifo_thrsld); 232 void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, 233 spi_config_t *spi_config, 234 uint32_t erase_cmd, 235 uint32_t blk_sec_addr, 236 uint32_t dis_hw_ctrl, 237 uint32_t wr_reg_delay_ms); 238 uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, 239 spi_config_t *spi_config, 240 uint32_t write_cmd, 241 uint32_t addr, 242 uint8_t *data, 243 uint32_t len_in_bytes, 244 uint16_t page_size, 245 uint32_t hsize, 246 uint32_t dis_hw_ctrl, 247 uint32_t wr_reg_delay_ms, 248 uint32_t check_en, 249 uint32_t udma_enable, 250 void *udmaHandle, 251 void *gpdmaHandle); 252 void (*qspi_spi_read)(qspi_reg_t *qspi_reg, 253 spi_config_t *spi_config, 254 uint32_t addr, 255 uint8_t *data, 256 uint32_t hsize, 257 uint32_t len_in_bytes, 258 uint32_t manual_udma_read, 259 void *udmaHandle, 260 void *gpdmaHandle); 261 void (*qspi_usleep)(uint32_t delay_us); //!< function ptr for halting processor for delay (us) specified 262 void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, 263 uint32_t protect, 264 uint32_t cs_no, 265 uint32_t num_prot_bytes, 266 uint32_t wr_reg_delay_ms); 267 #if defined(SLI_SI917) || defined(SLI_SI915) 268 #if defined(SLI_SI917B0) || defined(SLI_SI915) 269 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, 270 uint8_t mode, 271 uint32_t *key1, 272 uint32_t *key2, 273 uint32_t key_len, 274 uint32_t kh_enable); 275 #else 276 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); 277 #endif 278 #else 279 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); 280 #endif 281 void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); 282 void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); 283 void (*qspi_status_control_reg_write)(spi_config_t *spi_config, 284 qspi_reg_t *qspi_reg, 285 uint16_t write_command, 286 uint32_t addr, 287 uint16_t write_value, 288 uint32_t cs_no, 289 uint32_t wr_reg_delay_ms); 290 void (*qspi_flash_protection)(spi_config_t *spi_config, 291 qspi_reg_t *qspi_reg, 292 uint32_t protection, 293 uint32_t wr_reg_delay_ms); 294 void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); 295 void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); 296 void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); 297 } ROM_QSPI_API_T; 298 //////////////////////////QSPI END////////////////////////// 299 300 /** @brief TIMERS ROM indirect function structure */ 301 typedef PRE_PACK struct POST_PACK { 302 RSI_UDMA_HANDLE_T (*udma_init)(void *mem, const RSI_UDMA_INIT_T *pInit); 303 304 uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); 305 rsi_error_t (*udma_setup_channel_transfer)(RSI_UDMA_HANDLE_T pHandle, 306 const RSI_UDMA_CHA_CFG_T *pCfg, 307 RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, 308 void *pSrcAddr, 309 void *pDstAddr); 310 311 rsi_error_t (*udma_set_channel_scatter_gather_transfer)(RSI_UDMA_HANDLE_T pHandle, 312 uint8_t dmaCh, 313 uint32_t taskCount, 314 void *pTaskList, 315 uint32_t transferType); 316 317 uint32_t (*udma_get_channel_transfer_length)(RSI_UDMA_HANDLE_T pHandle, 318 const RSI_UDMA_CHA_CFG_T *pCfg, 319 RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); 320 321 rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); 322 323 void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); 324 325 void (*udma_interrupt_handler)(RSI_UDMA_HANDLE_T pHandle); 326 327 rsi_error_t (*udma_interrupt_enable)(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); 328 329 } ROM_UDMA_API_T; 330 331 //////////////////////////UDMA END////////////////////////// 332 333 //////////////////////////UDMA WRAPPERS ////////////////////////// 334 typedef PRE_PACK struct POST_PACK { 335 RSI_UDMA_HANDLE_T(*uDMAx_Initialize) 336 (const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); 337 int32_t (*uDMAx_Uninitialize)(const UDMA_RESOURCES *udma); 338 int32_t (*uDMAx_ChannelConfigure)(const UDMA_RESOURCES *udma, 339 uint8_t ch, 340 uint32_t src_addr, 341 uint32_t dest_addr, 342 uint32_t size, 343 RSI_UDMA_CHA_CONFIG_DATA_T control, 344 const RSI_UDMA_CHA_CFG_T *config, 345 UDMA_SignalEvent_t cb_event, 346 UDMA_Channel_Info *chnl_info, 347 RSI_UDMA_HANDLE_T udmaHandle); 348 int32_t (*uDMAx_ChannelEnable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); 349 int32_t (*uDMAx_DMAEnable)(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); 350 int32_t (*uDMAx_ChannelDisable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); 351 uint32_t (*uDMAx_ChannelGetCount)(uint8_t ch, 352 RSI_UDMA_CHA_CONFIG_DATA_T control, 353 RSI_UDMA_CHA_CFG_T config, 354 const UDMA_RESOURCES *udma, 355 RSI_UDMA_HANDLE_T udmaHandle); 356 void (*uDMAx_IRQHandler)(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); 357 358 } ROM_UDMA_WRAPPER_API_T; 359 //////////////////////////UDMA WRAPPERS END////////////////////////// 360 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 361 typedef PRE_PACK struct POST_PACK { 362 rsi_error_t (*mcpwm_counter_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); 363 364 rsi_error_t (*mcpwm_channel_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); 365 366 rsi_error_t (*mcpwm_start)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); 367 368 rsi_error_t (*mcpwm_stop)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); 369 370 rsi_error_t (*mcpwm_set_time_period)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal); 371 372 void (*mcpwm_special_event_trigger_config)(RSI_MCPWM_T *pMCPWM, 373 boolean_t svtDir, 374 RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig); 375 376 rsi_error_t (*mcpwm_dead_time_value_set)(RSI_MCPWM_T *pMCPWM, 377 RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig, 378 uint8_t chnlNum); 379 380 rsi_error_t (*mcpwm_period_control_config)(RSI_MCPWM_T *pMCPWM, 381 uint32_t postScale, 382 uint32_t preScale, 383 uint8_t chnlNum); 384 385 rsi_error_t (*mcpwm_fault_avalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); 386 387 rsi_error_t (*mcpwm_fault_bvalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); 388 389 rsi_error_t (*mcpwm_set_base_timer_mode)(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum); 390 391 rsi_error_t (*mcpwm_set_output_mode)(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum); 392 393 void (*mcpwm_set_output_polarity)(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH); 394 395 void (*mcpwm_interrupt_handler)(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack); 396 397 } ROM_MCPWM_API_T; 398 #endif 399 ////////////MCPWM END/////////////////////// 400 401 /* RPDMA Function Pointer Table */ 402 typedef PRE_PACK struct POST_PACK { 403 uint32_t (*gpdma_get_mem_size)(void); 404 405 RSI_GPDMA_HANDLE_T (*gpdma_init)(void *mem, const RSI_GPDMA_INIT_T *pInit); 406 407 void (*gpdma_register_callback)(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB); 408 409 rsi_error_t (*gpdma_abort_channel)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); 410 411 rsi_error_t (*gpdma_setup_channel)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 412 413 rsi_error_t (*gpdma_build_descriptors)(RSI_GPDMA_HANDLE_T pHandle, 414 RSI_GPDMA_DESC_T *pXferCfg, 415 RSI_GPDMA_DESC_T *pDesc, 416 RSI_GPDMA_DESC_T *pDescPrev); 417 418 rsi_error_t (*gpdma_setup_channelTransfer)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc); 419 420 void (*gpdma_interrupt_handler)(RSI_GPDMA_HANDLE_T pHandle); 421 422 void (*gpdma_deInit)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 423 424 rsi_error_t (*gpdma_dma_channel_trigger)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); 425 426 uint32_t (*gpdma_channel_is_enabled)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); 427 428 rsi_error_t (*gpdma_interrupt_disable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 429 430 rsi_error_t (*gpdma_interrupt_enable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 431 432 rsi_error_t (*gpdma_error_status_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 433 434 uint32_t (*gpdma_get_error_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 435 436 rsi_error_t (*gpdma_interrupt_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 437 438 uint32_t (*gpdma_interrupt_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); 439 440 } ROM_RPDMA_API_T; 441 ///////////////////////////GPDMA END///////////////////// 442 443 /** @brief TIMERS ROM indirect function structure */ 444 typedef PRE_PACK struct POST_PACK { 445 rsi_error_t (*timers_microsec_timer_config)(RSI_TIMERS_T *pTIMER, 446 uint8_t timerNum, 447 uint16_t integer, 448 uint8_t fractional, 449 uint8_t mode); 450 uint32_t (*timers_read_timer)(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir); 451 } ROM_TIMERS_API_T; 452 453 ////////////////////////////TIMERS END/////////////////////// 454 455 //USART 456 typedef PRE_PACK struct POST_PACK { 457 int32_t (*USART_Initialize)(ARM_USART_SignalEvent_t cb_event, 458 USART_RESOURCES *usart, 459 UDMA_RESOURCES *udma, 460 RSI_UDMA_DESC_T *UDMA_Table, 461 RSI_UDMA_HANDLE_T *udmaHandle, 462 uint32_t *mem); 463 int32_t (*USART_Uninitialize)(USART_RESOURCES *usart, UDMA_RESOURCES *udma); 464 int32_t (*USART_PowerControl)(ARM_POWER_STATE state, 465 USART_RESOURCES *usart, 466 UDMA_RESOURCES *udma, 467 RSI_UDMA_HANDLE_T udmaHandle); 468 int32_t (*USART_SetBaudrate)(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES *usart); 469 int32_t (*USART_Send_Data)(const void *data, 470 uint32_t num, 471 USART_RESOURCES *usart, 472 UDMA_RESOURCES *udma, 473 UDMA_Channel_Info *chnl_info, 474 RSI_UDMA_HANDLE_T udmaHandle); 475 int32_t (*USART_Receive_Data)(const void *data, 476 uint32_t num, 477 USART_RESOURCES *usart, 478 UDMA_RESOURCES *udma, 479 UDMA_Channel_Info *chnl_info, 480 RSI_UDMA_HANDLE_T udmaHandle); 481 int32_t (*USART_Transfer)(const void *data_out, 482 void *data_in, 483 uint32_t num, 484 USART_RESOURCES *usart, 485 UDMA_RESOURCES *udma, 486 UDMA_Channel_Info *chnl_info, 487 RSI_UDMA_HANDLE_T udmaHandle); 488 uint32_t (*USART_GetTxCount)(USART_RESOURCES *usart); 489 uint32_t (*USART_GetRxCount)(USART_RESOURCES *usart); 490 int32_t (*USART_Control)(uint32_t control, 491 uint32_t arg, 492 uint32_t baseClk, 493 USART_RESOURCES *usart, 494 UDMA_RESOURCES *udma, 495 RSI_UDMA_HANDLE_T udmaHandle); 496 ARM_USART_STATUS (*USART_GetStatus)(USART_RESOURCES *usart); 497 int32_t (*USART_SetModemControl)(ARM_USART_MODEM_CONTROL control, USART_RESOURCES *usart); 498 ARM_USART_MODEM_STATUS (*USART_GetModemStatus)(USART_RESOURCES *usart); 499 void (*UartIrqHandler)(USART_RESOURCES *usart); 500 void (*USART_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); 501 void (*USART_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); 502 } ROM_USART_API_T; 503 //////////////////////USART END//////////////////// 504 505 //GPSI 506 typedef PRE_PACK struct POST_PACK { 507 int32_t (*GSPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, 508 const GSPI_RESOURCES *gspi, 509 UDMA_RESOURCES *udma, 510 RSI_UDMA_DESC_T *UDMA_Table, 511 RSI_UDMA_HANDLE_T *udmaHandle, 512 uint32_t *mem); 513 int32_t (*GSPI_Uninitialize)(const GSPI_RESOURCES *gspi, UDMA_RESOURCES *udma); 514 int32_t (*GSPI_PowerControl)(ARM_POWER_STATE state, const GSPI_RESOURCES *gspi); 515 #if defined(SLI_SI917B0) || defined(SLI_SI915) 516 int32_t (*GSPI_Control)(uint32_t control, 517 uint32_t arg, 518 const GSPI_RESOURCES *gspi, 519 uint32_t base_clock, 520 uint8_t spi_slavenumber); 521 #else 522 int32_t (*GSPI_Control)(uint32_t control, uint32_t arg, const GSPI_RESOURCES *gspi, uint32_t base_clock); 523 #endif 524 int32_t (*GSPI_Send)(const void *data, 525 uint32_t num, 526 const GSPI_RESOURCES *gspi, 527 UDMA_RESOURCES *udma, 528 UDMA_Channel_Info *chnl_info, 529 RSI_UDMA_HANDLE_T udmaHandle); 530 int32_t (*GSPI_Receive)(void *data, 531 uint32_t num, 532 const GSPI_RESOURCES *gspi, 533 UDMA_RESOURCES *udma, 534 UDMA_Channel_Info *chnl_info, 535 RSI_UDMA_HANDLE_T udmaHandle); 536 int32_t (*GSPI_Transfer)(const void *data_out, 537 void *data_in, 538 uint32_t num, 539 const GSPI_RESOURCES *gspi, 540 UDMA_RESOURCES *udma, 541 UDMA_Channel_Info *chnl_info, 542 RSI_UDMA_HANDLE_T udmaHandle); 543 uint32_t (*GSPI_GetDataCount)(const GSPI_RESOURCES *gspi); 544 void (*GSPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); 545 void (*GSPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); 546 void (*GSPI_IRQHandler)(const GSPI_RESOURCES *gspi); 547 } ROM_GSPI_API_T; 548 ////////////////////////////GSPI END////////////////////////// 549 550 //i2s 551 typedef PRE_PACK struct POST_PACK { 552 int32_t (*I2S_Initialize)(ARM_SAI_SignalEvent_t cb_event, 553 I2S_RESOURCES *i2s, 554 UDMA_RESOURCES *udma, 555 RSI_UDMA_DESC_T *UDMA_Table, 556 RSI_UDMA_HANDLE_T *udmaHandle, 557 uint32_t *mem); 558 int32_t (*I2S_Uninitialize)(I2S_RESOURCES *i2s, UDMA_RESOURCES *udma); 559 int32_t (*I2S_PowerControl)(ARM_POWER_STATE state, 560 I2S_RESOURCES *i2s, 561 UDMA_RESOURCES *udma, 562 RSI_UDMA_HANDLE_T udmaHandle); 563 int32_t (*I2S_Send)(const void *data, 564 uint32_t num, 565 I2S_RESOURCES *i2s, 566 UDMA_RESOURCES *udma, 567 UDMA_Channel_Info *chnl_info, 568 RSI_UDMA_HANDLE_T udmaHandle); 569 int32_t (*I2S_Receive)(void *data, 570 uint32_t num, 571 I2S_RESOURCES *i2s, 572 UDMA_RESOURCES *udma, 573 UDMA_Channel_Info *chnl_info, 574 RSI_UDMA_HANDLE_T udmaHandle); 575 uint32_t (*I2S_GetTxCount)(I2S_RESOURCES *i2s); 576 uint32_t (*I2S_GetRxCount)(I2S_RESOURCES *i2s); 577 int32_t (*I2S_Control)(uint32_t control, 578 uint32_t arg1, 579 uint32_t arg2, 580 I2S_RESOURCES *i2s, 581 UDMA_RESOURCES *udma, 582 RSI_UDMA_HANDLE_T udmaHandle); 583 ARM_SAI_STATUS (*I2S_GetStatus)(I2S_RESOURCES *i2s); 584 void (*I2S_IRQHandler)(I2S_RESOURCES *i2s); 585 void (*I2S_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); 586 void (*I2S_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); 587 } ROM_I2S_API_T; 588 ////////////////////////////I2S END//////////////////////// 589 590 //I2C 591 typedef PRE_PACK struct POST_PACK { 592 int32_t (*I2Cx_Initialize)(ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c); 593 int32_t (*I2Cx_Uninitialize)(I2C_RESOURCES *i2c); 594 int32_t (*I2Cx_PowerControl)(ARM_POWER_STATE state, I2C_RESOURCES *i2c); 595 int32_t ( 596 *I2Cx_MasterTransmit)(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); 597 int32_t (*I2Cx_MasterReceive)(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); 598 int32_t (*I2Cx_SlaveTransmit)(const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); 599 int32_t (*I2Cx_SlaveReceive)(uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); 600 int32_t (*I2Cx_GetDataCount)(I2C_RESOURCES *i2c); 601 int32_t (*I2Cx_Control)(uint32_t control, uint32_t arg, I2C_RESOURCES *i2c, uint32_t clock); 602 ARM_I2C_STATUS (*I2Cx_GetStatus)(I2C_RESOURCES *i2c); 603 uint32_t (*I2Cx_MasterHandler)(I2C_RESOURCES *i2c); 604 uint32_t (*I2Cx_SlaveHandler)(I2C_RESOURCES *i2c); 605 void (*I2Cx_IRQHandler)(I2C_RESOURCES *i2c); 606 } ROM_I2C_API_T; 607 ///////////////////I2C END///////////////// 608 #if 0 609 typedef PRE_PACK struct POST_PACK 610 { 611 void (* rsi_arm_offset_f32_opt)(int32_t *pSrc, int32_t scale, int32_t *pDst,uint32_t length,uint16_t inBank, uint16_t outBank ); 612 613 void (* rsi_arm_offset_q7_opt)( q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); 614 615 void (* rsi_arm_offset_q15_opt)( q15_t *pSrc, q15_t scale, q15_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); 616 617 void (* rsi_arm_offset_q31_opt)( q31_t *pSrc, q31_t scale, q31_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); 618 619 void (* rsi_fim_scalar_sub_q7)(q7_t *pSrc,q7_t scale,q7_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); 620 621 void (* rsi_fim_scalar_sub_q31)(q31_t *pSrc,q31_t scale,q31_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); 622 623 void (* rsi_fim_scalar_sub_f32)( int32_t *pSrc, int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); 624 625 void (* rsi_arm_scale_f32_opt)( int32_t *pSrc,int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); 626 627 void (* rsi_arm_scale_q7_opt)( q7_t *pSrc,q7_t scaleFract,int8_t shift,q7_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); 628 629 void (* rsi_arm_scale_q15_opt)( q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); 630 631 void (* rsi_arm_scale_q31_opt)( q31_t * pSrc,q31_t scaleFract, int8_t shift,q31_t * pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); 632 633 void (* rsi_fim_scalar_mul_q15)(q15_t *pSrc,q15_t *scale,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank, uint16_t outBank ); 634 635 void (* rsi_arm_add_f32_opt)( int32_t *pSrcA, int32_t *pSrcB,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 636 637 void (* rsi_arm_add_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 638 639 void (* rsi_arm_add_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 640 641 void (* rsi_arm_add_q31_opt)( q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 642 643 void (* rsi_fim_vector_add_q15)(q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 644 645 void (* rsi_arm_sub_f32_opt)(int32_t *pSrcA, int32_t *pSrcB,int32_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 646 647 void (* rsi_arm_sub_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 648 649 void (* rsi_arm_sub_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 650 651 void (*rsi_arm_sub_q31_opt)( q31_t *pSrcA, q31_t *pSrcB,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 652 653 void (* rsi_fim_read_data)( uint32_t bank,uint32_t length,volatile void *pDst, uint8_t data_type,typ_data_t type_data); 654 655 void (* rsi_fim_vector_sub_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 656 657 void (* rsi_arm_mult_f32_opt)( int32_t *pIn1,int32_t *pIn2, uint32_t SatTruncRound,uint32_t length,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 658 659 void (* rsi_arm_mult_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 660 661 void (* rsi_arm_mult_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 662 663 void (* rsi_arm_mult_q31_opt)(q31_t *pSrcA,q31_t *pSrcB,q31_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 664 665 void (* rsi_fim_vector_mul_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 666 667 void (* rsi_arm_cmplx_mult_real_q15_opt)(q15_t *pSrcCmplx,q15_t *pSrcReal,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 668 669 void (* rsi_arm_cmplx_mult_cmplx_q15_opt)(q15_t * pSrcA,q15_t * pSrcB,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 670 671 void (* rsi_arm_cmplx_mag_squared_q15_opt)(q15_t *pSrc,q15_t *pDst,uint32_t numSamples,uint16_t inBank, uint16_t outBank); 672 673 void (* rsi_fim_absSqr_q7)( q7_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); 674 675 void (* rsi_fim_absSqr_q15)( q15_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); 676 677 void (* rsi_fim_absSqr_q31)( q31_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); 678 679 void (* rsi_fim_absSqr_f32)(int32_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); 680 681 rsi_error_t (* rsi_arm_mat_mult_f32_opt)( const arm_matrix_instance_f32_opt *pSrcA, 682 const arm_matrix_instance_f32_opt *pSrcB,arm_matrix_instance_f32_opt *pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 683 684 rsi_error_t (* rsi_arm_mat_mult_q31_opt)( const arm_matrix_instance_q31_opt * pSrcA,const arm_matrix_instance_q31_opt * pSrcB, 685 arm_matrix_instance_q31_opt * pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 686 687 rsi_error_t (* rsi_arm_mat_mult_q15_opt)( const arm_matrix_instance_q15_opt * pSrcA, 688 const arm_matrix_instance_q15_opt * pSrcB,arm_matrix_instance_q15_opt * pDst,q15_t * pState 689 ,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 690 691 void (* rsi_arm_fir_init_f32_opt)( arm_fir_instance_f32_opt *S, uint16_t numTaps,int32_t *pCoeffs, int32_t *pState, 692 uint32_t blockSize); 693 694 void (* rsi_arm_fir_f32_opt)( arm_fir_instance_f32_opt *S, int32_t *pSrc, int32_t *pDst, 695 uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 696 697 void (* rsi_arm_fir_init_q31_opt)( arm_fir_instance_q31_opt *S,uint16_t numTaps,q31_t *pCoeffs, 698 q31_t *pState, uint32_t blockSize); 699 700 void (* rsi_arm_fir_q31_opt)( arm_fir_instance_q31_opt *S, q31_t *pSrc,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 701 702 void (* rsi_arm_fir_init_q15_opt)( arm_fir_instance_q15_opt *S,uint16_t numTaps,q15_t *pCoeffs, 703 q15_t *pState, uint32_t blockSize); 704 705 void (* rsi_arm_fir_q15_opt)( arm_fir_instance_q15_opt *S, q15_t *pSrc,q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 706 707 void (* rsi_arm_fir_init_q7_opt)( arm_fir_instance_q7_opt *S,uint16_t numTaps,q7_t *pCoeffs, 708 q7_t *pState, uint32_t blockSize); 709 710 void (* rsi_arm_fir_q7_opt)( arm_fir_instance_q7_opt *S, q7_t *pSrc,q7_t *pDst, 711 uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 712 713 void (* rsi_fim_interrupt_handler)(volatile FIM_Type *ptFim); 714 715 void (* rsi_arm_fir_interpolate_f32_opt)( const arm_fir_interpolate_instance_f32_opt * S, int32_t * pSrc, 716 int32_t * pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 717 718 arm_status (* rsi_arm_fir_interpolate_init_f32_opt)( arm_fir_interpolate_instance_f32_opt * S, 719 uint8_t L, uint16_t numTaps, int32_t * pCoeffs, 720 int32_t * pState,uint32_t blockSize ); 721 722 arm_status (* rsi_arm_fir_interpolate_init_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,uint8_t L, 723 uint16_t numTaps,q15_t * pCoeffs,q15_t * pState, 724 uint32_t blockSize ); 725 726 arm_status (* rsi_arm_fir_interpolate_init_q31_opt)( arm_fir_interpolate_instance_q31_opt *S, uint8_t L, 727 uint16_t numTaps,q31_t * pCoeffs, q31_t * pState, 728 uint32_t blockSize ); 729 730 void (* rsi_arm_fir_interpolate_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,q15_t * pSrc,q15_t *pDst, 731 uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 732 733 734 void (* rsi_arm_fir_interpolate_q31_opt)( const arm_fir_interpolate_instance_q31_opt * S, q31_t * pSrc, 735 q31_t * pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); 736 }ROM_FIM_API_T; 737 738 /////////////////////FIM END////////////////////// 739 #endif 740 typedef PRE_PACK struct POST_PACK { 741 void (*ct_ocu_high_Low_toggle_select)(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel); 742 rsi_error_t (*ct_wfg_control_config)(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg); 743 rsi_error_t (*ct_ocu_control)(RSI_CT_T *pCT, 744 boolean_t counterNum, 745 boolean_t dmaEn, 746 OCU_PARAMS_T *pOCUparams, 747 RSI_CT_CALLBACK_T *pCB); 748 749 rsi_error_t (*ct_wfg_comapre_value_set)(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams); 750 } ROM_CT_API_T; 751 752 ///////////////////////CT END/////////////////////////////////// 753 /** @brief SPI master ROM indirect function structure */ 754 typedef PRE_PACK struct POST_PACK { 755 void (*ps_clr_wkp_up_status)(uint32_t wakeUpIntrClear); 756 void (*ps_bg_ldo_config)(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode); 757 void (*ps_configure_trim_values)(uint16_t lf_ro_trim, 758 uint16_t lf_rc_trim, 759 uint16_t hf_ro_trim, 760 uint16_t hf_rc_trim, 761 uint16_t bg_ptat_trim, 762 uint16_t bg_trim); 763 void (*ps_wireless_shutdown)(void); 764 uint32_t (*RSI_SelectTaBootOption)(uint32_t option); 765 void (*RSI_GotoSleepWithRetention)(uint32_t stack_address, 766 uint32_t jump_cb_address, 767 uint32_t vector_offset, 768 uint32_t mode); 769 void (*RSI_WakeupWirelessProcessor)(void); 770 } ROM_PWR_API_T; 771 ///////////////////////POWERSAVE END/////////////////////////// 772 773 typedef PRE_PACK struct POST_PACK { 774 rsi_error_t (*ulpss_clock_config)(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); 775 776 rsi_error_t (*ulpss_ulp_peri_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 777 778 rsi_error_t (*ulpss_ulp_peri_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 779 780 rsi_error_t (*ulpss_ulp_dyn_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 781 782 rsi_error_t (*ulpss_ulp_dyn_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); 783 784 rsi_error_t (*ulpss_ulp_ssi_clk_config)(ULPCLK_Type *pULPCLK, 785 CLK_ENABLE_T clkType, 786 ULP_SSI_CLK_SELECT_T clkSource, 787 uint16_t divFactor); 788 789 rsi_error_t (*ulpss_ulp_i2s_clk_config)(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); 790 791 rsi_error_t (*ulpss_ulp_uar_clk_config)(ULPCLK_Type *pULPCLK, 792 CLK_ENABLE_T clkType, 793 boolean_t bFrClkSel, 794 ULP_UART_CLK_SELECT_T clkSource, 795 uint16_t divFactor); 796 797 rsi_error_t (*ulpss_time_clk_disable)(ULPCLK_Type *pULPCLK); 798 rsi_error_t (*ulpss_time_clk_config)(ULPCLK_Type *pULPCLK, 799 CLK_ENABLE_T clkType, 800 boolean_t bTmrSync, 801 ULP_TIMER_CLK_SELECT_T clkSource, 802 uint8_t skipSwitchTime); 803 804 rsi_error_t (*ulpss_aux_clk_config)(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); 805 806 rsi_error_t (*ulpss_vad_clk_config)(ULPCLK_Type *pULPCLK, 807 ULP_VAD_CLK_SELECT_T clkSource, 808 ULP_VAD_FCLK_SELECT_T FclkSource, 809 uint16_t divFactor); 810 811 rsi_error_t (*ulpss_touch_clk_config)(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); 812 813 rsi_error_t (*ulpss_slp_sensor_clk_config)(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); 814 815 rsi_error_t (*ulpss_peripheral_enable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); 816 817 rsi_error_t (*ulpss_peripheral_disable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); 818 819 } ROM_ULPSS_CLK_API_T; 820 821 ////////////////////////////ULPSS CLOCKS END///////////////////////////////// 822 823 typedef PRE_PACK struct POST_PACK { 824 boolean_t (*clk_check_pll_lock)(PLL_TYPE_T pllType); 825 rsi_error_t (*clk_soc_pll_clk_enable)(boolean_t clkEnable); 826 rsi_error_t (*clk_set_soc_pll_freq)(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); 827 rsi_error_t (*clk_soc_pll_set_freq_div)(const M4CLK_Type *pCLK, 828 boolean_t clk_en, 829 uint16_t divFactor, 830 uint16_t nFactor, 831 uint16_t mFactor, 832 uint16_t fcwF, 833 uint16_t dcoFixSel, 834 uint16_t ldoProg); 835 rsi_error_t (*clk_soc_pll_clk_set)(const M4CLK_Type *pCLK); 836 rsi_error_t (*clk_soc_pll_clk_bypass_enable)(boolean_t clkEnable); 837 rsi_error_t (*clk_soc_pll_clk_reset)(void); 838 rsi_error_t (*clk_soc_pll_pd_enable)(boolean_t en); 839 rsi_error_t (*clk_soc_pll_turn_off)(void); 840 rsi_error_t (*clk_soc_pll_turn_on)(void); 841 rsi_error_t (*clk_i2s_pll_clk_enable)(boolean_t clkEnable); 842 rsi_error_t (*clk_i2s_pll_clk_bypass_enable)(boolean_t clkEnable); 843 rsi_error_t (*clk_i2s_pll_pd_enable)(boolean_t en); 844 rsi_error_t (*clk_i2s_pll_turn_off)(void); 845 rsi_error_t (*clk_i2s_pll_turn_on)(void); 846 rsi_error_t (*clk_set_i2s_pll_freq)(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); 847 rsi_error_t (*clk_i2s_pll_set_freq_div)(const M4CLK_Type *pCLK, 848 uint16_t u16DivFactor1, 849 uint16_t u16DivFactor2, 850 uint16_t nFactor, 851 uint16_t mFactor, 852 uint16_t fcwF); 853 rsi_error_t (*clk_i2s_pll_clk_set)(const M4CLK_Type *pCLK); 854 rsi_error_t (*clk_i2s_pll_clk_reset)(void); 855 rsi_error_t (*clk_intf_pll_clk_enable)(boolean_t clkEnable); 856 rsi_error_t (*clk_intf_pll_pd_enable)(boolean_t en); 857 rsi_error_t (*clk_intf_pll_turn_off)(void); 858 rsi_error_t (*clk_set_intf_pll_freq)(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); 859 rsi_error_t (*clk_intf_pll_set_freq_div)(const M4CLK_Type *pCLK, 860 boolean_t clk_en, 861 uint16_t divFactor, 862 uint16_t nFactor, 863 uint16_t mFactor, 864 uint16_t fcwF, 865 uint16_t dcoFixSel, 866 uint16_t ldoProg); 867 rsi_error_t (*clk_intf_pll_clk_bypass_enable)(boolean_t clkEnable); 868 rsi_error_t (*clk_intf_pll_turn_on)(void); 869 rsi_error_t (*clk_intf_pll_clk_reset)(void); 870 rsi_error_t (*clk_intf_pll_clk_set)(const M4CLK_Type *pCLK); 871 rsi_error_t (*clk_peripheral_clk_enable1)(M4CLK_Type *pCLK, uint32_t flags); 872 rsi_error_t (*clk_peripheral_clk_disable1)(M4CLK_Type *pCLK, uint32_t flags); 873 rsi_error_t (*clk_peripheral_clk_enable2)(M4CLK_Type *pCLK, uint32_t flags); 874 rsi_error_t (*clk_peripheral_clk_disable2)(M4CLK_Type *pCLK, uint32_t flags); 875 rsi_error_t (*clk_peripheral_clk_enable3)(M4CLK_Type *pCLK, uint32_t flags); 876 rsi_error_t (*clk_peripheral_clk_disable3)(M4CLK_Type *pCLK, uint32_t flags); 877 rsi_error_t (*clk_dynamic_clk_gate_disable)(M4CLK_Type *pCLK, uint32_t flags); 878 rsi_error_t (*clk_dynamic_clk_gate_disable2)(M4CLK_Type *pCLK, uint32_t flags); 879 rsi_error_t (*clk_dynamic_clk_gate_enable)(M4CLK_Type *pCLK, uint32_t flags); 880 rsi_error_t (*clk_dynamic_clk_gate_enable2)(M4CLK_Type *pCLK, uint32_t flags); 881 rsi_error_t (*ulpss_enable_ref_clks)(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn); 882 rsi_error_t (*ulpss_disable_ref_clks)(REF_CLK_ENABLE_T clk_type); 883 rsi_error_t (*clk_qspi_clk_config)(M4CLK_Type *pCLK, 884 QSPI_CLK_SRC_SEL_T clkSource, 885 boolean_t swalloEn, 886 boolean_t OddDivEn, 887 uint32_t divFactor); 888 rsi_error_t (*clk_usart_clk_config)(M4CLK_Type *pCLK, 889 CLK_ENABLE_T clkType, 890 boolean_t FracDivEn, 891 EN_USART_T EN_USART_T, 892 USART_CLK_SRC_SEL_T clkSource, 893 uint32_t divFactor); 894 rsi_error_t (*clk_ssi_mst_clk_config)(M4CLK_Type *pCLK, 895 CLK_ENABLE_T clkType, 896 SSI_MST_CLK_SRC_SEL_T clkSource, 897 uint32_t divFactor); 898 #if !defined(SLI_SI917) && !defined(SLI_SI915) 899 rsi_error_t (*clk_sd_mem_clk_config)(M4CLK_Type *pCLK, 900 boolean_t swalloEn, 901 SDMEM_CLK_SRC_SEL_T clkSource, 902 uint32_t divFactor); 903 #endif 904 rsi_error_t (*clk_ct_clk_config)(M4CLK_Type *pCLK, 905 CT_CLK_SRC_SEL_T clkSource, 906 uint32_t divFactor, 907 CLK_ENABLE_T clkType); 908 #if !defined(SLI_SI917) && !defined(SLI_SI915) 909 rsi_error_t (*clk_cci_clk_config)(M4CLK_Type *pCLK, 910 CCI_CLK_SRC_SEL_T clkSource, 911 uint32_t divFactor, 912 CLK_ENABLE_T clkType); 913 #endif 914 rsi_error_t (*clk_i2s_clk_config)(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor); 915 rsi_error_t (*clk_mcu_clk_cut_config)(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor); 916 #if !defined(SLI_SI917) && !defined(SLI_SI915) 917 rsi_error_t (*clk_can_clk_config)(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType); 918 rsi_error_t (*clk_ethernet_clk_config)(M4CLK_Type *pCLK, 919 boolean_t swalloEn, 920 ETHERNET_CLK_SRC_SEL_T clkSource, 921 uint32_t divFactor); 922 #endif 923 rsi_error_t (*clk_m4_soc_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); 924 rsi_error_t (*clk_qspi_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor); 925 rsi_error_t (*clk_ct_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); 926 rsi_error_t (*clk_ssi_mst_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); 927 #if !defined(SLI_SI917) && !defined(SLI_SI915) 928 rsi_error_t (*clk_cci_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); 929 #endif 930 rsi_error_t (*clk_i2s_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); 931 #if !defined(SLI_SI917) && !defined(SLI_SI915) 932 rsi_error_t (*clk_sd_mem_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor); 933 #endif 934 rsi_error_t (*clk_usart_clk_div)(M4CLK_Type *pCLK, EN_USART_T EN_USART_T, uint8_t u8FracDivEn, uint32_t divFactor); 935 uint32_t (*clk_slp_clk_calib_config)(M4CLK_Type *pCLK, uint8_t clkCycles); 936 rsi_error_t (*clk_gspi_clk_config)(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel); 937 rsi_error_t (*clk_slp_clk_config)(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc); 938 rsi_error_t (*clk_i2c_clk_config)(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C); 939 rsi_error_t (*clk_xtal_clk_config)(uint8_t xtalPin); 940 #if !defined(SLI_SI917) && !defined(SLI_SI915) 941 rsi_error_t (*clk_usb_clk_config)(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor); 942 #endif 943 rsi_error_t (*clk_peripheral_clk_enable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); 944 rsi_error_t (*clk_peripheral_clk_disable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module); 945 void (*clk_config_pll_lock)(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit); 946 void (*clk_config_pll_ref_clk)(uint8_t ref_clk_src); 947 #if defined(SLI_SI917B0) || defined(SLI_SI915) 948 rsi_error_t (*clk_qspi_2_clk_config)(M4CLK_Type *pCLK, 949 QSPI_CLK_SRC_SEL_T clkSource, 950 boolean_t swalloEn, 951 boolean_t OddDivEn, 952 uint32_t divFactor); 953 #endif 954 } ROM_M4SS_CLK_API_T; 955 956 //////////////////////////M4 CLOCKS END/////////////////////// 957 958 ///////////////SSI///////////////////////////////// 959 typedef PRE_PACK struct POST_PACK { 960 int32_t (*SPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, 961 const SPI_RESOURCES *spi, 962 UDMA_RESOURCES *udma, 963 RSI_UDMA_DESC_T *UDMA_Table, 964 RSI_UDMA_HANDLE_T *udmaHandle, 965 uint32_t *mem); 966 int32_t (*SPI_Uninitialize)(const SPI_RESOURCES *spi, UDMA_RESOURCES *udma); 967 int32_t (*SPI_PowerControl)(ARM_POWER_STATE state, const SPI_RESOURCES *spi); 968 int32_t (*SPI_Send)(const void *data, 969 uint32_t num, 970 const SPI_RESOURCES *spi, 971 UDMA_RESOURCES *udma, 972 UDMA_Channel_Info *chnl_info, 973 RSI_UDMA_HANDLE_T udmaHandle); 974 int32_t (*SPI_Receive)(void *data, 975 uint32_t num, 976 const SPI_RESOURCES *spi, 977 UDMA_RESOURCES *udma, 978 UDMA_Channel_Info *chnl_info, 979 RSI_UDMA_HANDLE_T udmaHandle); 980 int32_t (*SPI_Transfer)(const void *data_out, 981 void *data_in, 982 uint32_t num, 983 const SPI_RESOURCES *spi, 984 UDMA_RESOURCES *udma, 985 UDMA_Channel_Info *chnl_info, 986 RSI_UDMA_HANDLE_T udmaHandle); 987 uint32_t (*SPI_GetDataCount)(const SPI_RESOURCES *spi); 988 #if defined(SLI_SI917B0) || defined(SLI_SI915) 989 int32_t (*SPI_Control)(uint32_t control, 990 uint32_t arg, 991 const SPI_RESOURCES *spi, 992 uint32_t base_clock, 993 uint8_t spi_slavenumber); 994 #else 995 int32_t (*SPI_Control)(uint32_t control, uint32_t arg, const SPI_RESOURCES *spi, uint32_t base_clock); 996 #endif 997 ARM_SPI_STATUS (*SPI_GetStatus)(const SPI_RESOURCES *spi); 998 void (*SPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); 999 void (*SPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); 1000 void (*SPI_IRQHandler)(const SPI_RESOURCES *spi); 1001 } ROM_SSI_API_T; 1002 //////////////////SSI END////////////////////////// 1003 1004 typedef struct { 1005 const ROM_EGPIO_API_T *pEGPIOROM; /*!< EGPIO driver API function table base address */ 1006 const ROM_TIMERS_API_T *pTIMERSROM; /*!< TIMERS driver API function table base address */ 1007 const ROM_UDMA_API_T *pUDMAROM; /*!< UDMA driver API function table base address */ 1008 const ROM_UDMA_WRAPPER_API_T *pUDMAWRAPPERROM; 1009 const ROM_CT_API_T *pCTROM; /*!< SCT driver API function table base address */ 1010 const ROM_RPDMA_API_T *pRPDMAROM; 1011 const ROM_PWR_API_T *pPWR; 1012 const ROM_M4SS_CLK_API_T *pM4SSCLK; 1013 const ROM_ULPSS_CLK_API_T *pULPSSCLK; 1014 const ROM_QSPI_API_T *pQSPIROM; 1015 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 1016 const ROM_EFUSE_API_T *pEFUSEROM; 1017 #endif 1018 const ROM_CRC_API_T *pCRCROM; 1019 const ROM_RNG_API_T *pRNGROM; 1020 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 1021 const ROM_MCPWM_API_T *pMCPWMROM; 1022 #endif 1023 const ROM_USART_API_T *pUSARTROM; 1024 const ROM_GSPI_API_T *pGSPIROM; 1025 const ROM_I2S_API_T *pI2SROM; 1026 const ROM_I2C_API_T *pI2CROM; 1027 #ifdef CHIP_9118 1028 const struct ROM_WL_API_S *pWLROM; 1029 #endif 1030 #if defined(SLI_SI917) || defined(SLI_SI915) 1031 const ROM_SSI_API_T *pSSIROM; 1032 #endif 1033 } RSI_ROM_API_T; 1034 1035 /*ROM base address */ 1036 #define RSI_ROM_API_BASE_LOC (0x00300100) 1037 1038 #define RSI_ROM_API ((RSI_ROM_API_T *)RSI_ROM_API_BASE_LOC) 1039 /* Pointer to EGPIO peripheral driver functions in ROM */ 1040 #define ROMAPI_EGPIO_API ((RSI_ROM_API)->pEGPIOROM) 1041 1042 /* Pointer to Timers peripheral driver functions in ROM */ 1043 #define ROMAPI_TIMER_API ((RSI_ROM_API)->pTIMERSROM) 1044 1045 /* Pointer to UDMA peripheral driver functions in ROM */ 1046 #define ROMAPI_UDMA_API ((RSI_ROM_API)->pUDMAROM) 1047 1048 #define ROMAPI_UDMA_WRAPPER_API ((RSI_ROM_API)->pUDMAWRAPPERROM) 1049 1050 /* Pointer to SCT peripheral driver functions in ROM */ 1051 #define ROMAPI_CT_API ((RSI_ROM_API)->pCTROM) 1052 1053 /* Pointer to RPDMA peripheral driver functions in ROM */ 1054 #define ROMAPI_GPDMA_API ((RSI_ROM_API)->pRPDMAROM) 1055 1056 /* Pointer to POWER driver functions in ROM */ 1057 #define ROMAPI_PWR_API ((RSI_ROM_API)->pPWR) 1058 1059 /* Pointer to M4SS CLOCKS driver functions in ROM */ 1060 #define ROMAPI_M4SS_CLK_API ((RSI_ROM_API)->pM4SSCLK) 1061 1062 /*ULP clocks*/ 1063 #define ROMAPI_ULPSS_CLK_API ((RSI_ROM_API)->pULPSSCLK) 1064 1065 /* Pointer to QSPI peripheral driver functions in ROM */ 1066 #define ROMAPI_QSPI_API ((RSI_ROM_API)->pQSPIROM) 1067 1068 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 1069 /* Pointer to EFUSE driver functions in ROM */ 1070 #define ROMAPI_EFUSE_API ((RSI_ROM_API)->pEFUSEROM) 1071 #endif 1072 1073 /* Pointer to CRC peripheral driver functions in ROM */ 1074 #define ROMAPI_CRC_API ((RSI_ROM_API)->pCRCROM) 1075 1076 /* Pointer to RNG peripheral driver functions in ROM */ 1077 #define ROMAPI_RNG_API ((RSI_ROM_API)->pRNGROM) 1078 1079 #if !defined(SLI_SI917B0) && !defined(SLI_SI915) 1080 /* Pointer to MCPWM peripheral driver functions in ROM */ 1081 #define ROMAPI_MCPWM_API ((RSI_ROM_API)->pMCPWMROM) 1082 #endif 1083 1084 /* Pointer to USART peripheral driver functions in ROM */ 1085 #define ROMAPI_USART_API ((RSI_ROM_API)->pUSARTROM) 1086 1087 /* Pointer to GSPI peripheral driver functions in ROM */ 1088 #define ROMAPI_GSPI_API ((RSI_ROM_API)->pGSPIROM) 1089 1090 /* Pointer to I2S peripheral driver functions in ROM */ 1091 #define ROMAPI_I2S_API ((RSI_ROM_API)->pI2SROM) 1092 1093 /* Pointer to I2C peripheral driver functions in ROM */ 1094 #define ROMAPI_I2C_API ((RSI_ROM_API)->pI2CROM) 1095 1096 #ifdef CHIP_9118 1097 /* Pointer to WIRELESS driver functions in ROM */ 1098 #define ROMAPI_WL ((RSI_ROM_API)->pWLROM) 1099 #endif 1100 1101 #if defined(SLI_SI917) || defined(SLI_SI915) 1102 /* Pointer to SSI driver functions in ROM */ 1103 #define ROMAPI_SSI_API ((RSI_ROM_API)->pSSIROM) 1104 #endif 1105 1106 #ifdef __cplusplus 1107 } 1108 #endif 1109 1110 #endif 1111 1112 #endif /* __RSI_ROM_TABLE_RS9116_H__ */ 1113
