1 // SPDX-License-Identifier: BSD-3-Clause
2 //
3 // Copyright(c) 2017-2021 Intel Corporation. All rights reserved.
4 //
5 // Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
6
7 #include <sof/drivers/dmic.h>
8 #include <sof/math/numbers.h>
9 #include <ipc/dai.h>
10 #include <ipc/dai-intel.h>
11 #include <stdint.h>
12
13 /* Decimation filter struct */
14 #include <sof/audio/coefficients/pdm_decim/pdm_decim_fir.h>
15
16 /* Decimation filters */
17 #include <sof/audio/coefficients/pdm_decim/pdm_decim_table.h>
18
19 /* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
20 static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3};
21 static const uint32_t coef_base_a[4] = {PDM0_COEFFICIENT_A, PDM1_COEFFICIENT_A,
22 PDM2_COEFFICIENT_A, PDM3_COEFFICIENT_A};
23 static const uint32_t coef_base_b[4] = {PDM0_COEFFICIENT_B, PDM1_COEFFICIENT_B,
24 PDM2_COEFFICIENT_B, PDM3_COEFFICIENT_B};
25
26 /* This function returns a raw list of potential microphone clock and decimation
27 * modes for achieving requested sample rates. The search is constrained by
28 * decimation HW capabililies and setup parameters. The parameters such as
29 * microphone clock min/max and duty cycle requirements need be checked from
30 * used microphone component datasheet.
31 */
find_modes(struct dai * dai,struct decim_modes * modes,uint32_t fs,int di)32 static void find_modes(struct dai *dai,
33 struct decim_modes *modes, uint32_t fs, int di)
34 {
35 struct dmic_pdata *dmic = dai_get_drvdata(dai);
36 int clkdiv_min;
37 int clkdiv_max;
38 int clkdiv;
39 int c1;
40 int du_min;
41 int du_max;
42 int pdmclk;
43 int osr;
44 int mfir;
45 int mcic;
46 int ioclk_test;
47 int osr_min = DMIC_MIN_OSR;
48 int j;
49 int i = 0;
50
51 /* Defaults, empty result */
52 modes->num_of_modes = 0;
53
54 /* The FIFO is not requested if sample rate is set to zero. Just
55 * return in such case with num_of_modes as zero.
56 */
57 if (fs == 0)
58 return;
59
60 /* Override DMIC_MIN_OSR for very high sample rates, use as minimum
61 * the nominal clock for the high rates.
62 */
63 if (fs >= DMIC_HIGH_RATE_MIN_FS)
64 osr_min = DMIC_HIGH_RATE_OSR_MIN;
65
66 /* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
67 if (dmic->global->prm[di].pdmclk_max < DMIC_HW_PDM_CLK_MIN ||
68 dmic->global->prm[di].pdmclk_max > DMIC_HW_IOCLK / 2) {
69 dai_err(dai, "find_modes(): pdm clock max not in range");
70 return;
71 }
72 if (dmic->global->prm[di].pdmclk_min < DMIC_HW_PDM_CLK_MIN ||
73 dmic->global->prm[di].pdmclk_min > dmic->global->prm[di].pdmclk_max) {
74 dai_err(dai, "find_modes(): pdm clock min not in range");
75 return;
76 }
77
78 /* Check for sane duty cycle */
79 if (dmic->global->prm[di].duty_min > dmic->global->prm[di].duty_max) {
80 dai_err(dai, "find_modes(): duty cycle min > max");
81 return;
82 }
83 if (dmic->global->prm[di].duty_min < DMIC_HW_DUTY_MIN ||
84 dmic->global->prm[di].duty_min > DMIC_HW_DUTY_MAX) {
85 dai_err(dai, "find_modes(): pdm clock min not in range");
86 return;
87 }
88 if (dmic->global->prm[di].duty_max < DMIC_HW_DUTY_MIN ||
89 dmic->global->prm[di].duty_max > DMIC_HW_DUTY_MAX) {
90 dai_err(dai, "find_modes(): pdm clock max not in range");
91 return;
92 }
93
94 /* Min and max clock dividers */
95 clkdiv_min = ceil_divide(DMIC_HW_IOCLK, dmic->global->prm[di].pdmclk_max);
96 clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN);
97 clkdiv_max = DMIC_HW_IOCLK / dmic->global->prm[di].pdmclk_min;
98
99 /* Loop possible clock dividers and check based on resulting
100 * oversampling ratio that CIC and FIR decimation ratios are
101 * feasible. The ratios need to be integers. Also the mic clock
102 * duty cycle need to be within limits.
103 */
104 for (clkdiv = clkdiv_min; clkdiv <= clkdiv_max; clkdiv++) {
105 /* Calculate duty cycle for this clock divider. Note that
106 * odd dividers cause non-50% duty cycle.
107 */
108 c1 = clkdiv >> 1;
109 du_min = 100 * c1 / clkdiv;
110 du_max = 100 - du_min;
111
112 /* Calculate PDM clock rate and oversampling ratio. */
113 pdmclk = DMIC_HW_IOCLK / clkdiv;
114 osr = pdmclk / fs;
115
116 /* Check that OSR constraints is met and clock duty cycle does
117 * not exceed microphone specification. If exceed proceed to
118 * next clkdiv.
119 */
120 if (osr < osr_min || du_min < dmic->global->prm[di].duty_min ||
121 du_max > dmic->global->prm[di].duty_max)
122 continue;
123
124 /* Loop FIR decimation factors candidates. If the
125 * integer divided decimation factors and clock dividers
126 * as multiplied with sample rate match the IO clock
127 * rate the division was exact and such decimation mode
128 * is possible. Then check that CIC decimation constraints
129 * are met. The passed decimation modes are added to array.
130 */
131 for (j = 0; fir_list[j]; j++) {
132 mfir = fir_list[j]->decim_factor;
133
134 /* Skip if previous decimation factor was the same */
135 if (j > 1 && fir_list[j - 1]->decim_factor == mfir)
136 continue;
137
138 mcic = osr / mfir;
139 ioclk_test = fs * mfir * mcic * clkdiv;
140
141 if (ioclk_test == DMIC_HW_IOCLK &&
142 mcic >= DMIC_HW_CIC_DECIM_MIN &&
143 mcic <= DMIC_HW_CIC_DECIM_MAX &&
144 i < DMIC_MAX_MODES) {
145 modes->clkdiv[i] = clkdiv;
146 modes->mcic[i] = mcic;
147 modes->mfir[i] = mfir;
148 i++;
149 }
150 }
151 }
152
153 modes->num_of_modes = i;
154 }
155
156 /* The previous raw modes list contains sane configuration possibilities. When
157 * there is request for both FIFOs A and B operation this function returns
158 * list of compatible settings.
159 */
match_modes(struct matched_modes * c,struct decim_modes * a,struct decim_modes * b)160 static void match_modes(struct matched_modes *c, struct decim_modes *a,
161 struct decim_modes *b)
162 {
163 int16_t idx[DMIC_MAX_MODES];
164 int idx_length;
165 int i;
166 int n;
167 int m;
168
169 /* Check if previous search got results. */
170 c->num_of_modes = 0;
171 if (a->num_of_modes == 0 && b->num_of_modes == 0) {
172 /* Nothing to do */
173 return;
174 }
175
176 /* Ensure that num_of_modes is sane. */
177 if (a->num_of_modes > DMIC_MAX_MODES ||
178 b->num_of_modes > DMIC_MAX_MODES)
179 return;
180
181 /* Check for request only for FIFO A or B. In such case pass list for
182 * A or B as such.
183 */
184 if (b->num_of_modes == 0) {
185 c->num_of_modes = a->num_of_modes;
186 for (i = 0; i < a->num_of_modes; i++) {
187 c->clkdiv[i] = a->clkdiv[i];
188 c->mcic[i] = a->mcic[i];
189 c->mfir_a[i] = a->mfir[i];
190 c->mfir_b[i] = 0; /* Mark FIR B as non-used */
191 }
192 return;
193 }
194
195 if (a->num_of_modes == 0) {
196 c->num_of_modes = b->num_of_modes;
197 for (i = 0; i < b->num_of_modes; i++) {
198 c->clkdiv[i] = b->clkdiv[i];
199 c->mcic[i] = b->mcic[i];
200 c->mfir_b[i] = b->mfir[i];
201 c->mfir_a[i] = 0; /* Mark FIR A as non-used */
202 }
203 return;
204 }
205
206 /* Merge a list of compatible modes */
207 i = 0;
208 for (n = 0; n < a->num_of_modes; n++) {
209 /* Find all indices of values a->clkdiv[n] in b->clkdiv[] */
210 idx_length = find_equal_int16(idx, b->clkdiv, a->clkdiv[n],
211 b->num_of_modes, 0);
212 for (m = 0; m < idx_length; m++) {
213 if (b->mcic[idx[m]] == a->mcic[n]) {
214 c->clkdiv[i] = a->clkdiv[n];
215 c->mcic[i] = a->mcic[n];
216 c->mfir_a[i] = a->mfir[n];
217 c->mfir_b[i] = b->mfir[idx[m]];
218 i++;
219 }
220 }
221 c->num_of_modes = i;
222 }
223 }
224
225 /* Finds a suitable FIR decimation filter from the included set */
get_fir(struct dai * dai,struct dmic_configuration * cfg,int mfir)226 static struct pdm_decim *get_fir(struct dai *dai,
227 struct dmic_configuration *cfg, int mfir)
228 {
229 int i;
230 int fs;
231 int cic_fs;
232 int fir_max_length;
233 struct pdm_decim *fir = NULL;
234
235 if (mfir <= 0)
236 return fir;
237
238 cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
239 fs = cic_fs / mfir;
240 /* FIR max. length depends on available cycles and coef RAM
241 * length. Exceeding this length sets HW overrun status and
242 * overwrite of other register.
243 */
244 fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX,
245 DMIC_HW_IOCLK / fs / 2 -
246 DMIC_FIR_PIPELINE_OVERHEAD);
247
248 i = 0;
249 /* Loop until NULL */
250 while (fir_list[i]) {
251 if (fir_list[i]->decim_factor == mfir) {
252 if (fir_list[i]->length <= fir_max_length) {
253 /* Store pointer, break from loop to avoid a
254 * Possible other mode with lower FIR length.
255 */
256 fir = fir_list[i];
257 break;
258 }
259 dai_info(dai, "get_fir(), Note length=%d exceeds max=%d",
260 fir_list[i]->length, fir_max_length);
261 }
262 i++;
263 }
264
265 return fir;
266 }
267
268 /* Calculate scale and shift to use for FIR coefficients. Scale is applied
269 * before write to HW coef RAM. Shift will be programmed to HW register.
270 */
fir_coef_scale(int32_t * fir_scale,int * fir_shift,int add_shift,const int32_t coef[],int coef_length,int32_t gain)271 static int fir_coef_scale(int32_t *fir_scale, int *fir_shift, int add_shift,
272 const int32_t coef[], int coef_length, int32_t gain)
273 {
274 int32_t amax;
275 int32_t new_amax;
276 int32_t fir_gain;
277 int shift;
278
279 /* Multiply gain passed from CIC with output full scale. */
280 fir_gain = Q_MULTSR_32X32((int64_t)gain, DMIC_HW_SENS_Q28,
281 DMIC_FIR_SCALE_Q, 28, DMIC_FIR_SCALE_Q);
282
283 /* Find the largest FIR coefficient value. */
284 amax = find_max_abs_int32((int32_t *)coef, coef_length);
285
286 /* Scale max. tap value with FIR gain. */
287 new_amax = Q_MULTSR_32X32((int64_t)amax, fir_gain, 31,
288 DMIC_FIR_SCALE_Q, DMIC_FIR_SCALE_Q);
289 if (new_amax <= 0)
290 return -EINVAL;
291
292 /* Get left shifts count to normalize the fractional value as 32 bit.
293 * We need right shifts count for scaling so need to invert. The
294 * difference of Q31 vs. used Q format is added to get the correct
295 * normalization right shift value.
296 */
297 shift = 31 - DMIC_FIR_SCALE_Q - norm_int32(new_amax);
298
299 /* Add to shift for coef raw Q31 format shift and store to
300 * configuration. Ensure range (fail should not happen with OK
301 * coefficient set).
302 */
303 *fir_shift = -shift + add_shift;
304 if (*fir_shift < DMIC_HW_FIR_SHIFT_MIN ||
305 *fir_shift > DMIC_HW_FIR_SHIFT_MAX)
306 return -EINVAL;
307
308 /* Compensate shift into FIR coef scaler and store as Q4.20. */
309 if (shift < 0)
310 *fir_scale = fir_gain << -shift;
311 else
312 *fir_scale = fir_gain >> shift;
313
314 return 0;
315 }
316
317 /* This function selects with a simple criteria one mode to set up the
318 * decimator. For the settings chosen for FIFOs A and B output a lookup
319 * is done for FIR coefficients from the included coefficients tables.
320 * For some decimation factors there may be several length coefficient sets.
321 * It is due to possible restruction of decimation engine cycles per given
322 * sample rate. If the coefficients length is exceeded the lookup continues.
323 * Therefore the list of coefficient set must present the filters for a
324 * decimation factor in decreasing length order.
325 *
326 * Note: If there is no filter available an error is returned. The parameters
327 * should be reviewed for such case. If still a filter is missing it should be
328 * added into the included set. FIR decimation with a high factor usually
329 * needs compromizes into specifications and is not desirable.
330 */
select_mode(struct dai * dai,struct dmic_configuration * cfg,struct matched_modes * modes)331 static int select_mode(struct dai *dai,
332 struct dmic_configuration *cfg,
333 struct matched_modes *modes)
334 {
335 int32_t g_cic;
336 int32_t fir_in_max;
337 int32_t cic_out_max;
338 int32_t gain_to_fir;
339 int16_t idx[DMIC_MAX_MODES];
340 int16_t *mfir;
341 int mcic;
342 int bits_cic;
343 int ret;
344 int n;
345 int found = 0;
346
347 /* If there are more than one possibilities select a mode with a preferred
348 * FIR decimation factor. If there are several select mode with highest
349 * ioclk divider to minimize microphone power consumption. The highest
350 * clock divisors are in the end of list so select the last of list.
351 * The minimum OSR criteria used in previous ensures that quality in
352 * the candidates should be sufficient.
353 */
354 if (modes->num_of_modes == 0) {
355 dai_err(dai, "select_mode(): no modes available");
356 return -EINVAL;
357 }
358
359 /* Valid modes presence is indicated with non-zero decimation
360 * factor in 1st element. If FIR A is not used get decimation factors
361 * from FIR B instead.
362 */
363 if (modes->mfir_a[0] > 0)
364 mfir = modes->mfir_a;
365 else
366 mfir = modes->mfir_b;
367
368 /* Search fir_list[] decimation factors from start towards end. The found
369 * last configuration entry with searched decimation factor will be used.
370 */
371 for (n = 0; fir_list[n]; n++) {
372 found = find_equal_int16(idx, mfir, fir_list[n]->decim_factor,
373 modes->num_of_modes, 0);
374 if (found)
375 break;
376 }
377
378 if (!found) {
379 dai_err(dai, "select_mode(): No filter for decimation found");
380 return -EINVAL;
381 }
382 n = idx[found - 1]; /* Option with highest clock divisor and lowest mic clock rate */
383
384 /* Get microphone clock and decimation parameters for used mode from
385 * the list.
386 */
387 cfg->clkdiv = modes->clkdiv[n];
388 cfg->mfir_a = modes->mfir_a[n];
389 cfg->mfir_b = modes->mfir_b[n];
390 cfg->mcic = modes->mcic[n];
391 cfg->fir_a = NULL;
392 cfg->fir_b = NULL;
393
394 /* Find raw FIR coefficients to match the decimation factors of FIR
395 * A and B.
396 */
397 if (cfg->mfir_a > 0) {
398 cfg->fir_a = get_fir(dai, cfg, cfg->mfir_a);
399 if (!cfg->fir_a) {
400 dai_err(dai, "select_mode(): cannot find FIR coefficients, mfir_a = %u",
401 cfg->mfir_a);
402 return -EINVAL;
403 }
404 }
405
406 if (cfg->mfir_b > 0) {
407 cfg->fir_b = get_fir(dai, cfg, cfg->mfir_b);
408 if (!cfg->fir_b) {
409 dai_err(dai, "select_mode(): cannot find FIR coefficients, mfir_b = %u",
410 cfg->mfir_b);
411 return -EINVAL;
412 }
413 }
414
415 /* Calculate CIC shift from the decimation factor specific gain. The
416 * gain of HW decimator equals decimation factor to power of 5.
417 */
418 mcic = cfg->mcic;
419 g_cic = mcic * mcic * mcic * mcic * mcic;
420 if (g_cic < 0) {
421 /* Erroneous decimation factor and CIC gain */
422 dai_err(dai, "select_mode(): erroneous decimation factor and CIC gain");
423 return -EINVAL;
424 }
425
426 bits_cic = 32 - norm_int32(g_cic);
427 cfg->cic_shift = bits_cic - DMIC_HW_BITS_FIR_INPUT;
428
429 /* Calculate remaining gain to FIR in Q format used for gain
430 * values.
431 */
432 fir_in_max = INT_MAX(DMIC_HW_BITS_FIR_INPUT);
433 if (cfg->cic_shift >= 0)
434 cic_out_max = g_cic >> cfg->cic_shift;
435 else
436 cic_out_max = g_cic << -cfg->cic_shift;
437
438 gain_to_fir = (int32_t)((((int64_t)fir_in_max) << DMIC_FIR_SCALE_Q) /
439 cic_out_max);
440
441 /* Calculate FIR scale and shift */
442 if (cfg->mfir_a > 0) {
443 cfg->fir_a_length = cfg->fir_a->length;
444 ret = fir_coef_scale(&cfg->fir_a_scale, &cfg->fir_a_shift,
445 cfg->fir_a->shift, cfg->fir_a->coef,
446 cfg->fir_a->length, gain_to_fir);
447 if (ret < 0) {
448 /* Invalid coefficient set found, should not happen. */
449 dai_err(dai, "select_mode(): invalid coefficient set found");
450 return -EINVAL;
451 }
452 } else {
453 cfg->fir_a_scale = 0;
454 cfg->fir_a_shift = 0;
455 cfg->fir_a_length = 0;
456 }
457
458 if (cfg->mfir_b > 0) {
459 cfg->fir_b_length = cfg->fir_b->length;
460 ret = fir_coef_scale(&cfg->fir_b_scale, &cfg->fir_b_shift,
461 cfg->fir_b->shift, cfg->fir_b->coef,
462 cfg->fir_b->length, gain_to_fir);
463 if (ret < 0) {
464 /* Invalid coefficient set found, should not happen. */
465 dai_err(dai, "select_mode(): invalid coefficient set found");
466 return -EINVAL;
467 }
468 } else {
469 cfg->fir_b_scale = 0;
470 cfg->fir_b_shift = 0;
471 cfg->fir_b_length = 0;
472 }
473
474 return 0;
475 }
476
477 /* The FIFO input packer mode (IPM) settings are somewhat different in
478 * HW versions. This helper function returns a suitable IPM bit field
479 * value to use.
480 */
481 #ifdef DMIC_IPM_VER1
482
ipm_helper1(struct dmic_pdata * dmic,int * ipm,int di)483 static void ipm_helper1(struct dmic_pdata *dmic, int *ipm, int di)
484 {
485 int pdm[DMIC_HW_CONTROLLERS];
486 int i;
487
488 /* Loop number of PDM controllers in the configuration. If mic A
489 * or B is enabled then a pdm controller is marked as active for
490 * this DAI.
491 */
492 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
493 if (dmic->global->prm[di].pdm[i].enable_mic_a ||
494 dmic->global->prm[di].pdm[i].enable_mic_b)
495 pdm[i] = 1;
496 else
497 pdm[i] = 0;
498 }
499
500 /* Set IPM to match active pdm controllers. */
501 *ipm = 0;
502
503 if (pdm[0] == 0 && pdm[1] > 0)
504 *ipm = 1;
505
506 if (pdm[0] > 0 && pdm[1] > 0)
507 *ipm = 2;
508 }
509
510 #endif
511
512 #ifdef DMIC_IPM_VER2
513
ipm_helper2(struct dmic_pdata * dmic,int source[],int * ipm,int di)514 static inline void ipm_helper2(struct dmic_pdata *dmic, int source[], int *ipm, int di)
515 {
516 int pdm[DMIC_HW_CONTROLLERS];
517 int i;
518 int n = 0;
519
520 for (i = 0; i < OUTCONTROLX_IPM_NUMSOURCES; i++)
521 source[i] = 0;
522
523 /* Loop number of PDM controllers in the configuration. If mic A
524 * or B is enabled then a pdm controller is marked as active.
525 * The function returns in array source[] the indice of enabled
526 * pdm controllers to be used for IPM configuration.
527 */
528 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
529 if (dmic->global->prm[di].pdm[i].enable_mic_a ||
530 dmic->global->prm[di].pdm[i].enable_mic_b) {
531 pdm[i] = 1;
532 source[n] = i;
533 n++;
534 } else {
535 pdm[i] = 0;
536 }
537 }
538
539 /* IPM bit field is set to count of active pdm controllers. */
540 *ipm = pdm[0];
541 for (i = 1; i < DMIC_HW_CONTROLLERS; i++)
542 *ipm += pdm[i];
543 }
544 #endif
545
546 /* Loop number of PDM controllers in the configuration. The function
547 * checks if the controller should operate as stereo or mono left (A)
548 * or mono right (B) mode. Mono right mode is setup as channel
549 * swapped mono left.
550 */
stereo_helper(struct dmic_pdata * dmic,int stereo[],int swap[])551 static int stereo_helper(struct dmic_pdata *dmic, int stereo[], int swap[])
552 {
553 int cnt;
554 int i;
555 int swap_check;
556 int ret = 0;
557
558 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
559 cnt = 0;
560 if (dmic->global->prm[0].pdm[i].enable_mic_a ||
561 dmic->global->prm[1].pdm[i].enable_mic_a)
562 cnt++;
563
564 if (dmic->global->prm[0].pdm[i].enable_mic_b ||
565 dmic->global->prm[1].pdm[i].enable_mic_b)
566 cnt++;
567
568 /* Set stereo mode if both mic A anc B are enabled. */
569 cnt >>= 1;
570 stereo[i] = cnt;
571
572 /* Swap channels if only mic B is used for mono processing. */
573 swap[i] = (dmic->global->prm[0].pdm[i].enable_mic_b ||
574 dmic->global->prm[1].pdm[i].enable_mic_b) && !cnt;
575
576 /* Check that swap does not conflict with other DAI request */
577 swap_check = dmic->global->prm[1].pdm[i].enable_mic_a ||
578 dmic->global->prm[0].pdm[i].enable_mic_a;
579
580 if (swap_check && swap[i])
581 ret = -EINVAL;
582 }
583 return ret;
584 }
585
configure_registers(struct dai * dai,struct dmic_configuration * cfg)586 static int configure_registers(struct dai *dai,
587 struct dmic_configuration *cfg)
588 {
589 struct dmic_pdata *dmic = dai_get_drvdata(dai);
590 int stereo[DMIC_HW_CONTROLLERS];
591 int swap[DMIC_HW_CONTROLLERS];
592 uint32_t val;
593 uint32_t ref;
594 int32_t ci;
595 uint32_t cu;
596 int ipm;
597 int of0;
598 int of1;
599 int fir_decim;
600 int fir_length;
601 int length;
602 int edge;
603 int soft_reset;
604 int cic_mute;
605 int fir_mute;
606 int i;
607 int j;
608 int ret;
609 int pol_a;
610 int pol_b;
611 int di = dai->index;
612 int dccomp = 1;
613 int array_a = 0;
614 int array_b = 0;
615 int bfth = 3; /* Should be 3 for 8 entries, 1 is 2 entries */
616 int th = 0; /* Used with TIE=1 */
617
618 /* Normal start sequence */
619 soft_reset = 1;
620 cic_mute = 1;
621 fir_mute = 1;
622
623 #ifdef DMIC_IPM_VER2
624 int source[OUTCONTROLX_IPM_NUMSOURCES];
625 #endif
626
627 /* pdata is set by dmic_probe(), error if it has not been set */
628 if (!dmic) {
629 dai_err(dai, "configure_registers(): pdata not set");
630 return -EINVAL;
631 }
632
633 dai_info(dai, "configuring registers");
634
635 /* OUTCONTROL0 and OUTCONTROL1 */
636 of0 = (dmic->global->prm[0].fifo_bits == 32) ? 2 : 0;
637
638 #if DMIC_HW_FIFOS > 1
639 of1 = (dmic->global->prm[1].fifo_bits == 32) ? 2 : 0;
640 #else
641 of1 = 0;
642 #endif
643
644 #ifdef DMIC_IPM_VER1
645 if (di == 0) {
646 ipm_helper1(dmic, &ipm, 0);
647 val = OUTCONTROL0_TIE(0) |
648 OUTCONTROL0_SIP(0) |
649 OUTCONTROL0_FINIT(1) |
650 OUTCONTROL0_FCI(0) |
651 OUTCONTROL0_BFTH(bfth) |
652 OUTCONTROL0_OF(of0) |
653 OUTCONTROL0_IPM(ipm) |
654 OUTCONTROL0_TH(th);
655 dai_write(dai, OUTCONTROL0, val);
656 dai_dbg(dai, "configure_registers(), OUTCONTROL0 = %08x", val);
657 } else {
658 ipm_helper1(dmic, &ipm, 1);
659 val = OUTCONTROL1_TIE(0) |
660 OUTCONTROL1_SIP(0) |
661 OUTCONTROL1_FINIT(1) |
662 OUTCONTROL1_FCI(0) |
663 OUTCONTROL1_BFTH(bfth) |
664 OUTCONTROL1_OF(of1) |
665 OUTCONTROL1_IPM(ipm) |
666 OUTCONTROL1_TH(th);
667 dai_write(dai, OUTCONTROL1, val);
668 dai_dbg(dai, "configure_registers(), OUTCONTROL1 = %08x", val);
669 }
670 #endif
671
672 #ifdef DMIC_IPM_VER2
673 if (di == 0) {
674 ipm_helper2(dmic, source, &ipm, 0);
675 val = OUTCONTROL0_TIE(0) |
676 OUTCONTROL0_SIP(0) |
677 OUTCONTROL0_FINIT(1) |
678 OUTCONTROL0_FCI(0) |
679 OUTCONTROL0_BFTH(bfth) |
680 OUTCONTROL0_OF(of0) |
681 OUTCONTROL0_IPM(ipm) |
682 OUTCONTROL0_IPM_SOURCE_1(source[0]) |
683 OUTCONTROL0_IPM_SOURCE_2(source[1]) |
684 OUTCONTROL0_IPM_SOURCE_3(source[2]) |
685 OUTCONTROL0_IPM_SOURCE_4(source[3]) |
686 OUTCONTROL0_TH(th);
687 dai_write(dai, OUTCONTROL0, val);
688 dai_dbg(dai, "configure_registers(), OUTCONTROL0 = %08x", val);
689 } else {
690 ipm_helper2(dmic, source, &ipm, 1);
691 val = OUTCONTROL1_TIE(0) |
692 OUTCONTROL1_SIP(0) |
693 OUTCONTROL1_FINIT(1) |
694 OUTCONTROL1_FCI(0) |
695 OUTCONTROL1_BFTH(bfth) |
696 OUTCONTROL1_OF(of1) |
697 OUTCONTROL1_IPM(ipm) |
698 OUTCONTROL1_IPM_SOURCE_1(source[0]) |
699 OUTCONTROL1_IPM_SOURCE_2(source[1]) |
700 OUTCONTROL1_IPM_SOURCE_3(source[2]) |
701 OUTCONTROL1_IPM_SOURCE_4(source[3]) |
702 OUTCONTROL1_TH(th);
703 dai_write(dai, OUTCONTROL1, val);
704 dai_dbg(dai, "configure_registers(), OUTCONTROL1 = %08x", val);
705 }
706 #endif
707
708 /* Mark enabled microphones into private data to be later used
709 * for starting correct parts of the HW.
710 */
711 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
712 dmic->enable[i] = (dmic->global->prm[di].pdm[i].enable_mic_b << 1) |
713 dmic->global->prm[di].pdm[i].enable_mic_a;
714 }
715
716
717 ret = stereo_helper(dmic, stereo, swap);
718 if (ret < 0) {
719 dai_err(dai, "configure_registers(): enable conflict");
720 return ret;
721 }
722
723 /* Note about accessing dmic_active_fifos_mask: the dai spinlock has been set in
724 * the calling function dmic_set_config().
725 */
726 for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
727 if (dmic->global->active_fifos_mask == 0) {
728 /* CIC */
729 pol_a = dmic->global->prm[di].pdm[i].polarity_mic_a;
730 pol_b = dmic->global->prm[di].pdm[i].polarity_mic_b;
731 val = CIC_CONTROL_SOFT_RESET(soft_reset) |
732 CIC_CONTROL_CIC_START_B(0) |
733 CIC_CONTROL_CIC_START_A(0) |
734 CIC_CONTROL_MIC_B_POLARITY(pol_b) |
735 CIC_CONTROL_MIC_A_POLARITY(pol_a) |
736 CIC_CONTROL_MIC_MUTE(cic_mute) |
737 CIC_CONTROL_STEREO_MODE(stereo[i]);
738 dai_write(dai, base[i] + CIC_CONTROL, val);
739 dai_dbg(dai, "configure_registers(), CIC_CONTROL = %08x", val);
740
741 val = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) |
742 CIC_CONFIG_COMB_COUNT(cfg->mcic - 1);
743 dai_write(dai, base[i] + CIC_CONFIG, val);
744 dai_dbg(dai, "configure_registers(), CIC_CONFIG = %08x", val);
745
746 /* Mono right channel mic usage requires swap of PDM channels
747 * since the mono decimation is done with only left channel
748 * processing active.
749 */
750 edge = dmic->global->prm[di].pdm[i].clk_edge;
751 if (swap[i])
752 edge = !edge;
753
754 val = MIC_CONTROL_PDM_CLKDIV(cfg->clkdiv - 2) |
755 MIC_CONTROL_PDM_SKEW(dmic->global->prm[di].pdm[i].skew) |
756 MIC_CONTROL_CLK_EDGE(edge) |
757 MIC_CONTROL_PDM_EN_B(0) |
758 MIC_CONTROL_PDM_EN_A(0);
759 dai_write(dai, base[i] + MIC_CONTROL, val);
760 dai_dbg(dai, "configure_registers(), MIC_CONTROL = %08x", val);
761 } else {
762 /* Check that request is compatible with running configuration:
763 * CIC decimation factor and shift value check
764 */
765 val = dai_read(dai, base[i] + CIC_CONFIG);
766 ref = CIC_CONFIG_CIC_SHIFT(cfg->cic_shift + 8) |
767 CIC_CONFIG_COMB_COUNT(cfg->mcic - 1);
768 if ((val &
769 (CIC_CONFIG_CIC_SHIFT_MASK | CIC_CONFIG_COMB_COUNT_MASK)) != ref) {
770 dai_err(dai, "configure_registers(): CIC_CONFIG %08x block", val);
771 return -EINVAL;
772 }
773
774 /* Clock divider check */
775 val = dai_read(dai, base[i] + MIC_CONTROL);
776 ref = MIC_CONTROL_PDM_CLKDIV(cfg->clkdiv - 2);
777 if ((val & MIC_CONTROL_PDM_CLKDIV_MASK) != ref) {
778 dai_err(dai, "configure_registers(): MIC_CONTROL %08x block", val);
779 return -EINVAL;
780 }
781 }
782
783 if (di == 0) {
784 /* FIR A */
785 fir_decim = MAX(cfg->mfir_a - 1, 0);
786 fir_length = MAX(cfg->fir_a_length - 1, 0);
787 val = FIR_CONTROL_A_START(0) |
788 FIR_CONTROL_A_ARRAY_START_EN(array_a) |
789 FIR_CONTROL_A_DCCOMP(dccomp) |
790 FIR_CONTROL_A_MUTE(fir_mute) |
791 FIR_CONTROL_A_STEREO(stereo[i]);
792 dai_write(dai, base[i] + FIR_CONTROL_A, val);
793 dai_dbg(dai, "configure_registers(), FIR_CONTROL_A = %08x", val);
794
795 val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) |
796 FIR_CONFIG_A_FIR_SHIFT(cfg->fir_a_shift) |
797 FIR_CONFIG_A_FIR_LENGTH(fir_length);
798 dai_write(dai, base[i] + FIR_CONFIG_A, val);
799 dai_dbg(dai, "configure_registers(), FIR_CONFIG_A = %08x", val);
800
801 val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0);
802 dai_write(dai, base[i] + DC_OFFSET_LEFT_A, val);
803 dai_dbg(dai, "configure_registers(), DC_OFFSET_LEFT_A = %08x", val);
804
805 val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0);
806 dai_write(dai, base[i] + DC_OFFSET_RIGHT_A, val);
807 dai_dbg(dai, "configure_registers(), DC_OFFSET_RIGHT_A = %08x", val);
808
809 val = OUT_GAIN_LEFT_A_GAIN(0);
810 dai_write(dai, base[i] + OUT_GAIN_LEFT_A, val);
811 dai_dbg(dai, "configure_registers(), OUT_GAIN_LEFT_A = %08x", val);
812
813 val = OUT_GAIN_RIGHT_A_GAIN(0);
814 dai_write(dai, base[i] + OUT_GAIN_RIGHT_A, val);
815 dai_dbg(dai, "configure_registers(), OUT_GAIN_RIGHT_A = %08x", val);
816
817 /* Write coef RAM A with scaled coefficient in reverse order */
818 length = cfg->fir_a_length;
819 for (j = 0; j < length; j++) {
820 ci = (int32_t)Q_MULTSR_32X32((int64_t)cfg->fir_a->coef[j],
821 cfg->fir_a_scale, 31,
822 DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
823 cu = FIR_COEF_A(ci);
824 dai_write(dai, coef_base_a[i] + ((length - j - 1) << 2), cu);
825 }
826 }
827
828 if (di == 1) {
829 /* FIR B */
830 fir_decim = MAX(cfg->mfir_b - 1, 0);
831 fir_length = MAX(cfg->fir_b_length - 1, 0);
832 val = FIR_CONTROL_B_START(0) |
833 FIR_CONTROL_B_ARRAY_START_EN(array_b) |
834 FIR_CONTROL_B_DCCOMP(dccomp) |
835 FIR_CONTROL_B_MUTE(fir_mute) |
836 FIR_CONTROL_B_STEREO(stereo[i]);
837 dai_write(dai, base[i] + FIR_CONTROL_B, val);
838 dai_dbg(dai, "configure_registers(), FIR_CONTROL_B = %08x", val);
839
840 val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) |
841 FIR_CONFIG_B_FIR_SHIFT(cfg->fir_b_shift) |
842 FIR_CONFIG_B_FIR_LENGTH(fir_length);
843 dai_write(dai, base[i] + FIR_CONFIG_B, val);
844 dai_dbg(dai, "configure_registers(), FIR_CONFIG_B = %08x", val);
845
846 val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0);
847 dai_write(dai, base[i] + DC_OFFSET_LEFT_B, val);
848 dai_dbg(dai, "configure_registers(), DC_OFFSET_LEFT_B = %08x", val);
849
850 val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0);
851 dai_write(dai, base[i] + DC_OFFSET_RIGHT_B, val);
852 dai_dbg(dai, "configure_registers(), DC_OFFSET_RIGHT_B = %08x", val);
853
854 val = OUT_GAIN_LEFT_B_GAIN(0);
855 dai_write(dai, base[i] + OUT_GAIN_LEFT_B, val);
856 dai_dbg(dai, "configure_registers(), OUT_GAIN_LEFT_B = %08x", val);
857
858 val = OUT_GAIN_RIGHT_B_GAIN(0);
859 dai_write(dai, base[i] + OUT_GAIN_RIGHT_B, val);
860 dai_dbg(dai, "configure_registers(), OUT_GAIN_RIGHT_B = %08x", val);
861
862 /* Write coef RAM B with scaled coefficient in reverse order */
863 length = cfg->fir_b_length;
864 for (j = 0; j < length; j++) {
865 ci = (int32_t)Q_MULTSR_32X32((int64_t)cfg->fir_b->coef[j],
866 cfg->fir_b_scale, 31,
867 DMIC_FIR_SCALE_Q, DMIC_HW_FIR_COEF_Q);
868 cu = FIR_COEF_B(ci);
869 dai_write(dai, coef_base_b[i] + ((length - j - 1) << 2), cu);
870 }
871 }
872 }
873
874 return 0;
875 }
876
877 /* get DMIC hw params */
dmic_get_hw_params_computed(struct dai * dai,struct sof_ipc_stream_params * params,int dir)878 int dmic_get_hw_params_computed(struct dai *dai, struct sof_ipc_stream_params *params, int dir)
879 {
880 struct dmic_pdata *dmic = dai_get_drvdata(dai);
881 int di = dai->index;
882
883 if (!dmic) {
884 dai_err(dai, "dmic_get_hw_params(): dai %d not configured!", di);
885 return -EINVAL;
886 }
887 params->rate = dmic->global->prm[di].fifo_fs;
888 params->buffer_fmt = 0;
889
890 switch (dmic->global->prm[di].num_pdm_active) {
891 case 1:
892 params->channels = 2;
893 break;
894 case 2:
895 params->channels = 4;
896 break;
897 default:
898 dai_info(dai, "dmic_get_hw_params(): not supported PDM active count %d",
899 dmic->global->prm[di].num_pdm_active);
900 return -EINVAL;
901 }
902
903 switch (dmic->global->prm[di].fifo_bits) {
904 case 16:
905 params->frame_fmt = SOF_IPC_FRAME_S16_LE;
906 break;
907 case 32:
908 params->frame_fmt = SOF_IPC_FRAME_S32_LE;
909 break;
910 default:
911 dai_err(dai, "dmic_get_hw_params(): not supported format");
912 return -EINVAL;
913 }
914
915 return 0;
916 }
917
dmic_set_config_computed(struct dai * dai)918 int dmic_set_config_computed(struct dai *dai)
919 {
920 struct dmic_pdata *dmic = dai_get_drvdata(dai);
921 struct matched_modes modes_ab;
922 struct dmic_configuration cfg;
923 struct decim_modes modes_a;
924 struct decim_modes modes_b;
925 int ret;
926 int di = dai->index;
927
928 dai_info(dai, "dmic_set_config(), prm config->dmic.num_pdm_active = %u",
929 dmic->global->prm[di].num_pdm_active);
930 dai_info(dai, "dmic_set_config(), prm pdmclk_min = %u, pdmclk_max = %u",
931 dmic->global->prm[di].pdmclk_min, dmic->global->prm[di].pdmclk_max);
932 dai_info(dai, "dmic_set_config(), prm duty_min = %u, duty_max = %u",
933 dmic->global->prm[di].duty_min, dmic->global->prm[di].duty_max);
934 dai_info(dai, "dmic_set_config(), prm fifo_fs = %u, fifo_bits = %u",
935 dmic->global->prm[di].fifo_fs, dmic->global->prm[di].fifo_bits);
936
937 switch (dmic->global->prm[di].fifo_bits) {
938 case 0:
939 case 16:
940 case 32:
941 break;
942 default:
943 dai_err(dai, "dmic_set_config_computed(): invalid fifo_bits");
944 return -EINVAL;
945 }
946
947 /* Match and select optimal decimators configuration for FIFOs A and B
948 * paths. This setup phase is still abstract. Successful completion
949 * points struct cfg to FIR coefficients and contains the scale value
950 * to use for FIR coefficient RAM write as well as the CIC and FIR
951 * shift values.
952 */
953 find_modes(dai, &modes_a, dmic->global->prm[0].fifo_fs, di);
954 if (modes_a.num_of_modes == 0 && dmic->global->prm[0].fifo_fs > 0) {
955 dai_err(dai, "dmic_set_config(): No modes found found for FIFO A");
956 return -EINVAL;
957 }
958
959 find_modes(dai, &modes_b, dmic->global->prm[1].fifo_fs, di);
960 if (modes_b.num_of_modes == 0 && dmic->global->prm[1].fifo_fs > 0) {
961 dai_err(dai, "dmic_set_config(): No modes found for FIFO B");
962 return -EINVAL;
963 }
964
965 match_modes(&modes_ab, &modes_a, &modes_b);
966 ret = select_mode(dai, &cfg, &modes_ab);
967 if (ret < 0) {
968 dai_err(dai, "dmic_set_config(): select_mode() failed");
969 return -EINVAL;
970 }
971
972 dai_info(dai, "dmic_set_config(), cfg clkdiv = %u, mcic = %u",
973 cfg.clkdiv, cfg.mcic);
974 dai_info(dai, "dmic_set_config(), cfg mfir_a = %u, mfir_b = %u",
975 cfg.mfir_a, cfg.mfir_b);
976 dai_info(dai, "dmic_set_config(), cfg cic_shift = %u",
977 cfg.cic_shift);
978 dai_info(dai, "dmic_set_config(), cfg fir_a_shift = %u, cfg.fir_b_shift = %u",
979 cfg.fir_a_shift, cfg.fir_b_shift);
980 dai_info(dai, "dmic_set_config(), cfg fir_a_length = %u, fir_b_length = %u",
981 cfg.fir_a_length, cfg.fir_b_length);
982
983 /* Determine register bits configuration from decimator configuration and
984 * the requested parameters.
985 */
986 ret = configure_registers(dai, &cfg);
987 if (ret < 0) {
988 dai_err(dai, "dmic_set_config(): cannot configure registers");
989 ret = -EINVAL;
990 }
991
992 return ret;
993 }
994
