1/*
2 * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32vf103.h>
15
16/ {
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu: cpu@0 {
25			clock-frequency = <DT_FREQ_M(108)>;
26			compatible = "nuclei,bumblebee", "riscv";
27			riscv,isa = "rv32imac_zicsr_zifencei";
28			reg = <0>;
29		};
30	};
31
32	sram0: memory@20000000 {
33		compatible = "mmio-sram";
34	};
35
36	soc {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "simple-bus";
40		interrupt-parent = <&eclic>;
41		ranges;
42
43		systimer: timer@d1000000 {
44			compatible = "nuclei,systimer";
45			reg = <0xd1000000 0x10000>;
46			interrupts = <3 0>, <7 0>;
47			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
48		};
49
50		eclic: interrupt-controller@d2000000 {
51			compatible = "nuclei,eclic";
52			#address-cells = <0>;
53			#interrupt-cells = <2>;
54			interrupt-controller;
55			reg =  <0xd2000000 0x0001
56				0xd2000004 0x0004
57				0xd200000b 0x0001
58				0xd2001000 0x1000>;
59		};
60
61		rcu: reset-clock-controller@40021000 {
62			compatible = "gd,gd32-rcu";
63			reg = <0x40021000 0x400>;
64			status = "okay";
65
66			cctl: clock-controller {
67				compatible = "gd,gd32-cctl";
68				#clock-cells = <1>;
69				status = "okay";
70			};
71
72			rctl: reset-controller {
73				compatible = "gd,gd32-rctl";
74				#reset-cells = <1>;
75				status = "okay";
76			};
77		};
78
79		fmc: flash-controller@40022000 {
80			compatible = "gd,gd32-flash-controller";
81			reg = <0x40022000 0x400>;
82			#address-cells = <1>;
83			#size-cells = <1>;
84
85			flash0: flash@8000000 {
86				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
87				write-block-size = <2>;
88				max-erase-time-ms = <300>;
89				page-size = <DT_SIZE_K(1)>;
90			};
91		};
92
93		usart0: serial@40013800 {
94			compatible = "gd,gd32-usart";
95			reg = <0x40013800 0x400>;
96			interrupts = <56 0>;
97			clocks = <&cctl GD32_CLOCK_USART0>;
98			resets = <&rctl GD32_RESET_USART0>;
99			status = "disabled";
100		};
101
102		usart1: serial@40004400 {
103			compatible = "gd,gd32-usart";
104			reg = <0x40004400 0x400>;
105			interrupts = <57 0>;
106			clocks = <&cctl GD32_CLOCK_USART1>;
107			resets = <&rctl GD32_RESET_USART1>;
108			status = "disabled";
109		};
110
111		usart2: serial@40004800 {
112			compatible = "gd,gd32-usart";
113			reg = <0x40004800 0x400>;
114			interrupts = <58 0>;
115			clocks = <&cctl GD32_CLOCK_USART2>;
116			resets = <&rctl GD32_RESET_USART2>;
117			status = "disabled";
118		};
119
120		uart3: serial@40004c00 {
121			compatible = "gd,gd32-usart";
122			reg = <0x40004c00 0x400>;
123			interrupts = <71 0>;
124			clocks = <&cctl GD32_CLOCK_UART3>;
125			resets = <&rctl GD32_RESET_UART3>;
126			status = "disabled";
127		};
128
129		uart4: serial@40005000 {
130			compatible = "gd,gd32-usart";
131			reg = <0x40005000 0x400>;
132			interrupts = <72 0>;
133			clocks = <&cctl GD32_CLOCK_UART4>;
134			resets = <&rctl GD32_RESET_UART4>;
135			status = "disabled";
136		};
137
138		adc0: adc@40012400 {
139			compatible = "gd,gd32-adc";
140			reg = <0x40012400 0x400>;
141			interrupts = <37 0>;
142			clocks = <&cctl GD32_CLOCK_ADC0>;
143			resets = <&rctl GD32_RESET_ADC0>;
144			channels = <16>;
145			status = "disabled";
146			#io-channel-cells = <1>;
147		};
148
149		adc1: adc@40012800 {
150			compatible = "gd,gd32-adc";
151			reg = <0x40012800 0x400>;
152			interrupts = <37 0>;
153			clocks = <&cctl GD32_CLOCK_ADC1>;
154			resets = <&rctl GD32_RESET_ADC1>;
155			channels = <16>;
156			status = "disabled";
157			#io-channel-cells = <1>;
158		};
159
160		dac: dac@40007400 {
161			compatible = "gd,gd32-dac";
162			reg = <0x40007400 0x400>;
163			clocks = <&cctl GD32_CLOCK_DAC>;
164			resets = <&rctl GD32_RESET_DAC>;
165			num-channels = <2>;
166			status = "disabled";
167			#io-channel-cells = <1>;
168		};
169
170		i2c0: i2c@40005400 {
171			compatible = "gd,gd32-i2c";
172			reg = <0x40005400 0x400>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175			clock-frequency = <I2C_BITRATE_STANDARD>;
176			interrupts = <50 0>, <51 0>;
177			interrupt-names = "event", "error";
178			clocks = <&cctl GD32_CLOCK_I2C0>;
179			resets = <&rctl GD32_RESET_I2C0>;
180			status = "disabled";
181		};
182
183		spi0: spi@40013000 {
184			compatible = "gd,gd32-spi";
185			reg = <0x40013000 0x400>;
186			interrupts = <54 0>;
187			clocks = <&cctl GD32_CLOCK_SPI0>;
188			resets = <&rctl GD32_RESET_SPI0>;
189			status = "disabled";
190			#address-cells = <1>;
191			#size-cells = <0>;
192		};
193
194		spi1: spi@40003800 {
195			compatible = "gd,gd32-spi";
196			reg = <0x40003800 0x400>;
197			interrupts = <55 0>;
198			clocks = <&cctl GD32_CLOCK_SPI1>;
199			resets = <&rctl GD32_RESET_SPI1>;
200			status = "disabled";
201			#address-cells = <1>;
202			#size-cells = <0>;
203		};
204
205		afio: afio@40010000 {
206			compatible = "gd,gd32-afio";
207			reg = <0x40010000 0x400>;
208			clocks = <&cctl GD32_CLOCK_AFIO>;
209			status = "okay";
210		};
211
212		exti: interrupt-controller@40010400 {
213			compatible = "gd,gd32-exti";
214			#address-cells = <0>;
215			interrupt-controller;
216			#interrupt-cells = <1>;
217			reg = <0x40010400 0x400>;
218			num-lines = <19>;
219			interrupts = <25 0>, <26 0>, <27 0>, <28 0>, <29 0>,
220				     <42 0>, <59 0>;
221			interrupt-names = "line0", "line1", "line2", "line3",
222					  "line4", "line5-9", "line10-15";
223			status = "okay";
224		};
225
226		fwdgt: watchdog@40003000 {
227			compatible = "gd,gd32-fwdgt";
228			reg = <0x40003000 0x400>;
229			status = "disabled";
230		};
231
232		wwdgt: watchdog@40002c00 {
233			compatible = "gd,gd32-wwdgt";
234			reg = <0x40002C00 0x400>;
235			clocks = <&cctl GD32_CLOCK_WWDGT>;
236			resets = <&rctl GD32_RESET_WWDGT>;
237			interrupts = <0 0>;
238			status = "disabled";
239		};
240
241		pinctrl: pin-controller@40010800 {
242			compatible = "gd,gd32-pinctrl-afio";
243			reg = <0x40010800 0x1c00>;
244			#address-cells = <1>;
245			#size-cells = <1>;
246			status = "okay";
247
248			gpioa: gpio@40010800 {
249				compatible = "gd,gd32-gpio";
250				reg = <0x40010800 0x400>;
251				gpio-controller;
252				#gpio-cells = <2>;
253				clocks = <&cctl GD32_CLOCK_GPIOA>;
254				resets = <&rctl GD32_RESET_GPIOA>;
255				status = "disabled";
256			};
257
258			gpiob: gpio@40010c00 {
259				compatible = "gd,gd32-gpio";
260				reg = <0x40010c00 0x400>;
261				gpio-controller;
262				#gpio-cells = <2>;
263				clocks = <&cctl GD32_CLOCK_GPIOB>;
264				resets = <&rctl GD32_RESET_GPIOB>;
265				status = "disabled";
266			};
267
268			gpioc: gpio@40011000 {
269				compatible = "gd,gd32-gpio";
270				reg = <0x40011000 0x400>;
271				gpio-controller;
272				#gpio-cells = <2>;
273				clocks = <&cctl GD32_CLOCK_GPIOC>;
274				resets = <&rctl GD32_RESET_GPIOC>;
275				status = "disabled";
276			};
277
278			gpiod: gpio@40011400 {
279				compatible = "gd,gd32-gpio";
280				reg = <0x40011400 0x400>;
281				gpio-controller;
282				#gpio-cells = <2>;
283				clocks = <&cctl GD32_CLOCK_GPIOD>;
284				resets = <&rctl GD32_RESET_GPIOD>;
285				status = "disabled";
286			};
287
288			gpioe: gpio@40011800 {
289				compatible = "gd,gd32-gpio";
290				reg = <0x40011800 0x400>;
291				gpio-controller;
292				#gpio-cells = <2>;
293				clocks = <&cctl GD32_CLOCK_GPIOE>;
294				resets = <&rctl GD32_RESET_GPIOE>;
295				status = "disabled";
296			};
297		};
298
299		timer0: timer@40012c00 {
300			compatible = "gd,gd32-timer";
301			reg = <0x40012c00 0x400>;
302			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
303			interrupt-names = "brk", "up", "trgcom", "cc";
304			clocks = <&cctl GD32_CLOCK_TIMER0>;
305			resets = <&rctl GD32_RESET_TIMER0>;
306			is-advanced;
307			channels = <4>;
308			status = "disabled";
309
310			pwm {
311				compatible = "gd,gd32-pwm";
312				status = "disabled";
313				#pwm-cells = <3>;
314			};
315		};
316
317		timer1: timer@40000000 {
318			compatible = "gd,gd32-timer";
319			reg = <0x40000000 0x400>;
320			interrupts = <47 0>;
321			interrupt-names = "global";
322			clocks = <&cctl GD32_CLOCK_TIMER1>;
323			resets = <&rctl GD32_RESET_TIMER1>;
324			channels = <4>;
325			status = "disabled";
326
327			pwm {
328				compatible = "gd,gd32-pwm";
329				status = "disabled";
330				#pwm-cells = <3>;
331			};
332		};
333
334		timer2: timer@40000400 {
335			compatible = "gd,gd32-timer";
336			reg = <0x40000400 0x400>;
337			interrupts = <48 0>;
338			interrupt-names = "global";
339			clocks = <&cctl GD32_CLOCK_TIMER2>;
340			resets = <&rctl GD32_RESET_TIMER2>;
341			channels = <4>;
342			status = "disabled";
343
344			pwm {
345				compatible = "gd,gd32-pwm";
346				status = "disabled";
347				#pwm-cells = <3>;
348			};
349		};
350
351		timer3: timer@40000800 {
352			compatible = "gd,gd32-timer";
353			reg = <0x40000800 0x400>;
354			interrupts = <49 0>;
355			interrupt-names = "global";
356			clocks = <&cctl GD32_CLOCK_TIMER3>;
357			resets = <&rctl GD32_RESET_TIMER3>;
358			channels = <4>;
359			status = "disabled";
360
361			pwm {
362				compatible = "gd,gd32-pwm";
363				status = "disabled";
364				#pwm-cells = <3>;
365			};
366		};
367
368		timer4: timer@40000c00 {
369			compatible = "gd,gd32-timer";
370			reg = <0x40000c00 0x400>;
371			interrupts = <69 0>;
372			interrupt-names = "global";
373			clocks = <&cctl GD32_CLOCK_TIMER4>;
374			resets = <&rctl GD32_RESET_TIMER4>;
375			channels = <4>;
376			status = "disabled";
377
378			pwm {
379				compatible = "gd,gd32-pwm";
380				status = "disabled";
381				#pwm-cells = <3>;
382			};
383		};
384
385		timer5: timer@40001000 {
386			compatible = "gd,gd32-timer";
387			reg = <0x40001000 0x400>;
388			interrupts = <73 0>;
389			interrupt-names = "global";
390			clocks = <&cctl GD32_CLOCK_TIMER5>;
391			resets = <&rctl GD32_RESET_TIMER5>;
392			channels = <0>;
393			status = "disabled";
394		};
395
396		timer6: timer@40001400 {
397			compatible = "gd,gd32-timer";
398			reg = <0x40001400 0x400>;
399			interrupts = <74 0>;
400			interrupt-names = "global";
401			clocks = <&cctl GD32_CLOCK_TIMER6>;
402			resets = <&rctl GD32_RESET_TIMER6>;
403			channels = <0>;
404			status = "disabled";
405		};
406
407		dma0: dma@40020000 {
408			compatible = "gd,gd32-dma";
409			reg = <0x40020000 0x400>;
410			interrupts = <30 0>, <31 0>, <32 0>, <33 0>,
411				     <34 0>, <35 0>, <36 0>;
412			clocks = <&cctl GD32_CLOCK_DMA0>;
413			dma-channels = <7>;
414			gd,mem2mem;
415			#dma-cells = <2>;
416			status = "disabled";
417		};
418
419		dma1: dma@40020400 {
420			compatible = "gd,gd32-dma";
421			reg = <0x40020400 0x400>;
422			interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
423				     <79 0>;
424			clocks = <&cctl GD32_CLOCK_DMA1>;
425			dma-channels = <5>;
426			gd,mem2mem;
427			#dma-cells = <2>;
428			status = "disabled";
429		};
430	};
431};
432