1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RTC_CNTL_STRUCT_H_ 15 #define _SOC_RTC_CNTL_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct rtc_cntl_dev_s { 24 union { 25 struct { 26 uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ 27 uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ 28 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ 29 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ 30 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ 31 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ 32 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ 33 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ 34 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ 35 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ 36 uint32_t xtl_force_pd: 1; /*crystall force power down*/ 37 uint32_t xtl_force_pu: 1; /*crystall force power up*/ 38 uint32_t bias_sleep_folw_8m: 1; /*BIAS_SLEEP follow CK8M*/ 39 uint32_t bias_force_sleep: 1; /*BIAS_SLEEP force sleep*/ 40 uint32_t bias_force_nosleep: 1; /*BIAS_SLEEP force no sleep*/ 41 uint32_t bias_i2c_folw_8m: 1; /*BIAS_I2C follow CK8M*/ 42 uint32_t bias_i2c_force_pd: 1; /*BIAS_I2C force power down*/ 43 uint32_t bias_i2c_force_pu: 1; /*BIAS_I2C force power up*/ 44 uint32_t bias_core_folw_8m: 1; /*BIAS_CORE follow CK8M*/ 45 uint32_t bias_core_force_pd: 1; /*BIAS_CORE force power down*/ 46 uint32_t bias_core_force_pu: 1; /*BIAS_CORE force power up*/ 47 uint32_t xtl_force_iso: 1; 48 uint32_t pll_force_iso: 1; 49 uint32_t analog_force_iso: 1; 50 uint32_t xtl_force_noiso: 1; 51 uint32_t pll_force_noiso: 1; 52 uint32_t analog_force_noiso: 1; 53 uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ 54 uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ 55 uint32_t sw_sys_rst: 1; /*SW system reset*/ 56 }; 57 uint32_t val; 58 } options0; 59 uint32_t slp_timer0; /*RTC sleep timer low 32 bits*/ 60 union { 61 struct { 62 uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ 63 uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ 64 uint32_t reserved17: 15; 65 }; 66 uint32_t val; 67 } slp_timer1; 68 union { 69 struct { 70 uint32_t reserved0: 30; 71 uint32_t valid: 1; /*To indicate the register is updated*/ 72 uint32_t update: 1; /*Set 1: to update register with RTC timer*/ 73 }; 74 uint32_t val; 75 } time_update; 76 uint32_t time0; /*RTC timer low 32 bits*/ 77 union { 78 struct { 79 uint32_t time_hi:16; /*RTC timer high 16 bits*/ 80 uint32_t reserved16: 16; 81 }; 82 uint32_t val; 83 } time1; 84 union { 85 struct { 86 uint32_t reserved0: 20; 87 uint32_t touch_wakeup_force_en: 1; /*touch controller force wake up*/ 88 uint32_t ulp_cp_wakeup_force_en: 1; /*ULP-coprocessor force wake up*/ 89 uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge 0: APB to RTC using sync*/ 90 uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ 91 uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ 92 uint32_t reserved25: 3; 93 uint32_t sdio_active_ind: 1; /*SDIO active indication*/ 94 uint32_t slp_wakeup: 1; /*sleep wakeup bit*/ 95 uint32_t slp_reject: 1; /*sleep reject bit*/ 96 uint32_t sleep_en: 1; /*sleep enable bit*/ 97 }; 98 uint32_t val; 99 } state0; 100 union { 101 struct { 102 uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ 103 uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ 104 uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ 105 uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ 106 uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ 107 }; 108 uint32_t val; 109 } timer1; 110 union { 111 struct { 112 uint32_t reserved0: 15; 113 uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ 114 uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ 115 }; 116 uint32_t val; 117 } timer2; 118 union { 119 struct { 120 uint32_t wifi_wait_timer: 9; 121 uint32_t wifi_powerup_timer: 7; 122 uint32_t rom_ram_wait_timer: 9; 123 uint32_t rom_ram_powerup_timer: 7; 124 }; 125 uint32_t val; 126 } timer3; 127 union { 128 struct { 129 uint32_t rtc_wait_timer: 9; 130 uint32_t rtc_powerup_timer: 7; 131 uint32_t dg_wrap_wait_timer: 9; 132 uint32_t dg_wrap_powerup_timer: 7; 133 }; 134 uint32_t val; 135 } timer4; 136 union { 137 struct { 138 uint32_t ulp_cp_subtimer_prediv: 8; 139 uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ 140 uint32_t rtcmem_wait_timer: 9; 141 uint32_t rtcmem_powerup_timer: 7; 142 }; 143 uint32_t val; 144 } timer5; 145 union { 146 struct { 147 uint32_t reserved0: 23; 148 uint32_t plla_force_pd: 1; /*PLLA force power down*/ 149 uint32_t plla_force_pu: 1; /*PLLA force power up*/ 150 uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ 151 uint32_t pvtmon_pu: 1; /*1: PVTMON power up otherwise power down*/ 152 uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up otherwise power down*/ 153 uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up otherwise power down*/ 154 uint32_t reserved29: 1; 155 uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up otherwise power down*/ 156 uint32_t pll_i2c_pu: 1; /*1: PLL_I2C power up otherwise power down*/ 157 }; 158 uint32_t val; 159 } ana_conf; 160 union { 161 struct { 162 uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ 163 uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ 164 uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ 165 uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ 166 uint32_t reserved14: 18; 167 }; 168 uint32_t val; 169 } reset_state; 170 union { 171 struct { 172 uint32_t wakeup_cause: 11; /*wakeup cause*/ 173 uint32_t rtc_wakeup_ena: 11; /*wakeup enable bitmap*/ 174 uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ 175 uint32_t reserved23: 9; 176 }; 177 uint32_t val; 178 } wakeup_state; 179 union { 180 struct { 181 uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ 182 uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ 183 uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ 184 uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ 185 uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ 186 uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ 187 uint32_t rtc_touch: 1; /*enable touch interrupt*/ 188 uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ 189 uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ 190 uint32_t reserved9: 23; 191 }; 192 uint32_t val; 193 } int_ena; 194 union { 195 struct { 196 uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ 197 uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ 198 uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ 199 uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ 200 uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ 201 uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ 202 uint32_t rtc_touch: 1; /*touch interrupt raw*/ 203 uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ 204 uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ 205 uint32_t reserved9: 23; 206 }; 207 uint32_t val; 208 } int_raw; 209 union { 210 struct { 211 uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ 212 uint32_t slp_reject: 1; /*sleep reject interrupt state*/ 213 uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ 214 uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ 215 uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ 216 uint32_t rtc_sar: 1; /*ULP-coprocessor interrupt state*/ 217 uint32_t rtc_touch: 1; /*touch interrupt state*/ 218 uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ 219 uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ 220 uint32_t reserved9: 23; 221 }; 222 uint32_t val; 223 } int_st; 224 union { 225 struct { 226 uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ 227 uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ 228 uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ 229 uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ 230 uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ 231 uint32_t rtc_sar: 1; /*Clear ULP-coprocessor interrupt state*/ 232 uint32_t rtc_touch: 1; /*Clear touch interrupt state*/ 233 uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ 234 uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ 235 uint32_t reserved9: 23; 236 }; 237 uint32_t val; 238 } int_clr; 239 uint32_t rtc_store0; /*32-bit general purpose retention register*/ 240 uint32_t rtc_store1; /*32-bit general purpose retention register*/ 241 uint32_t rtc_store2; /*32-bit general purpose retention register*/ 242 uint32_t rtc_store3; /*32-bit general purpose retention register*/ 243 union { 244 struct { 245 uint32_t reserved0: 30; 246 uint32_t ctr_lv: 1; /*0: power down XTAL at high level 1: power down XTAL at low level*/ 247 uint32_t ctr_en: 1; /*enable control XTAL by external pads*/ 248 }; 249 uint32_t val; 250 } ext_xtl_conf; 251 union { 252 struct { 253 uint32_t reserved0: 30; 254 uint32_t wakeup0_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ 255 uint32_t wakeup1_lv: 1; /*0: external wakeup at low level 1: external wakeup at high level*/ 256 }; 257 uint32_t val; 258 } ext_wakeup_conf; 259 union { 260 struct { 261 uint32_t reserved0: 24; 262 uint32_t gpio_reject_en: 1; /*enable GPIO reject*/ 263 uint32_t sdio_reject_en: 1; /*enable SDIO reject*/ 264 uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ 265 uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ 266 uint32_t reject_cause: 4; /*sleep reject cause*/ 267 }; 268 uint32_t val; 269 } slp_reject_conf; 270 union { 271 struct { 272 uint32_t reserved0: 29; 273 uint32_t cpusel_conf: 1; /*CPU sel option*/ 274 uint32_t cpuperiod_sel: 2; /*CPU period sel*/ 275 }; 276 uint32_t val; 277 } cpu_period_conf; 278 union { 279 struct { 280 uint32_t reserved0: 22; 281 uint32_t sdio_act_dnum:10; 282 }; 283 uint32_t val; 284 } sdio_act_conf; 285 union { 286 struct { 287 uint32_t reserved0: 4; 288 uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ 289 uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ 290 uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ 291 uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ 292 uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ 293 uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ 294 uint32_t ck8m_dfreq_force: 1; 295 uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ 296 uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ 297 uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ 298 uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ 299 uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ 300 uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ 301 uint32_t soc_clk_sel: 2; /*SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ 302 uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ 303 uint32_t ana_clk_rtc_sel: 2; /*slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ 304 }; 305 uint32_t val; 306 } clk_conf; 307 union { 308 struct { 309 uint32_t reserved0: 21; 310 uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ 311 uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG 0: use state machine*/ 312 uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 313 uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ 314 uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ 315 uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ 316 uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ 317 uint32_t xpd_sdio: 1; /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ 318 }; 319 uint32_t val; 320 } sdio_conf; 321 union { 322 struct { 323 uint32_t reserved0: 24; 324 uint32_t dbg_atten: 2; /*DBG_ATTEN*/ 325 uint32_t enb_sck_xtal: 1; /*ENB_SCK_XTAL*/ 326 uint32_t inc_heartbeat_refresh: 1; /*INC_HEARTBEAT_REFRESH*/ 327 uint32_t dec_heartbeat_period: 1; /*DEC_HEARTBEAT_PERIOD*/ 328 uint32_t inc_heartbeat_period: 1; /*INC_HEARTBEAT_PERIOD*/ 329 uint32_t dec_heartbeat_width: 1; /*DEC_HEARTBEAT_WIDTH*/ 330 uint32_t rst_bias_i2c: 1; /*RST_BIAS_I2C*/ 331 }; 332 uint32_t val; 333 } bias_conf; 334 union { 335 struct { 336 uint32_t reserved0: 7; 337 uint32_t sck_dcap_force: 1; /*N/A*/ 338 uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ 339 uint32_t dig_dbias_wak: 3; /*DIG_REG_DBIAS during wakeup*/ 340 uint32_t sck_dcap: 8; /*SCK_DCAP*/ 341 uint32_t rtc_dbias_slp: 3; /*RTC_DBIAS during sleep*/ 342 uint32_t rtc_dbias_wak: 3; /*RTC_DBIAS during wakeup*/ 343 uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ 344 uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ 345 uint32_t rtc_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ 346 uint32_t rtc_force_pu: 1; /*RTC_REG force power up*/ 347 }; 348 uint32_t val; 349 } rtc; 350 union { 351 struct { 352 uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ 353 uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ 354 uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ 355 uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ 356 uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ 357 uint32_t force_noiso: 1; /*rtc_peri force no ISO*/ 358 uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ 359 uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ 360 uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ 361 uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ 362 uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ 363 uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ 364 uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ 365 uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ 366 uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ 367 uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ 368 uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ 369 uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ 370 uint32_t pwc_force_pd: 1; /*rtc_peri force power down*/ 371 uint32_t pwc_force_pu: 1; /*rtc_peri force power up*/ 372 uint32_t pd_en: 1; /*enable power down rtc_peri in sleep*/ 373 uint32_t reserved21: 11; 374 }; 375 uint32_t val; 376 } rtc_pwc; 377 union { 378 struct { 379 uint32_t reserved0: 3; 380 uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ 381 uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ 382 uint32_t rom0_force_pd: 1; /*ROM force power down*/ 383 uint32_t rom0_force_pu: 1; /*ROM force power up*/ 384 uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ 385 uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ 386 uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ 387 uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ 388 uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ 389 uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ 390 uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ 391 uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ 392 uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ 393 uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ 394 uint32_t wifi_force_pd: 1; /*wifi force power down*/ 395 uint32_t wifi_force_pu: 1; /*wifi force power up*/ 396 uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ 397 uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ 398 uint32_t reserved21: 3; 399 uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ 400 uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ 401 uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ 402 uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ 403 uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ 404 uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ 405 uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ 406 uint32_t dg_wrap_pd_en: 1; /*enable power down digital core in sleep*/ 407 }; 408 uint32_t val; 409 } dig_pwc; 410 union { 411 struct { 412 uint32_t reserved0: 7; 413 uint32_t dig_iso_force_off: 1; 414 uint32_t dig_iso_force_on: 1; 415 uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ 416 uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ 417 uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ 418 uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ 419 uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ 420 uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ 421 uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ 422 uint32_t rom0_force_iso: 1; /*ROM force ISO*/ 423 uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ 424 uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ 425 uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ 426 uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ 427 uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ 428 uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ 429 uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ 430 uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ 431 uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ 432 uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ 433 uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ 434 uint32_t wifi_force_iso: 1; /*wifi force ISO*/ 435 uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ 436 uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ 437 uint32_t dg_wrap_force_noiso: 1; /*digital core force no ISO*/ 438 }; 439 uint32_t val; 440 } dig_iso; 441 union { 442 struct { 443 uint32_t reserved0: 7; 444 uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ 445 uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ 446 uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ 447 uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ 448 uint32_t sys_reset_length: 3; /*system reset counter length*/ 449 uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ 450 uint32_t level_int_en: 1; /*When set, level type interrupt generation is enabled*/ 451 uint32_t edge_int_en: 1; /*When set, edge type interrupt generation is enabled*/ 452 uint32_t stg3: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ 453 uint32_t stg2: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ 454 uint32_t stg1: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ 455 uint32_t stg0: 3; /*1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en*/ 456 uint32_t en: 1; /*enable RTC WDT*/ 457 }; 458 uint32_t val; 459 } wdt_config0; 460 uint32_t wdt_config1; /**/ 461 uint32_t wdt_config2; /**/ 462 uint32_t wdt_config3; /**/ 463 uint32_t wdt_config4; /**/ 464 union { 465 struct { 466 uint32_t reserved0: 31; 467 uint32_t feed: 1; 468 }; 469 uint32_t val; 470 } wdt_feed; 471 uint32_t wdt_wprotect; /**/ 472 union { 473 struct { 474 uint32_t reserved0: 29; 475 uint32_t ent_rtc: 1; /*ENT_RTC*/ 476 uint32_t dtest_rtc: 2; /*DTEST_RTC*/ 477 }; 478 uint32_t val; 479 } test_mux; 480 union { 481 struct { 482 uint32_t reserved0: 20; 483 uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ 484 uint32_t procpu_c1: 6; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ 485 }; 486 uint32_t val; 487 } sw_cpu_stall; 488 uint32_t store4; /*32-bit general purpose retention register*/ 489 uint32_t store5; /*32-bit general purpose retention register*/ 490 uint32_t store6; /*32-bit general purpose retention register*/ 491 uint32_t store7; /*32-bit general purpose retention register*/ 492 uint32_t diag0; /**/ 493 uint32_t diag1; /**/ 494 union { 495 struct { 496 uint32_t adc1_hold_force: 1; 497 uint32_t adc2_hold_force: 1; 498 uint32_t pdac1_hold_force: 1; 499 uint32_t pdac2_hold_force: 1; 500 uint32_t sense1_hold_force: 1; 501 uint32_t sense2_hold_force: 1; 502 uint32_t sense3_hold_force: 1; 503 uint32_t sense4_hold_force: 1; 504 uint32_t touch_pad0_hold_force: 1; 505 uint32_t touch_pad1_hold_force: 1; 506 uint32_t touch_pad2_hold_force: 1; 507 uint32_t touch_pad3_hold_force: 1; 508 uint32_t touch_pad4_hold_force: 1; 509 uint32_t touch_pad5_hold_force: 1; 510 uint32_t touch_pad6_hold_force: 1; 511 uint32_t touch_pad7_hold_force: 1; 512 uint32_t x32p_hold_force: 1; 513 uint32_t x32n_hold_force: 1; 514 uint32_t reserved18: 14; 515 }; 516 uint32_t val; 517 } hold_force; 518 union { 519 struct { 520 uint32_t ext_wakeup1_sel: 18; /*Bitmap to select RTC pads for ext wakeup1*/ 521 uint32_t ext_wakeup1_status_clr: 1; /*clear ext wakeup1 status*/ 522 uint32_t reserved19: 13; 523 }; 524 uint32_t val; 525 } ext_wakeup1; 526 union { 527 struct { 528 uint32_t ext_wakeup1_status:18; /*ext wakeup1 status*/ 529 uint32_t reserved18: 14; 530 }; 531 uint32_t val; 532 } ext_wakeup1_status; 533 union { 534 struct { 535 uint32_t reserved0: 14; 536 uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ 537 uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ 538 uint32_t rst_wait: 10; /*brown out reset wait cycles*/ 539 uint32_t rst_ena: 1; /*enable brown out reset*/ 540 uint32_t thres: 3; /*brown out threshold*/ 541 uint32_t ena: 1; /*enable brown out*/ 542 uint32_t det: 1; /*brown out detect*/ 543 }; 544 uint32_t val; 545 } brown_out; 546 uint32_t reserved_39; 547 uint32_t reserved_3d; 548 uint32_t reserved_41; 549 uint32_t reserved_45; 550 uint32_t reserved_49; 551 uint32_t reserved_4d; 552 union { 553 struct { 554 uint32_t date: 28; 555 uint32_t reserved28: 4; 556 }; 557 uint32_t val; 558 } date; 559 } rtc_cntl_dev_t; 560 extern rtc_cntl_dev_t RTCCNTL; 561 562 #ifdef __cplusplus 563 } 564 #endif 565 566 #endif /* _SOC_RTC_CNTL_STRUCT_H_ */ 567
