1 /*
2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8 #include <string.h>
9
10 #include <lib/utils.h>
11
12 #include <dram.h>
13
14 #include "dram_spec_timing.h"
15
16 static const uint8_t ddr3_cl_cwl[][7] = {
17 /*
18 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066
19 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07
20 * cl<<4, cwl cl<<4, cwl cl<<4, cwl
21 */
22 /* DDR3_800D (5-5-5) */
23 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0},
24 /* DDR3_800E (6-6-6) */
25 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0},
26 /* DDR3_1066E (6-6-6) */
27 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0},
28 /* DDR3_1066F (7-7-7) */
29 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0},
30 /* DDR3_1066G (8-8-8) */
31 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0},
32 /* DDR3_1333F (7-7-7) */
33 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7),
34 0, 0, 0},
35 /* DDR3_1333G (8-8-8) */
36 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7),
37 0, 0, 0},
38 /* DDR3_1333H (9-9-9) */
39 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7),
40 0, 0, 0},
41 /* DDR3_1333J (10-10-10) */
42 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7),
43 0, 0, 0},
44 /* DDR3_1600G (8-8-8) */
45 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7),
46 ((8 << 4) | 8), 0, 0},
47 /* DDR3_1600H (9-9-9) */
48 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7),
49 ((9 << 4) | 8), 0, 0},
50 /* DDR3_1600J (10-10-10) */
51 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7),
52 ((10 << 4) | 8), 0, 0},
53 /* DDR3_1600K (11-11-11) */
54 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7),
55 ((11 << 4) | 8), 0, 0},
56 /* DDR3_1866J (10-10-10) */
57 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7),
58 ((9 << 4) | 8), ((11 << 4) | 9), 0},
59 /* DDR3_1866K (11-11-11) */
60 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7),
61 ((10 << 4) | 8), ((11 << 4) | 9), 0},
62 /* DDR3_1866L (12-12-12) */
63 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7),
64 ((11 << 4) | 8), ((12 << 4) | 9), 0},
65 /* DDR3_1866M (13-13-13) */
66 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7),
67 ((11 << 4) | 8), ((13 << 4) | 9), 0},
68 /* DDR3_2133K (11-11-11) */
69 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7),
70 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)},
71 /* DDR3_2133L (12-12-12) */
72 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7),
73 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)},
74 /* DDR3_2133M (13-13-13) */
75 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7),
76 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)},
77 /* DDR3_2133N (14-14-14) */
78 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7),
79 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)},
80 /* DDR3_DEFAULT */
81 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7),
82 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}
83 };
84
85 static const uint16_t ddr3_trc_tfaw[] = {
86 /* tRC tFAW */
87 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */
88 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */
89
90 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */
91 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */
92 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */
93
94 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */
95 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */
96 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */
97 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */
98
99 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */
100 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/
101 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */
102 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */
103
104 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */
105 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */
106 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */
107 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */
108
109 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */
110 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */
111 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */
112 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */
113
114 ((53 << 8) | 50) /* DDR3_DEFAULT */
115 };
116
get_max_speed_rate(struct timing_related_config * timing_config)117 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config)
118 {
119 if (timing_config->ch_cnt > 1)
120 return max(timing_config->dram_info[0].speed_rate,
121 timing_config->dram_info[1].speed_rate);
122 else
123 return timing_config->dram_info[0].speed_rate;
124 }
125
126 static uint32_t
get_max_die_capability(struct timing_related_config * timing_config)127 get_max_die_capability(struct timing_related_config *timing_config)
128 {
129 uint32_t die_cap = 0;
130 uint32_t cs, ch;
131
132 for (ch = 0; ch < timing_config->ch_cnt; ch++) {
133 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) {
134 die_cap = max(die_cap,
135 timing_config->
136 dram_info[ch].per_die_capability[cs]);
137 }
138 }
139 return die_cap;
140 }
141
142 /* tRSTL, 100ns */
143 #define DDR3_TRSTL (100)
144 /* trsth, 500us */
145 #define DDR3_TRSTH (500000)
146 /* trefi, 7.8us */
147 #define DDR3_TREFI_7_8_US (7800)
148 /* tWR, 15ns */
149 #define DDR3_TWR (15)
150 /* tRTP, max(4 tCK,7.5ns) */
151 #define DDR3_TRTP (7)
152 /* tRRD = max(4nCK, 10ns) */
153 #define DDR3_TRRD (10)
154 /* tCK */
155 #define DDR3_TCCD (4)
156 /*tWTR, max(4 tCK,7.5ns)*/
157 #define DDR3_TWTR (7)
158 /* tCK */
159 #define DDR3_TRTW (0)
160 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */
161 #define DDR3_TRAS (37)
162 /* ns */
163 #define DDR3_TRFC_512MBIT (90)
164 /* ns */
165 #define DDR3_TRFC_1GBIT (110)
166 /* ns */
167 #define DDR3_TRFC_2GBIT (160)
168 /* ns */
169 #define DDR3_TRFC_4GBIT (300)
170 /* ns */
171 #define DDR3_TRFC_8GBIT (350)
172
173 /*pd and sr*/
174 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */
175 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */
176 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */
177 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */
178 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */
179 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */
180
181 /*mode register timing*/
182 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */
183 #define DDR3_TMRD (4) /* tMRD, 4 tCK */
184
185 /* ZQ */
186 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */
187 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */
188 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */
189
190 /* Write leveling */
191 #define DDR3_TWLMRD (40) /* tCK */
192 #define DDR3_TWLO (9) /* max 7.5ns */
193 #define DDR3_TWLDQSEN (25) /* tCK */
194
195 /*
196 * Description: depend on input parameter "timing_config",
197 * and calculate all ddr3
198 * spec timing to "pdram_timing"
199 * parameters:
200 * input: timing_config
201 * output: pdram_timing
202 */
ddr3_get_parameter(struct timing_related_config * timing_config,struct dram_timing_t * pdram_timing)203 static void ddr3_get_parameter(struct timing_related_config *timing_config,
204 struct dram_timing_t *pdram_timing)
205 {
206 uint32_t nmhz = timing_config->freq;
207 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config);
208 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config);
209 uint32_t tmp;
210
211 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t));
212 pdram_timing->mhz = nmhz;
213 pdram_timing->al = 0;
214 pdram_timing->bl = timing_config->bl;
215 if (nmhz <= 330)
216 tmp = 0;
217 else if (nmhz <= 400)
218 tmp = 1;
219 else if (nmhz <= 533)
220 tmp = 2;
221 else if (nmhz <= 666)
222 tmp = 3;
223 else if (nmhz <= 800)
224 tmp = 4;
225 else if (nmhz <= 933)
226 tmp = 5;
227 else
228 tmp = 6;
229
230 /* when dll bypss cl = cwl = 6 */
231 if (nmhz < 300) {
232 pdram_timing->cl = 6;
233 pdram_timing->cwl = 6;
234 } else {
235 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf;
236 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf;
237 }
238
239 switch (timing_config->dramds) {
240 case 40:
241 tmp = DDR3_DS_40;
242 break;
243 case 34:
244 default:
245 tmp = DDR3_DS_34;
246 break;
247 }
248
249 if (timing_config->odt)
250 switch (timing_config->dramodt) {
251 case 60:
252 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
253 break;
254 case 40:
255 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
256 break;
257 case 120:
258 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
259 break;
260 case 0:
261 default:
262 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
263 break;
264 }
265 else
266 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
267
268 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl);
269 pdram_timing->mr[3] = 0;
270
271 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000);
272 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000);
273 /* tREFI, average periodic refresh interval, 7.8us */
274 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000);
275 /* base timing */
276 pdram_timing->trcd = pdram_timing->cl;
277 pdram_timing->trp = pdram_timing->cl;
278 pdram_timing->trppb = pdram_timing->cl;
279 tmp = ((DDR3_TWR * nmhz + 999) / 1000);
280 pdram_timing->twr = tmp;
281 pdram_timing->tdal = tmp + pdram_timing->trp;
282 if (tmp < 9) {
283 tmp = tmp - 4;
284 } else {
285 tmp += (tmp & 0x1) ? 1 : 0;
286 tmp = tmp >> 1;
287 }
288 if (pdram_timing->bl == 4)
289 pdram_timing->mr[0] = DDR3_BC4
290 | DDR3_CL(pdram_timing->cl)
291 | DDR3_WR(tmp);
292 else
293 pdram_timing->mr[0] = DDR3_BL8
294 | DDR3_CL(pdram_timing->cl)
295 | DDR3_WR(tmp);
296 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
297 pdram_timing->trtp = max(4, tmp);
298 pdram_timing->trc =
299 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000);
300 tmp = ((DDR3_TRRD * nmhz + 999) / 1000);
301 pdram_timing->trrd = max(4, tmp);
302 pdram_timing->tccd = DDR3_TCCD;
303 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000);
304 pdram_timing->twtr = max(4, tmp);
305 pdram_timing->trtw = DDR3_TRTW;
306 pdram_timing->tras_max = 9 * pdram_timing->trefi;
307 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999)
308 / 1000);
309 pdram_timing->tfaw =
310 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999)
311 / 1000);
312 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */
313 if (ddr_capability_per_die <= 0x4000000)
314 tmp = DDR3_TRFC_512MBIT;
315 else if (ddr_capability_per_die <= 0x8000000)
316 tmp = DDR3_TRFC_1GBIT;
317 else if (ddr_capability_per_die <= 0x10000000)
318 tmp = DDR3_TRFC_2GBIT;
319 else if (ddr_capability_per_die <= 0x20000000)
320 tmp = DDR3_TRFC_4GBIT;
321 else
322 tmp = DDR3_TRFC_8GBIT;
323 pdram_timing->trfc = (tmp * nmhz + 999) / 1000;
324 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000));
325 pdram_timing->tdqsck_max = 0;
326 /*pd and sr*/
327 pdram_timing->txsr = DDR3_TDLLK;
328 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
329 pdram_timing->txp = max(3, tmp);
330 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000);
331 pdram_timing->txpdll = max(10, tmp);
332 pdram_timing->tdllk = DDR3_TDLLK;
333 if (nmhz >= 533)
334 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000);
335 else
336 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000);
337 pdram_timing->tcke = max(3, tmp);
338 pdram_timing->tckesr = (pdram_timing->tcke + 1);
339 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000);
340 pdram_timing->tcksre = max(5, tmp);
341 pdram_timing->tcksrx = max(5, tmp);
342 /*mode register timing*/
343 tmp = ((DDR3_TMOD * nmhz + 999) / 1000);
344 pdram_timing->tmod = max(12, tmp);
345 pdram_timing->tmrd = DDR3_TMRD;
346 pdram_timing->tmrr = 0;
347 /*ODT*/
348 pdram_timing->todton = pdram_timing->cwl - 2;
349 /*ZQ*/
350 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000);
351 pdram_timing->tzqinit = max(512, tmp);
352 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000);
353 pdram_timing->tzqcs = max(64, tmp);
354 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000);
355 pdram_timing->tzqoper = max(256, tmp);
356 /* write leveling */
357 pdram_timing->twlmrd = DDR3_TWLMRD;
358 pdram_timing->twldqsen = DDR3_TWLDQSEN;
359 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000);
360 }
361
362 #define LPDDR2_TINIT1 (100) /* ns */
363 #define LPDDR2_TINIT2 (5) /* tCK */
364 #define LPDDR2_TINIT3 (200000) /* 200us */
365 #define LPDDR2_TINIT4 (1000) /* 1us */
366 #define LPDDR2_TINIT5 (10000) /* 10us */
367 #define LPDDR2_TRSTL (0) /* tCK */
368 #define LPDDR2_TRSTH (500000) /* 500us */
369 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */
370 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */
371
372 /* base timing */
373 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */
374 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */
375 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */
376 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */
377 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */
378 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */
379 #define LPDDR2_TCCD (2) /* tCK */
380 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */
381 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */
382 #define LPDDR2_TRTW (0) /* tCK */
383 #define LPDDR2_TRAS_MAX (70000) /* 70us */
384 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */
385 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */
386 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */
387 #define LPDDR2_TRFC_8GBIT (210) /* ns */
388 #define LPDDR2_TRFC_4GBIT (130) /* ns */
389 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */
390 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */
391
392 /*pd and sr*/
393 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */
394 #define LPDDR2_TXPDLL (0)
395 #define LPDDR2_TDLLK (0) /* tCK */
396 #define LPDDR2_TCKE (3) /* tCK */
397 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */
398 #define LPDDR2_TCKSRE (1) /* tCK */
399 #define LPDDR2_TCKSRX (2) /* tCK */
400
401 /*mode register timing*/
402 #define LPDDR2_TMOD (0)
403 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */
404 #define LPDDR2_TMRR (2) /* tCK */
405
406 /*ZQ*/
407 #define LPDDR2_TZQINIT (1000) /* ns */
408 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */
409 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */
410 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */
411
412 /*
413 * Description: depend on input parameter "timing_config",
414 * and calculate all lpddr2
415 * spec timing to "pdram_timing"
416 * parameters:
417 * input: timing_config
418 * output: pdram_timing
419 */
lpddr2_get_parameter(struct timing_related_config * timing_config,struct dram_timing_t * pdram_timing)420 static void lpddr2_get_parameter(struct timing_related_config *timing_config,
421 struct dram_timing_t *pdram_timing)
422 {
423 uint32_t nmhz = timing_config->freq;
424 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config);
425 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp;
426
427 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t));
428 pdram_timing->mhz = nmhz;
429 pdram_timing->al = 0;
430 pdram_timing->bl = timing_config->bl;
431
432 /* 1066 933 800 667 533 400 333
433 * RL, 8 7 6 5 4 3 3
434 * WL, 4 4 3 2 2 1 1
435 */
436 if (nmhz <= 266) {
437 pdram_timing->cl = 4;
438 pdram_timing->cwl = 2;
439 pdram_timing->mr[2] = LPDDR2_RL4_WL2;
440 } else if (nmhz <= 333) {
441 pdram_timing->cl = 5;
442 pdram_timing->cwl = 2;
443 pdram_timing->mr[2] = LPDDR2_RL5_WL2;
444 } else if (nmhz <= 400) {
445 pdram_timing->cl = 6;
446 pdram_timing->cwl = 3;
447 pdram_timing->mr[2] = LPDDR2_RL6_WL3;
448 } else if (nmhz <= 466) {
449 pdram_timing->cl = 7;
450 pdram_timing->cwl = 4;
451 pdram_timing->mr[2] = LPDDR2_RL7_WL4;
452 } else {
453 pdram_timing->cl = 8;
454 pdram_timing->cwl = 4;
455 pdram_timing->mr[2] = LPDDR2_RL8_WL4;
456 }
457 switch (timing_config->dramds) {
458 case 120:
459 pdram_timing->mr[3] = LPDDR2_DS_120;
460 break;
461 case 80:
462 pdram_timing->mr[3] = LPDDR2_DS_80;
463 break;
464 case 60:
465 pdram_timing->mr[3] = LPDDR2_DS_60;
466 break;
467 case 48:
468 pdram_timing->mr[3] = LPDDR2_DS_48;
469 break;
470 case 40:
471 pdram_timing->mr[3] = LPDDR2_DS_40;
472 break;
473 case 34:
474 default:
475 pdram_timing->mr[3] = LPDDR2_DS_34;
476 break;
477 }
478 pdram_timing->mr[0] = 0;
479
480 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000;
481 pdram_timing->tinit2 = LPDDR2_TINIT2;
482 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000;
483 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000;
484 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000;
485 pdram_timing->trstl = LPDDR2_TRSTL;
486 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000;
487 /*
488 * tREFI, average periodic refresh interval,
489 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb)
490 */
491 if (ddr_capability_per_die >= 0x10000000)
492 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999)
493 / 1000;
494 else
495 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999)
496 / 1000;
497 /* base timing */
498 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000);
499 pdram_timing->trcd = max(3, tmp);
500 /*
501 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow),
502 */
503 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000);
504 trppb_tmp = max(3, trppb_tmp);
505 pdram_timing->trppb = trppb_tmp;
506 /*
507 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow),
508 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow))
509 */
510 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000);
511 trp_tmp = max(3, trp_tmp);
512 pdram_timing->trp = trp_tmp;
513 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000);
514 twr_tmp = max(3, twr_tmp);
515 pdram_timing->twr = twr_tmp;
516 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 :
517 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4);
518 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp);
519 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
520 pdram_timing->trtp = max(2, tmp);
521 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000);
522 tras_tmp = max(3, tras_tmp);
523 pdram_timing->tras_min = tras_tmp;
524 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000);
525 pdram_timing->trc = (tras_tmp + trp_tmp);
526 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000);
527 pdram_timing->trrd = max(2, tmp);
528 pdram_timing->tccd = LPDDR2_TCCD;
529 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */
530 if (nmhz > 200)
531 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) +
532 999) / 1000);
533 else
534 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000);
535 pdram_timing->twtr = max(2, tmp);
536 pdram_timing->trtw = LPDDR2_TRTW;
537 if (nmhz <= 200)
538 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999)
539 / 1000;
540 else
541 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999)
542 / 1000;
543 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */
544 if (ddr_capability_per_die >= 0x40000000) {
545 pdram_timing->trfc =
546 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000;
547 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000);
548 } else {
549 pdram_timing->trfc =
550 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000;
551 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000);
552 }
553 if (tmp < 2)
554 tmp = 2;
555 pdram_timing->txsr = tmp;
556 pdram_timing->txsnr = tmp;
557 /* tdqsck use rounded down */
558 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1))
559 / 1000);
560 pdram_timing->tdqsck_max =
561 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999)
562 / 1000);
563 /* pd and sr */
564 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
565 pdram_timing->txp = max(2, tmp);
566 pdram_timing->txpdll = LPDDR2_TXPDLL;
567 pdram_timing->tdllk = LPDDR2_TDLLK;
568 pdram_timing->tcke = LPDDR2_TCKE;
569 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000);
570 pdram_timing->tckesr = max(3, tmp);
571 pdram_timing->tcksre = LPDDR2_TCKSRE;
572 pdram_timing->tcksrx = LPDDR2_TCKSRX;
573 /* mode register timing */
574 pdram_timing->tmod = LPDDR2_TMOD;
575 pdram_timing->tmrd = LPDDR2_TMRD;
576 pdram_timing->tmrr = LPDDR2_TMRR;
577 /* ZQ */
578 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000;
579 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000);
580 pdram_timing->tzqcs = max(6, tmp);
581 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000);
582 pdram_timing->tzqoper = max(6, tmp);
583 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000);
584 pdram_timing->tzqreset = max(3, tmp);
585 }
586
587 #define LPDDR3_TINIT1 (100) /* ns */
588 #define LPDDR3_TINIT2 (5) /* tCK */
589 #define LPDDR3_TINIT3 (200000) /* 200us */
590 #define LPDDR3_TINIT4 (1000) /* 1us */
591 #define LPDDR3_TINIT5 (10000) /* 10us */
592 #define LPDDR3_TRSTL (0)
593 #define LPDDR3_TRSTH (0) /* 500us */
594 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */
595
596 /* base timging */
597 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */
598 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */
599 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */
600 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */
601 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */
602 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */
603 #define LPDDR3_TCCD (4) /* tCK */
604 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */
605 #define LPDDR3_TRTW (0) /* tCK register min valid value */
606 #define LPDDR3_TRAS_MAX (70000) /* 70us */
607 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */
608 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */
609 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */
610 #define LPDDR3_TRFC_4GBIT (130) /* ns */
611 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */
612 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */
613
614 /* pd and sr */
615 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */
616 #define LPDDR3_TXPDLL (0)
617 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */
618 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */
619 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */
620 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */
621
622 /* mode register timing */
623 #define LPDDR3_TMOD (0)
624 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */
625 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */
626 #define LPDDR3_TMRRI LPDDR3_TRCD
627
628 /* ODT */
629 #define LPDDR3_TODTON (3) /* 3.5ns */
630
631 /* ZQ */
632 #define LPDDR3_TZQINIT (1000) /* 1us */
633 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */
634 #define LPDDR3_TZQCL (360) /* 360ns */
635 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */
636 /* write leveling */
637 #define LPDDR3_TWLMRD (40) /* ns */
638 #define LPDDR3_TWLO (20) /* ns */
639 #define LPDDR3_TWLDQSEN (25) /* ns */
640 /* CA training */
641 #define LPDDR3_TCACKEL (10) /* tCK */
642 #define LPDDR3_TCAENT (10) /* tCK */
643 #define LPDDR3_TCAMRD (20) /* tCK */
644 #define LPDDR3_TCACKEH (10) /* tCK */
645 #define LPDDR3_TCAEXT (10) /* tCK */
646 #define LPDDR3_TADR (20) /* ns */
647 #define LPDDR3_TMRZ (3) /* ns */
648
649 /* FSP */
650 #define LPDDR3_TFC_LONG (250) /* ns */
651
652 /*
653 * Description: depend on input parameter "timing_config",
654 * and calculate all lpddr3
655 * spec timing to "pdram_timing"
656 * parameters:
657 * input: timing_config
658 * output: pdram_timing
659 */
lpddr3_get_parameter(struct timing_related_config * timing_config,struct dram_timing_t * pdram_timing)660 static void lpddr3_get_parameter(struct timing_related_config *timing_config,
661 struct dram_timing_t *pdram_timing)
662 {
663 uint32_t nmhz = timing_config->freq;
664 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config);
665 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp;
666
667 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t));
668 pdram_timing->mhz = nmhz;
669 pdram_timing->al = 0;
670 pdram_timing->bl = timing_config->bl;
671
672 /*
673 * Only support Write Latency Set A here
674 * 1066 933 800 733 667 600 533 400 166
675 * RL, 16 14 12 11 10 9 8 6 3
676 * WL, 8 8 6 6 6 5 4 3 1
677 */
678 if (nmhz <= 400) {
679 pdram_timing->cl = 6;
680 pdram_timing->cwl = 3;
681 pdram_timing->mr[2] = LPDDR3_RL6_WL3;
682 } else if (nmhz <= 533) {
683 pdram_timing->cl = 8;
684 pdram_timing->cwl = 4;
685 pdram_timing->mr[2] = LPDDR3_RL8_WL4;
686 } else if (nmhz <= 600) {
687 pdram_timing->cl = 9;
688 pdram_timing->cwl = 5;
689 pdram_timing->mr[2] = LPDDR3_RL9_WL5;
690 } else if (nmhz <= 667) {
691 pdram_timing->cl = 10;
692 pdram_timing->cwl = 6;
693 pdram_timing->mr[2] = LPDDR3_RL10_WL6;
694 } else if (nmhz <= 733) {
695 pdram_timing->cl = 11;
696 pdram_timing->cwl = 6;
697 pdram_timing->mr[2] = LPDDR3_RL11_WL6;
698 } else if (nmhz <= 800) {
699 pdram_timing->cl = 12;
700 pdram_timing->cwl = 6;
701 pdram_timing->mr[2] = LPDDR3_RL12_WL6;
702 } else if (nmhz <= 933) {
703 pdram_timing->cl = 14;
704 pdram_timing->cwl = 8;
705 pdram_timing->mr[2] = LPDDR3_RL14_WL8;
706 } else {
707 pdram_timing->cl = 16;
708 pdram_timing->cwl = 8;
709 pdram_timing->mr[2] = LPDDR3_RL16_WL8;
710 }
711 switch (timing_config->dramds) {
712 case 80:
713 pdram_timing->mr[3] = LPDDR3_DS_80;
714 break;
715 case 60:
716 pdram_timing->mr[3] = LPDDR3_DS_60;
717 break;
718 case 48:
719 pdram_timing->mr[3] = LPDDR3_DS_48;
720 break;
721 case 40:
722 pdram_timing->mr[3] = LPDDR3_DS_40;
723 break;
724 case 3440:
725 pdram_timing->mr[3] = LPDDR3_DS_34D_40U;
726 break;
727 case 4048:
728 pdram_timing->mr[3] = LPDDR3_DS_40D_48U;
729 break;
730 case 3448:
731 pdram_timing->mr[3] = LPDDR3_DS_34D_48U;
732 break;
733 case 34:
734 default:
735 pdram_timing->mr[3] = LPDDR3_DS_34;
736 break;
737 }
738 pdram_timing->mr[0] = 0;
739 if (timing_config->odt)
740 switch (timing_config->dramodt) {
741 case 60:
742 pdram_timing->mr11 = LPDDR3_ODT_60;
743 break;
744 case 120:
745 pdram_timing->mr11 = LPDDR3_ODT_120;
746 break;
747 case 240:
748 default:
749 pdram_timing->mr11 = LPDDR3_ODT_240;
750 break;
751 }
752 else
753 pdram_timing->mr11 = LPDDR3_ODT_DIS;
754
755 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000;
756 pdram_timing->tinit2 = LPDDR3_TINIT2;
757 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000;
758 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000;
759 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000;
760 pdram_timing->trstl = LPDDR3_TRSTL;
761 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000;
762 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */
763 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000;
764 /* base timing */
765 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000);
766 pdram_timing->trcd = max(3, tmp);
767 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000);
768 trppb_tmp = max(3, trppb_tmp);
769 pdram_timing->trppb = trppb_tmp;
770 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000);
771 trp_tmp = max(3, trp_tmp);
772 pdram_timing->trp = trp_tmp;
773 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000);
774 twr_tmp = max(4, twr_tmp);
775 pdram_timing->twr = twr_tmp;
776 if (twr_tmp <= 6)
777 twr_tmp = 6;
778 else if (twr_tmp <= 8)
779 twr_tmp = 8;
780 else if (twr_tmp <= 12)
781 twr_tmp = twr_tmp;
782 else if (twr_tmp <= 14)
783 twr_tmp = 14;
784 else
785 twr_tmp = 16;
786 if (twr_tmp > 9)
787 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/
788 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2);
789 bl_tmp = LPDDR3_BL8;
790 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp);
791 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
792 pdram_timing->trtp = max(4, tmp);
793 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000);
794 tras_tmp = max(3, tras_tmp);
795 pdram_timing->tras_min = tras_tmp;
796 pdram_timing->trc = (tras_tmp + trp_tmp);
797 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000);
798 pdram_timing->trrd = max(2, tmp);
799 pdram_timing->tccd = LPDDR3_TCCD;
800 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000);
801 pdram_timing->twtr = max(4, tmp);
802 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000);
803 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000);
804 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000;
805 pdram_timing->tfaw = max(8, tmp);
806 if (ddr_capability_per_die > 0x20000000) {
807 pdram_timing->trfc =
808 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000;
809 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000);
810 } else {
811 pdram_timing->trfc =
812 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000;
813 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000);
814 }
815 pdram_timing->txsr = max(2, tmp);
816 pdram_timing->txsnr = max(2, tmp);
817 /* tdqsck use rounded down */
818 pdram_timing->tdqsck =
819 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1))
820 / 1000);
821 pdram_timing->tdqsck_max =
822 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999)
823 / 1000);
824 /*pd and sr*/
825 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
826 pdram_timing->txp = max(3, tmp);
827 pdram_timing->txpdll = LPDDR3_TXPDLL;
828 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000);
829 pdram_timing->tcke = max(3, tmp);
830 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000);
831 pdram_timing->tckesr = max(3, tmp);
832 pdram_timing->tcksre = LPDDR3_TCKSRE;
833 pdram_timing->tcksrx = LPDDR3_TCKSRX;
834 /*mode register timing*/
835 pdram_timing->tmod = LPDDR3_TMOD;
836 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000);
837 pdram_timing->tmrd = max(10, tmp);
838 pdram_timing->tmrr = LPDDR3_TMRR;
839 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000);
840 pdram_timing->tmrri = max(3, tmp);
841 /* ODT */
842 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999)
843 / 1000;
844 /* ZQ */
845 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000;
846 pdram_timing->tzqcs =
847 ((LPDDR3_TZQCS * nmhz + 999) / 1000);
848 pdram_timing->tzqoper =
849 ((LPDDR3_TZQCL * nmhz + 999) / 1000);
850 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000);
851 pdram_timing->tzqreset = max(3, tmp);
852 /* write leveling */
853 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000;
854 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000;
855 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000;
856 /* CA training */
857 pdram_timing->tcackel = LPDDR3_TCACKEL;
858 pdram_timing->tcaent = LPDDR3_TCAENT;
859 pdram_timing->tcamrd = LPDDR3_TCAMRD;
860 pdram_timing->tcackeh = LPDDR3_TCACKEH;
861 pdram_timing->tcaext = LPDDR3_TCAEXT;
862 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000;
863 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000;
864 pdram_timing->tcacd = pdram_timing->tadr + 2;
865
866 /* FSP */
867 pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000;
868 }
869
870 #define LPDDR4_TINIT1 (200000) /* 200us */
871 #define LPDDR4_TINIT2 (10) /* 10ns */
872 #define LPDDR4_TINIT3 (2000000) /* 2ms */
873 #define LPDDR4_TINIT4 (5) /* tCK */
874 #define LPDDR4_TINIT5 (2000) /* 2us */
875 #define LPDDR4_TRSTL LPDDR4_TINIT1
876 #define LPDDR4_TRSTH LPDDR4_TINIT3
877 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */
878
879 /* base timging */
880 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */
881 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */
882 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */
883 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */
884 #define LPDDR4_TCCD_BL16 (8) /* tCK */
885 #define LPDDR4_TCCD_BL32 (16) /* tCK */
886 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */
887 #define LPDDR4_TRTW (0) /* tCK register min valid value */
888 #define LPDDR4_TRAS_MAX (70000) /* 70us */
889 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */
890 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */
891 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */
892 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */
893 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */
894 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */
895 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */
896 #define LPDDR4_TPPD (4) /* tCK */
897
898 /* pd and sr */
899 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */
900 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */
901 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */
902 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */
903 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */
904 #define LPDDR4_TCSCKE (1) /* 1.75ns */
905 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */
906 #define LPDDR4_TCSCKEH (1) /* 1.75ns */
907 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */
908 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */
909 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */
910 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */
911 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */
912 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */
913
914 /* mode register timing */
915 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */
916 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */
917
918 /* ODT */
919 #define LPDDR4_TODTON (3) /* 3.5ns */
920
921 /* ZQ */
922 #define LPDDR4_TZQCAL (1000) /* 1us */
923 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */
924 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */
925 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */
926
927 /* write leveling */
928 #define LPDDR4_TWLMRD (40) /* tCK */
929 #define LPDDR4_TWLO (20) /* ns */
930 #define LPDDR4_TWLDQSEN (20) /* tCK */
931
932 /* CA training */
933 #define LPDDR4_TCAENT (250) /* ns */
934 #define LPDDR4_TADR (20) /* ns */
935 #define LPDDR4_TMRZ (1) /* 1.5ns */
936 #define LPDDR4_TVREF_LONG (250) /* ns */
937 #define LPDDR4_TVREF_SHORT (100) /* ns */
938
939 /* VRCG */
940 #define LPDDR4_TVRCG_ENABLE (200) /* ns */
941 #define LPDDR4_TVRCG_DISABLE (100) /* ns */
942
943 /* FSP */
944 #define LPDDR4_TFC_LONG (250) /* ns */
945 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */
946 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */
947
948 /*
949 * Description: depend on input parameter "timing_config",
950 * and calculate all lpddr4
951 * spec timing to "pdram_timing"
952 * parameters:
953 * input: timing_config
954 * output: pdram_timing
955 */
lpddr4_get_parameter(struct timing_related_config * timing_config,struct dram_timing_t * pdram_timing)956 static void lpddr4_get_parameter(struct timing_related_config *timing_config,
957 struct dram_timing_t *pdram_timing)
958 {
959 uint32_t nmhz = timing_config->freq;
960 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config);
961 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp;
962
963 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t));
964 pdram_timing->mhz = nmhz;
965 pdram_timing->al = 0;
966 pdram_timing->bl = timing_config->bl;
967
968 /*
969 * Only support Write Latency Set A here
970 * 2133 1866 1600 1333 1066 800 533 266
971 * RL, 36 32 28 24 20 14 10 6
972 * WL, 18 16 14 12 10 8 6 4
973 * nWR, 40 34 30 24 20 16 10 6
974 * nRTP,16 14 12 10 8 8 8 8
975 */
976 tmp = (timing_config->bl == 32) ? 1 : 0;
977
978 /*
979 * we always use WR preamble = 2tCK
980 * RD preamble = Static
981 */
982 tmp |= (1 << 2);
983 if (nmhz <= 266) {
984 pdram_timing->cl = 6;
985 pdram_timing->cwl = 4;
986 pdram_timing->twr = 6;
987 pdram_timing->trtp = 8;
988 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4;
989 } else if (nmhz <= 533) {
990 if (timing_config->rdbi) {
991 pdram_timing->cl = 12;
992 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6;
993 } else {
994 pdram_timing->cl = 10;
995 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6;
996 }
997 pdram_timing->cwl = 6;
998 pdram_timing->twr = 10;
999 pdram_timing->trtp = 8;
1000 tmp |= (1 << 4);
1001 } else if (nmhz <= 800) {
1002 if (timing_config->rdbi) {
1003 pdram_timing->cl = 16;
1004 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8;
1005 } else {
1006 pdram_timing->cl = 14;
1007 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8;
1008 }
1009 pdram_timing->cwl = 8;
1010 pdram_timing->twr = 16;
1011 pdram_timing->trtp = 8;
1012 tmp |= (2 << 4);
1013 } else if (nmhz <= 1066) {
1014 if (timing_config->rdbi) {
1015 pdram_timing->cl = 22;
1016 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10;
1017 } else {
1018 pdram_timing->cl = 20;
1019 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10;
1020 }
1021 pdram_timing->cwl = 10;
1022 pdram_timing->twr = 20;
1023 pdram_timing->trtp = 8;
1024 tmp |= (3 << 4);
1025 } else if (nmhz <= 1333) {
1026 if (timing_config->rdbi) {
1027 pdram_timing->cl = 28;
1028 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 |
1029 LPDDR4_A_WL12;
1030 } else {
1031 pdram_timing->cl = 24;
1032 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 |
1033 LPDDR4_A_WL12;
1034 }
1035 pdram_timing->cwl = 12;
1036 pdram_timing->twr = 24;
1037 pdram_timing->trtp = 10;
1038 tmp |= (4 << 4);
1039 } else if (nmhz <= 1600) {
1040 if (timing_config->rdbi) {
1041 pdram_timing->cl = 32;
1042 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 |
1043 LPDDR4_A_WL14;
1044 } else {
1045 pdram_timing->cl = 28;
1046 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 |
1047 LPDDR4_A_WL14;
1048 }
1049 pdram_timing->cwl = 14;
1050 pdram_timing->twr = 30;
1051 pdram_timing->trtp = 12;
1052 tmp |= (5 << 4);
1053 } else if (nmhz <= 1866) {
1054 if (timing_config->rdbi) {
1055 pdram_timing->cl = 36;
1056 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 |
1057 LPDDR4_A_WL16;
1058 } else {
1059 pdram_timing->cl = 32;
1060 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 |
1061 LPDDR4_A_WL16;
1062 }
1063 pdram_timing->cwl = 16;
1064 pdram_timing->twr = 34;
1065 pdram_timing->trtp = 14;
1066 tmp |= (6 << 4);
1067 } else {
1068 if (timing_config->rdbi) {
1069 pdram_timing->cl = 40;
1070 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 |
1071 LPDDR4_A_WL18;
1072 } else {
1073 pdram_timing->cl = 36;
1074 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 |
1075 LPDDR4_A_WL18;
1076 }
1077 pdram_timing->cwl = 18;
1078 pdram_timing->twr = 40;
1079 pdram_timing->trtp = 16;
1080 tmp |= (7 << 4);
1081 }
1082 pdram_timing->mr[1] = tmp;
1083 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) |
1084 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0);
1085 switch (timing_config->dramds) {
1086 case 240:
1087 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp;
1088 break;
1089 case 120:
1090 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp;
1091 break;
1092 case 80:
1093 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp;
1094 break;
1095 case 60:
1096 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp;
1097 break;
1098 case 48:
1099 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp;
1100 break;
1101 case 40:
1102 default:
1103 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp;
1104 break;
1105 }
1106 pdram_timing->mr[0] = 0;
1107 if (timing_config->odt) {
1108 switch (timing_config->dramodt) {
1109 case 240:
1110 tmp = LPDDR4_DQODT_240;
1111 break;
1112 case 120:
1113 tmp = LPDDR4_DQODT_120;
1114 break;
1115 case 80:
1116 tmp = LPDDR4_DQODT_80;
1117 break;
1118 case 60:
1119 tmp = LPDDR4_DQODT_60;
1120 break;
1121 case 48:
1122 tmp = LPDDR4_DQODT_48;
1123 break;
1124 case 40:
1125 default:
1126 tmp = LPDDR4_DQODT_40;
1127 break;
1128 }
1129
1130 switch (timing_config->caodt) {
1131 case 240:
1132 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
1133 break;
1134 case 120:
1135 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
1136 break;
1137 case 80:
1138 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
1139 break;
1140 case 60:
1141 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
1142 break;
1143 case 48:
1144 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
1145 break;
1146 case 40:
1147 default:
1148 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
1149 break;
1150 }
1151 } else {
1152 pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp;
1153 }
1154
1155 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000;
1156 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000;
1157 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000;
1158 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000;
1159 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000;
1160 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000;
1161 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000;
1162 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */
1163 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000;
1164 /* base timing */
1165 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000);
1166 pdram_timing->trcd = max(4, tmp);
1167 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000);
1168 trppb_tmp = max(4, trppb_tmp);
1169 pdram_timing->trppb = trppb_tmp;
1170 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000);
1171 trp_tmp = max(4, trp_tmp);
1172 pdram_timing->trp = trp_tmp;
1173 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000);
1174 tras_tmp = max(3, tras_tmp);
1175 pdram_timing->tras_min = tras_tmp;
1176 pdram_timing->trc = (tras_tmp + trp_tmp);
1177 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000);
1178 pdram_timing->trrd = max(4, tmp);
1179 if (timing_config->bl == 32)
1180 pdram_timing->tccd = LPDDR4_TCCD_BL16;
1181 else
1182 pdram_timing->tccd = LPDDR4_TCCD_BL32;
1183 pdram_timing->tccdmw = 4 * pdram_timing->tccd;
1184 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000);
1185 pdram_timing->twtr = max(8, tmp);
1186 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000);
1187 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000);
1188 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000;
1189 if (ddr_capability_per_die > 0x60000000) {
1190 /* >= 12Gb */
1191 pdram_timing->trfc =
1192 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000;
1193 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) +
1194 999) / 1000);
1195 } else if (ddr_capability_per_die > 0x30000000) {
1196 pdram_timing->trfc =
1197 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000;
1198 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) +
1199 999) / 1000);
1200 } else {
1201 pdram_timing->trfc =
1202 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000;
1203 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) +
1204 999) / 1000);
1205 }
1206 pdram_timing->txsr = max(2, tmp);
1207 pdram_timing->txsnr = max(2, tmp);
1208 /* tdqsck use rounded down */
1209 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz +
1210 (nmhz >> 1)) / 1000);
1211 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz +
1212 (nmhz >> 1) + 999) / 1000);
1213 pdram_timing->tppd = LPDDR4_TPPD;
1214 /* pd and sr */
1215 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
1216 pdram_timing->txp = max(5, tmp);
1217 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000);
1218 pdram_timing->tcke = max(4, tmp);
1219 tmp = ((LPDDR4_TESCKE * nmhz +
1220 ((nmhz * 3) / 4) +
1221 999) / 1000);
1222 pdram_timing->tescke = max(3, tmp);
1223 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000);
1224 pdram_timing->tsr = max(3, tmp);
1225 tmp = ((LPDDR4_TCMDCKE * nmhz +
1226 ((nmhz * 3) / 4) +
1227 999) / 1000);
1228 pdram_timing->tcmdcke = max(3, tmp);
1229 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz +
1230 ((nmhz * 3) / 4) +
1231 999) / 1000);
1232 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000);
1233 pdram_timing->tckelcs = max(5, tmp);
1234 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz +
1235 ((nmhz * 3) / 4) +
1236 999) / 1000);
1237 tmp = ((LPDDR4_TCKEHCS * nmhz +
1238 (nmhz >> 1) + 999) / 1000);
1239 pdram_timing->tckehcs = max(5, tmp);
1240 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000);
1241 pdram_timing->tmrwckel = max(10, tmp);
1242 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) +
1243 999) / 1000);
1244 pdram_timing->tckelcmd = max(3, tmp);
1245 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) +
1246 999) / 1000);
1247 pdram_timing->tckehcmd = max(3, tmp);
1248 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) +
1249 999) / 1000);
1250 pdram_timing->tckelpd = max(3, tmp);
1251 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) +
1252 999) / 1000);
1253 pdram_timing->tckckel = max(3, tmp);
1254 /* mode register timing */
1255 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000);
1256 pdram_timing->tmrd = max(10, tmp);
1257 pdram_timing->tmrr = LPDDR4_TMRR;
1258 pdram_timing->tmrri = pdram_timing->trcd + 3;
1259 /* ODT */
1260 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999)
1261 / 1000;
1262 /* ZQ */
1263 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000;
1264 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000);
1265 pdram_timing->tzqlat = max(8, tmp);
1266 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000);
1267 pdram_timing->tzqreset = max(3, tmp);
1268 tmp = ((LPDDR4_TZQCKE * nmhz +
1269 ((nmhz * 3) / 4) +
1270 999) / 1000);
1271 pdram_timing->tzqcke = max(3, tmp);
1272 /* write leveling */
1273 pdram_timing->twlmrd = LPDDR4_TWLMRD;
1274 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000;
1275 pdram_timing->twldqsen = LPDDR4_TWLDQSEN;
1276 /* CA training */
1277 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000;
1278 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000;
1279 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000;
1280 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000;
1281 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000;
1282 /* VRCG */
1283 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz +
1284 999) / 1000;
1285 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz +
1286 999) / 1000;
1287 /* FSP */
1288 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000;
1289 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000;
1290 pdram_timing->tckfspe = max(4, tmp);
1291 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000;
1292 pdram_timing->tckfspx = max(4, tmp);
1293 }
1294
1295 /*
1296 * Description: depend on input parameter "timing_config",
1297 * and calculate correspond "dram_type"
1298 * spec timing to "pdram_timing"
1299 * parameters:
1300 * input: timing_config
1301 * output: pdram_timing
1302 * NOTE: MR ODT is set, need to disable by controller
1303 */
dram_get_parameter(struct timing_related_config * timing_config,struct dram_timing_t * pdram_timing)1304 void dram_get_parameter(struct timing_related_config *timing_config,
1305 struct dram_timing_t *pdram_timing)
1306 {
1307 switch (timing_config->dram_type) {
1308 case DDR3:
1309 ddr3_get_parameter(timing_config, pdram_timing);
1310 break;
1311 case LPDDR2:
1312 lpddr2_get_parameter(timing_config, pdram_timing);
1313 break;
1314 case LPDDR3:
1315 lpddr3_get_parameter(timing_config, pdram_timing);
1316 break;
1317 case LPDDR4:
1318 lpddr4_get_parameter(timing_config, pdram_timing);
1319 break;
1320 default:
1321 /* Do nothing in default case */
1322 break;
1323 }
1324 }
1325
