1/*
2 * Copyright (c) 2021 Katsuhiro Suzuki
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <freq.h>
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
14	model = "sifive,FU740";
15
16	clocks {
17		coreclk: core-clk {
18			#clock-cells = <0>;
19			compatible = "fixed-clock";
20			clock-frequency = <DT_FREQ_M(1000)>;
21		};
22
23		pclk: p-clk {
24			#clock-cells = <0>;
25			compatible = "fixed-clock";
26			clock-frequency = <DT_FREQ_K(125125)>;
27		};
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			compatible = "sifive,s7", "riscv";
36			device_type = "cpu";
37			reg = <0>;
38			riscv,isa = "rv64imac_zicsr_zifencei";
39			status = "okay";
40
41			hlic0: interrupt-controller {
42				compatible = "riscv,cpu-intc";
43				#address-cells = <0>;
44				#interrupt-cells = <1>;
45				interrupt-controller;
46			};
47		};
48		cpu1: cpu@1 {
49			compatible = "sifive,u74", "riscv";
50			device_type = "cpu";
51			mmu-type = "riscv,sv39";
52			reg = <0x1>;
53			riscv,isa = "rv64gc";
54
55			hlic1: interrupt-controller {
56				compatible = "riscv,cpu-intc";
57				#address-cells = <0>;
58				#interrupt-cells = <1>;
59				interrupt-controller;
60			};
61		};
62		cpu2: cpu@2 {
63			compatible = "sifive,u74", "riscv";
64			device_type = "cpu";
65			mmu-type = "riscv,sv39";
66			reg = <0x2>;
67			riscv,isa = "rv64gc";
68
69			hlic2: interrupt-controller {
70				compatible = "riscv,cpu-intc";
71				#address-cells = <0>;
72				#interrupt-cells = <1>;
73				interrupt-controller;
74			};
75		};
76		cpu3: cpu@3 {
77			compatible = "sifive,u74", "riscv";
78			device_type = "cpu";
79			mmu-type = "riscv,sv39";
80			reg = <0x3>;
81			riscv,isa = "rv64gc";
82
83			hlic3: interrupt-controller {
84				compatible = "riscv,cpu-intc";
85				#address-cells = <0>;
86				#interrupt-cells = <1>;
87				interrupt-controller;
88			};
89		};
90		cpu4: cpu@4 {
91			compatible = "sifive,u74", "riscv";
92			device_type = "cpu";
93			mmu-type = "riscv,sv39";
94			reg = <0x4>;
95			riscv,isa = "rv64gc";
96
97			hlic4: interrupt-controller {
98				compatible = "riscv,cpu-intc";
99				#address-cells = <0>;
100				#interrupt-cells = <1>;
101				interrupt-controller;
102			};
103		};
104	};
105
106	soc {
107		#address-cells = <2>;
108		#size-cells = <2>;
109		compatible = "fu740-soc", "sifive-soc", "simple-bus";
110		ranges;
111
112		modeselect: rom@1000 {
113			compatible = "sifive,modeselect0";
114			reg = <0x0 0x1000 0x0 0x1000>;
115			reg-names = "mem";
116		};
117
118		maskrom: rom@10000 {
119			compatible = "sifive,maskrom0";
120			reg = <0x0 0x10000 0x0 0x8000>;
121			reg-names = "mem";
122		};
123
124		dtim: dtim@1000000 {
125			compatible = "sifive,dtim0";
126			reg = <0x0 0x1000000 0x0 0x2000>;
127			reg-names = "mem";
128		};
129
130		clint: clint@2000000 {
131			compatible = "sifive,clint0";
132			interrupts-extended = <&hlic0 3 &hlic0 7
133				&hlic1 3 &hlic1 7
134				&hlic2 3 &hlic2 7
135				&hlic3 3 &hlic3 7
136				&hlic4 3 &hlic4 7>;
137			reg = <0x0 0x2000000 0x0 0x10000>;
138		};
139
140		mtimer: timer@200bff8 {
141			compatible = "riscv,machine-timer";
142			interrupts-extended = <&hlic0 7
143						&hlic1 7
144						&hlic2 7
145						&hlic3 7
146						&hlic4 7>;
147			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
148			reg-names = "mtime", "mtimecmp";
149		};
150
151		l2lim: l2lim@8000000 {
152			compatible = "sifive,l2lim0";
153			reg = <0x0 0x8000000 0x0 0x200000>;
154			reg-names = "mem";
155		};
156
157		plic: interrupt-controller@c000000 {
158			compatible = "sifive,plic-1.0.0";
159			#address-cells = <0>;
160			#interrupt-cells = <2>;
161			interrupt-controller;
162			interrupts-extended = <&hlic0 11
163				&hlic1 11
164				&hlic2 11
165				&hlic3 11
166				&hlic4 11>;
167			reg = <0x0 0x0c000000 0x0 0x04000000>;
168			riscv,max-priority = <7>;
169			riscv,ndev = <52>;
170		};
171
172		uart0: serial@10010000 {
173			compatible = "sifive,uart0";
174			interrupt-parent = <&plic>;
175			interrupts = <39 1>;
176			reg = <0x0 0x10010000 0x0 0x1000>;
177			reg-names = "control";
178			status = "disabled";
179		};
180
181		uart1: serial@10011000 {
182			compatible = "sifive,uart0";
183			interrupt-parent = <&plic>;
184			interrupts = <40 1>;
185			reg = <0x0 0x10011000 0x0 0x1000>;
186			reg-names = "control";
187			status = "disabled";
188		};
189
190		spi0: spi@10040000 {
191			compatible = "sifive,spi0";
192			interrupt-parent = <&plic>;
193			interrupts = <41 1>;
194			reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
195			reg-names = "control", "mem";
196			status = "disabled";
197			#address-cells = <1>;
198			#size-cells = <0>;
199		};
200
201		spi1: spi@10041000 {
202			compatible = "sifive,spi0";
203			interrupt-parent = <&plic>;
204			interrupts = <42 1>;
205			reg = <0x0 0x10041000 0x0 0x1000>;
206			reg-names = "control";
207			status = "disabled";
208			#address-cells = <1>;
209			#size-cells = <0>;
210		};
211
212		spi2: spi@10050000 {
213			compatible = "sifive,spi0";
214			interrupt-parent = <&plic>;
215			interrupts = <43 1>;
216			reg = <0x0 0x10050000 0x0 0x1000>;
217			reg-names = "control";
218			status = "disabled";
219			#address-cells = <1>;
220			#size-cells = <0>;
221		};
222		dmc: dmc@100b0000 {
223			compatible = "sifive,fu740-c000-ddr";
224			reg = <0x0 0x100b0000 0x0 0x0800
225			       0x0 0x100b2000 0x0 0x2000
226			       0x0 0x100b8000 0x0 0x1000>;
227			status = "disabled";
228		};
229	};
230};
231