1 /*
2  * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 #include <stdint.h>
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13 
14 /** Interrupt Registers */
15 /** Type of dma_int_raw register
16  *  Raw interrupt status
17  */
18 typedef union {
19     struct {
20         /** dma_in_done_int_raw : RO; bitpos: [0]; default: 0;
21          *  This is the interrupt raw bit. Triggered when the last data of frame is received or
22          *  the receive buffer is full indicated by inlink descriptor.
23          */
24         uint32_t dma_in_done_int_raw: 1;
25         /** dma_in_suc_eof_int_raw : RO; bitpos: [1]; default: 0;
26          *  This is the interrupt raw bit. Triggered when the last data of one frame is
27          *  received.
28          */
29         uint32_t dma_in_suc_eof_int_raw: 1;
30         /** dma_out_done_int_raw : RO; bitpos: [2]; default: 0;
31          *  This is the interrupt raw bit. Triggered when all data indicated by one outlink
32          *  descriptor has been pushed into Tx FIFO.
33          */
34         uint32_t dma_out_done_int_raw: 1;
35         /** dma_out_eof_int_raw : RO; bitpos: [3]; default: 0;
36          *  This is the interrupt raw bit. Triggered when the last data with EOF flag has been
37          *  pushed into Tx FIFO.
38          */
39         uint32_t dma_out_eof_int_raw: 1;
40         /** dma_in_dscr_err_int_raw : RO; bitpos: [4]; default: 0;
41          *  This is the interrupt raw bit. Triggered when detecting inlink descriptor error,
42          *  including owner error, the second and third word error of inlink descriptor.
43          */
44         uint32_t dma_in_dscr_err_int_raw: 1;
45         /** dma_out_dscr_err_int_raw : RO; bitpos: [5]; default: 0;
46          *  This is the interrupt raw bit. Triggered when detecting outlink descriptor error,
47          *  including owner error, the second and third word error of outlink descriptor.
48          */
49         uint32_t dma_out_dscr_err_int_raw: 1;
50         /** dma_in_dscr_empty_int_raw : RO; bitpos: [6]; default: 0;
51          *  This is the interrupt raw bit. Triggered when receiving data is completed and no
52          *  more inlink descriptor.
53          */
54         uint32_t dma_in_dscr_empty_int_raw: 1;
55         /** dma_out_total_eof_int_raw : RO; bitpos: [7]; default: 0;
56          *  This is the interrupt raw bit. Triggered when data corresponding to all outlink
57          *  descriptor and the last descriptor with valid EOF is transmitted out.
58          */
59         uint32_t dma_out_total_eof_int_raw: 1;
60         /** dma_crc_done_int_raw : RO; bitpos: [8]; default: 0;
61          *  This is the interrupt raw bit. Triggered when crc calculation is done.
62          */
63         uint32_t dma_crc_done_int_raw: 1;
64         uint32_t reserved9: 23;
65     };
66     uint32_t val;
67 } cp_dma_int_raw_reg_t;
68 
69 /** Type of dma_int_st register
70  *  Masked interrupt status
71  */
72 typedef union {
73     struct {
74         /** dma_in_done_int_st : RO; bitpos: [0]; default: 0;
75          *  This is the masked interrupt bit for cp_in_done_int interrupt when
76          *  cp_in_done_int_ena is set to 1.
77          */
78         uint32_t dma_in_done_int_st: 1;
79         /** dma_in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
80          *  This is the masked interrupt bit for cp_in_suc_eof_int interrupt when
81          *  cp_in_suc_eof_int_ena is set to 1.
82          */
83         uint32_t dma_in_suc_eof_int_st: 1;
84         /** dma_out_done_int_st : RO; bitpos: [2]; default: 0;
85          *  This is the masked interrupt bit for cp_out_done_int interrupt when
86          *  cp_out_done_int_ena is set to 1.
87          */
88         uint32_t dma_out_done_int_st: 1;
89         /** dma_out_eof_int_st : RO; bitpos: [3]; default: 0;
90          *  This is the masked interrupt bit for cp_out_eof_int interrupt when
91          *  cp_out_eof_int_ena is set to 1.
92          */
93         uint32_t dma_out_eof_int_st: 1;
94         /** dma_in_dscr_err_int_st : RO; bitpos: [4]; default: 0;
95          *  This is the masked interrupt bit for cp_in_dscr_err_int interrupt when
96          *  cp_in_dscr_err_int_ena is set to 1.
97          */
98         uint32_t dma_in_dscr_err_int_st: 1;
99         /** dma_out_dscr_err_int_st : RO; bitpos: [5]; default: 0;
100          *  This is the masked interrupt bit for cp_out_dscr_err_int interrupt when
101          *  cp_out_dscr_err_int_ena is set to 1.
102          */
103         uint32_t dma_out_dscr_err_int_st: 1;
104         /** dma_in_dscr_empty_int_st : RO; bitpos: [6]; default: 0;
105          *  This is the masked interrupt bit for cp_in_dscr_empty_int interrupt when
106          *  cp_in_dscr_empty_int_ena is set to 1.
107          */
108         uint32_t dma_in_dscr_empty_int_st: 1;
109         /** dma_out_total_eof_int_st : RO; bitpos: [7]; default: 0;
110          *  This is the masked interrupt bit for cp_out_total_eof_int interrupt when
111          *  cp_out_total_eof_int_ena is set to 1.
112          */
113         uint32_t dma_out_total_eof_int_st: 1;
114         /** dma_crc_done_int_st : RO; bitpos: [8]; default: 0;
115          *  This is the masked interrupt bit for cp_crc_done_int interrupt when
116          *  cp_crc_done_int_ena is set to 1.
117          */
118         uint32_t dma_crc_done_int_st: 1;
119         uint32_t reserved9: 23;
120     };
121     uint32_t val;
122 } cp_dma_int_st_reg_t;
123 
124 /** Type of dma_int_ena register
125  *  Interrupt enable bits
126  */
127 typedef union {
128     struct {
129         /** dma_in_done_int_ena : R/W; bitpos: [0]; default: 0;
130          *  This is the interrupt enable bit for cp_in_done_int interrupt.
131          */
132         uint32_t dma_in_done_int_ena: 1;
133         /** dma_in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
134          *  This is the interrupt enable bit for cp_in_suc_eof_int interrupt.
135          */
136         uint32_t dma_in_suc_eof_int_ena: 1;
137         /** dma_out_done_int_ena : R/W; bitpos: [2]; default: 0;
138          *  This is the interrupt enable bit for cp_out_done_int interrupt.
139          */
140         uint32_t dma_out_done_int_ena: 1;
141         /** dma_out_eof_int_ena : R/W; bitpos: [3]; default: 0;
142          *  This is the interrupt enable bit for cp_out_eof_int interrupt.
143          */
144         uint32_t dma_out_eof_int_ena: 1;
145         /** dma_in_dscr_err_int_ena : R/W; bitpos: [4]; default: 0;
146          *  This is the interrupt enable bit for cp_in_dscr_err_int interrupt.
147          */
148         uint32_t dma_in_dscr_err_int_ena: 1;
149         /** dma_out_dscr_err_int_ena : R/W; bitpos: [5]; default: 0;
150          *  This is the interrupt enable bit for cp_out_dscr_err_int interrupt.
151          */
152         uint32_t dma_out_dscr_err_int_ena: 1;
153         /** dma_in_dscr_empty_int_ena : R/W; bitpos: [6]; default: 0;
154          *  This is the interrupt enable bit for cp_in_dscr_empty_int interrupt.
155          */
156         uint32_t dma_in_dscr_empty_int_ena: 1;
157         /** dma_out_total_eof_int_ena : R/W; bitpos: [7]; default: 0;
158          *  This is the interrupt enable bit for cp_out_total_eof_int interrupt.
159          */
160         uint32_t dma_out_total_eof_int_ena: 1;
161         /** dma_crc_done_int_ena : R/W; bitpos: [8]; default: 0;
162          *  This is the interrupt enable bit for cp_crc_done_int interrupt.
163          */
164         uint32_t dma_crc_done_int_ena: 1;
165         uint32_t reserved9: 23;
166     };
167     uint32_t val;
168 } cp_dma_int_ena_reg_t;
169 
170 /** Type of dma_int_clr register
171  *  Interrupt clear bits
172  */
173 typedef union {
174     struct {
175         /** dma_in_done_int_clr : WO; bitpos: [0]; default: 0;
176          *  Set this bit to clear cp_in_done_int interrupt.
177          */
178         uint32_t dma_in_done_int_clr: 1;
179         /** dma_in_suc_eof_int_clr : WO; bitpos: [1]; default: 0;
180          *  Set this bit to clear cp_in_suc_eof_int interrupt.
181          */
182         uint32_t dma_in_suc_eof_int_clr: 1;
183         /** dma_out_done_int_clr : WO; bitpos: [2]; default: 0;
184          *  Set this bit to clear cp_out_done_int interrupt.
185          */
186         uint32_t dma_out_done_int_clr: 1;
187         /** dma_out_eof_int_clr : WO; bitpos: [3]; default: 0;
188          *  Set this bit to clear cp_out_eof_int interrupt.
189          */
190         uint32_t dma_out_eof_int_clr: 1;
191         /** dma_in_dscr_err_int_clr : WO; bitpos: [4]; default: 0;
192          *  Set this bit to clear cp_in_dscr_err_int interrupt.
193          */
194         uint32_t dma_in_dscr_err_int_clr: 1;
195         /** dma_out_dscr_err_int_clr : WO; bitpos: [5]; default: 0;
196          *  Set this bit to clear cp_out_dscr_err_int interrupt.
197          */
198         uint32_t dma_out_dscr_err_int_clr: 1;
199         /** dma_in_dscr_empty_int_clr : WO; bitpos: [6]; default: 0;
200          *  Set this bit to clear cp_in_dscr_empty_int interrupt.
201          */
202         uint32_t dma_in_dscr_empty_int_clr: 1;
203         /** dma_out_total_eof_int_clr : WO; bitpos: [7]; default: 0;
204          *  Set this bit to clear cp_out_total_eof_int interrupt.
205          */
206         uint32_t dma_out_total_eof_int_clr: 1;
207         /** dma_crc_done_int_clr : WO; bitpos: [8]; default: 0;
208          *  Set this bit to clear cp_crc_done_int interrupt.
209          */
210         uint32_t dma_crc_done_int_clr: 1;
211         uint32_t reserved9: 23;
212     };
213     uint32_t val;
214 } cp_dma_int_clr_reg_t;
215 
216 
217 /** Configuration Registers */
218 /** Type of dma_out_link register
219  *  Link descriptor address and control
220  */
221 typedef union {
222     struct {
223         /** dma_outlink_addr : R/W; bitpos: [19:0]; default: 0;
224          *  This register is used to specify the least significant 20 bits of the first outlink
225          *  descriptor's address.
226          */
227         uint32_t dma_outlink_addr: 20;
228         uint32_t reserved_20: 8;
229         /** dma_outlink_stop : R/W; bitpos: [28]; default: 0;
230          *  Set this bit to stop dealing with the outlink descriptor.
231          */
232         uint32_t dma_outlink_stop: 1;
233         /** dma_outlink_start : R/W; bitpos: [29]; default: 0;
234          *  Set this bit to start a new outlink descriptor.
235          */
236         uint32_t dma_outlink_start: 1;
237         /** dma_outlink_restart : R/W; bitpos: [30]; default: 0;
238          *  Set this bit to restart the outlink descriptpr from the last address.
239          */
240         uint32_t dma_outlink_restart: 1;
241         /** dma_outlink_park : RO; bitpos: [31]; default: 0;
242          *  1: the outlink descriptor's FSM is in idle state.
243          *  0: the outlink descriptor's FSM is working.
244          */
245         uint32_t dma_outlink_park: 1;
246     };
247     uint32_t val;
248 } cp_dma_out_link_reg_t;
249 
250 /** Type of dma_in_link register
251  *  Link descriptor address and control
252  */
253 typedef union {
254     struct {
255         /** dma_inlink_addr : R/W; bitpos: [19:0]; default: 0;
256          *  This register is used to specify the least significant 20 bits of the first inlink
257          *  descriptor's address.
258          */
259         uint32_t dma_inlink_addr: 20;
260         uint32_t reserved_20: 8;
261         /** dma_inlink_stop : R/W; bitpos: [28]; default: 0;
262          *  Set this bit to stop dealing with the inlink descriptors.
263          */
264         uint32_t dma_inlink_stop: 1;
265         /** dma_inlink_start : R/W; bitpos: [29]; default: 0;
266          *  Set this bit to start dealing with the inlink descriptors.
267          */
268         uint32_t dma_inlink_start: 1;
269         /** dma_inlink_restart : R/W; bitpos: [30]; default: 0;
270          *  Set this bit to restart new inlink descriptors.
271          */
272         uint32_t dma_inlink_restart: 1;
273         /** dma_inlink_park : RO; bitpos: [31]; default: 0;
274          *  1: the inlink descriptor's FSM is in idle state.
275          *  0: the inlink descriptor's FSM is working.
276          */
277         uint32_t dma_inlink_park: 1;
278     };
279     uint32_t val;
280 } cp_dma_in_link_reg_t;
281 
282 /** Type of dma_conf register
283  *  Copy DMA configuration register
284  */
285 typedef union {
286     struct {
287         /** dma_in_rst : R/W; bitpos: [0]; default: 0;
288          *  Set this bit to reset in_inf state machine.
289          */
290         uint32_t dma_in_rst: 1;
291         /** dma_out_rst : R/W; bitpos: [1]; default: 0;
292          *  Set this bit to reset out_inf state machine.
293          */
294         uint32_t dma_out_rst: 1;
295         /** dma_cmdfifo_rst : R/W; bitpos: [2]; default: 0;
296          *  Set this bit to reset in_cmd fifo and out_cmd fifo.
297          */
298         uint32_t dma_cmdfifo_rst: 1;
299         /** dma_fifo_rst : R/W; bitpos: [3]; default: 0;
300          *  Set this bit to reset data in receive FIFO.
301          */
302         uint32_t dma_fifo_rst: 1;
303         /** dma_out_owner : R/W; bitpos: [4]; default: 0;
304          *  This is used to configure the owner bit in OUT descriptor. This is effective only
305          *  when you set reg_out_auto_wrback.
306          */
307         uint32_t dma_out_owner: 1;
308         /** dma_in_owner : R/W; bitpos: [5]; default: 0;
309          *  This is used to configure the owner bit in IN descriptor.
310          */
311         uint32_t dma_in_owner: 1;
312         /** dma_out_auto_wrback : R/W; bitpos: [6]; default: 0;
313          *  This bit is used to write back out descriptor when hardware has already used this
314          *  descriptor.
315          */
316         uint32_t dma_out_auto_wrback: 1;
317         /** dma_check_owner : R/W; bitpos: [7]; default: 0;
318          *  Set this bit to enable owner bit check in descriptor.
319          */
320         uint32_t dma_check_owner: 1;
321         /** dma_crc_cal_reset : R/W; bitpos: [8]; default: 0;
322          *  Set this bit to reset crc calculation.
323          */
324         uint32_t dma_crc_cal_reset: 1;
325         /** dma_crc_cal_en : R/W; bitpos: [9]; default: 0;
326          *  Set this bit enable crc calculation function.
327          */
328         uint32_t dma_crc_cal_en: 1;
329         /** dma_crc_big_endian_en : R/W; bitpos: [10]; default: 0;
330          *  Set this bit to reorder the bit of data which will be send to excute crc.
331          */
332         uint32_t dma_crc_big_endian_en: 1;
333         /** dma_crc_out_reverse_en : R/W; bitpos: [11]; default: 0;
334          *  Set this bit to reverse the crc calculation result.
335          */
336         uint32_t dma_crc_out_reverse_en: 1;
337         uint32_t reserved_12: 19;
338         /** dma_clk_en : R/W; bitpos: [31]; default: 0;
339          *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
340          *  registers.
341          */
342         uint32_t dma_clk_en: 1;
343     };
344     uint32_t val;
345 } cp_dma_conf_reg_t;
346 
347 
348 /** Status Registers */
349 /** Type of dma_out_eof_des_addr register
350  *  Outlink descriptor address when EOF occurs
351  */
352 typedef union {
353     struct {
354         /** dma_out_eof_des_addr : RO; bitpos: [31:0]; default: 0;
355          *  This register stores the address of the outlink descriptor when the EOF bit in this
356          *  descriptor is 1.
357          */
358         uint32_t dma_out_eof_des_addr: 32;
359     };
360     uint32_t val;
361 } cp_dma_out_eof_des_addr_reg_t;
362 
363 /** Type of dma_in_eof_des_addr register
364  *  Inlink descriptor address when EOF occurs
365  */
366 typedef union {
367     struct {
368         /** dma_in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
369          *  This register stores the address of the inlink descriptor when received successful
370          *  EOF.
371          */
372         uint32_t dma_in_suc_eof_des_addr: 32;
373     };
374     uint32_t val;
375 } cp_dma_in_eof_des_addr_reg_t;
376 
377 /** Type of dma_out_eof_bfr_des_addr register
378  *  Outlink descriptor address before the last outlink descriptor
379  */
380 typedef union {
381     struct {
382         /** dma_out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
383          *  This register stores the address of the outlink descriptor before the last outlink
384          *  descriptor.
385          */
386         uint32_t dma_out_eof_bfr_des_addr: 32;
387     };
388     uint32_t val;
389 } cp_dma_out_eof_bfr_des_addr_reg_t;
390 
391 /** Type of dma_inlink_dscr register
392  *  Address of current inlink descriptor
393  */
394 typedef union {
395     struct {
396         /** dma_inlink_dscr : RO; bitpos: [31:0]; default: 0;
397          *  The address of the current inlink descriptor x.
398          */
399         uint32_t dma_inlink_dscr: 32;
400     };
401     uint32_t val;
402 } cp_dma_inlink_dscr_reg_t;
403 
404 /** Type of dma_inlink_dscr_bf0 register
405  *  Address of last inlink descriptor
406  */
407 typedef union {
408     struct {
409         /** dma_inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
410          *  The address of the last inlink descriptor x-1.
411          */
412         uint32_t dma_inlink_dscr_bf0: 32;
413     };
414     uint32_t val;
415 } cp_dma_inlink_dscr_bf0_reg_t;
416 
417 /** Type of dma_inlink_dscr_bf1 register
418  *  Address of the second-to-last inlink descriptor
419  */
420 typedef union {
421     struct {
422         /** dma_inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
423          *  The address of the second-to-last inlink descriptor x-2.
424          */
425         uint32_t dma_inlink_dscr_bf1: 32;
426     };
427     uint32_t val;
428 } cp_dma_inlink_dscr_bf1_reg_t;
429 
430 /** Type of dma_outlink_dscr register
431  *  Address of current outlink descriptor
432  */
433 typedef union {
434     struct {
435         /** dma_outlink_dscr : RO; bitpos: [31:0]; default: 0;
436          *  The address of the current outlink descriptor y.
437          */
438         uint32_t dma_outlink_dscr: 32;
439     };
440     uint32_t val;
441 } cp_dma_outlink_dscr_reg_t;
442 
443 /** Type of dma_outlink_dscr_bf0 register
444  *  Address of last outlink descriptor
445  */
446 typedef union {
447     struct {
448         /** dma_outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
449          *  The address of the last outlink descriptor y-1.
450          */
451         uint32_t dma_outlink_dscr_bf0: 32;
452     };
453     uint32_t val;
454 } cp_dma_outlink_dscr_bf0_reg_t;
455 
456 /** Type of dma_outlink_dscr_bf1 register
457  *  Address of the second-to-last outlink descriptor
458  */
459 typedef union {
460     struct {
461         /** dma_outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
462          *  The address of the second-to-last outlink descriptor y-2.
463          */
464         uint32_t dma_outlink_dscr_bf1: 32;
465     };
466     uint32_t val;
467 } cp_dma_outlink_dscr_bf1_reg_t;
468 
469 /** Type of dma_in_st register
470  *  Status register of receiving data
471  */
472 typedef union {
473     struct {
474         /** dma_inlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
475          *  This register stores the current inlink descriptor's address.
476          */
477         uint32_t dma_inlink_dscr_addr: 18;
478         /** dma_in_dscr_state : RO; bitpos: [19:18]; default: 0;
479          *  Reserved.
480          */
481         uint32_t dma_in_dscr_state: 2;
482         /** dma_in_state : RO; bitpos: [22:20]; default: 0;
483          *  Reserved.
484          */
485         uint32_t dma_in_state: 3;
486         /** dma_fifo_empty : RO; bitpos: [23]; default: 0;
487          *  Copy DMA FIFO empty signal.
488          */
489         uint32_t dma_fifo_empty: 1;
490         uint32_t reserved24: 8;
491     };
492     uint32_t val;
493 } cp_dma_in_st_reg_t;
494 
495 /** Type of dma_out_st register
496  *  Status register of transmitting data
497  */
498 typedef union {
499     struct {
500         /** dma_outlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
501          *  This register stores the current outlink descriptor's address.
502          */
503         uint32_t dma_outlink_dscr_addr: 18;
504         /** dma_out_dscr_state : RO; bitpos: [19:18]; default: 0;
505          *  Reserved.
506          */
507         uint32_t dma_out_dscr_state: 2;
508         /** dma_out_state : RO; bitpos: [22:20]; default: 0;
509          *  Reserved.
510          */
511         uint32_t dma_out_state: 3;
512         /** dma_fifo_full : RO; bitpos: [23]; default: 0;
513          *  Copy DMA FIFO full signal.
514          */
515         uint32_t dma_fifo_full: 1;
516         uint32_t reserved24: 8;
517     };
518     uint32_t val;
519 } cp_dma_out_st_reg_t;
520 
521 /** Type of dma_crc_out register
522  *  CRC result register
523  */
524 typedef union {
525     struct {
526         /** dma_crc_result : RO; bitpos: [31:0]; default: 0;
527          *  This register stores the result of CRC.
528          */
529         uint32_t dma_crc_result: 32;
530     };
531     uint32_t val;
532 } cp_dma_crc_out_reg_t;
533 
534 /** Type of dma_date register
535  *  Copy DMA version register
536  */
537 typedef union {
538     struct {
539         /** dma_dma_date : R/W; bitpos: [31:0]; default: 403185664;
540          *  This is the version register.
541          */
542         uint32_t dma_dma_date: 32;
543     };
544     uint32_t val;
545 } cp_dma_date_reg_t;
546 
547 
548 typedef struct {
549     volatile cp_dma_int_raw_reg_t dma_int_raw;
550     volatile cp_dma_int_st_reg_t dma_int_st;
551     volatile cp_dma_int_ena_reg_t dma_int_ena;
552     volatile cp_dma_int_clr_reg_t dma_int_clr;
553     volatile cp_dma_out_link_reg_t dma_out_link;
554     volatile cp_dma_in_link_reg_t dma_in_link;
555     volatile cp_dma_out_eof_des_addr_reg_t dma_out_eof_des_addr;
556     volatile cp_dma_in_eof_des_addr_reg_t dma_in_eof_des_addr;
557     volatile cp_dma_out_eof_bfr_des_addr_reg_t dma_out_eof_bfr_des_addr;
558     volatile cp_dma_inlink_dscr_reg_t dma_inlink_dscr;
559     volatile cp_dma_inlink_dscr_bf0_reg_t dma_inlink_dscr_bf0;
560     volatile cp_dma_inlink_dscr_bf1_reg_t dma_inlink_dscr_bf1;
561     volatile cp_dma_outlink_dscr_reg_t dma_outlink_dscr;
562     volatile cp_dma_outlink_dscr_bf0_reg_t dma_outlink_dscr_bf0;
563     volatile cp_dma_outlink_dscr_bf1_reg_t dma_outlink_dscr_bf1;
564     volatile cp_dma_conf_reg_t dma_conf;
565     volatile cp_dma_in_st_reg_t dma_in_st;
566     volatile cp_dma_out_st_reg_t dma_out_st;
567     volatile cp_dma_crc_out_reg_t dma_crc_out;
568     uint32_t reserved_04c;
569     uint32_t reserved_050;
570     uint32_t reserved_054;
571     uint32_t reserved_058;
572     uint32_t reserved_05c;
573     uint32_t reserved_060;
574     uint32_t reserved_064;
575     uint32_t reserved_068;
576     uint32_t reserved_06c;
577     uint32_t reserved_070;
578     uint32_t reserved_074;
579     uint32_t reserved_078;
580     uint32_t reserved_07c;
581     uint32_t reserved_080;
582     uint32_t reserved_084;
583     uint32_t reserved_088;
584     uint32_t reserved_08c;
585     uint32_t reserved_090;
586     uint32_t reserved_094;
587     uint32_t reserved_098;
588     uint32_t reserved_09c;
589     uint32_t reserved_0a0;
590     uint32_t reserved_0a4;
591     uint32_t reserved_0a8;
592     uint32_t reserved_0ac;
593     uint32_t reserved_0b0;
594     uint32_t reserved_0b4;
595     uint32_t reserved_0b8;
596     uint32_t reserved_0bc;
597     uint32_t reserved_0c0;
598     uint32_t reserved_0c4;
599     uint32_t reserved_0c8;
600     uint32_t reserved_0cc;
601     uint32_t reserved_0d0;
602     uint32_t reserved_0d4;
603     uint32_t reserved_0d8;
604     uint32_t reserved_0dc;
605     uint32_t reserved_0e0;
606     uint32_t reserved_0e4;
607     uint32_t reserved_0e8;
608     uint32_t reserved_0ec;
609     uint32_t reserved_0f0;
610     uint32_t reserved_0f4;
611     uint32_t reserved_0f8;
612     volatile cp_dma_date_reg_t dma_date;
613 } cp_dma_dev_t;
614 
615 #ifndef __cplusplus
616 _Static_assert(sizeof(cp_dma_dev_t) == 0x100, "cp_dma_dev_t should occupy 0x100 bytes in memory");
617 #endif
618 
619 extern cp_dma_dev_t CP_DMA;
620 
621 #ifdef __cplusplus
622 }
623 #endif
624