1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 #include "esp_err.h" 9 #include "hal/adc_types.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #if CONFIG_IDF_TARGET_ESP32 16 /*--------------------------------------------------------------- 17 ESP32 Deprecated Types 18 ---------------------------------------------------------------*/ 19 /** 20 * @brief ADC digital controller (DMA mode) conversion rules setting. 21 */ 22 typedef struct { 23 union { 24 struct { 25 uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements. 26 0: measurement range 0 - 800mV, 27 1: measurement range 0 - 1100mV, 28 2: measurement range 0 - 1350mV, 29 3: measurement range 0 - 2600mV. */ 30 uint8_t bit_width: 2; /*!< ADC resolution. 31 - 0: 9 bit; 32 - 1: 10 bit; 33 - 2: 11 bit; 34 - 3: 12 bit. */ 35 int8_t channel: 4; /*!< ADC channel index. */ 36 }; 37 uint8_t val; /*!<Raw data value */ 38 }; 39 } adc_digi_pattern_table_t __attribute__((deprecated)); 40 41 /** 42 * Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs: 43 * 44 * +---------------------+--------+--------+--------+ 45 * | conv_mode | single | both | alter | 46 * +---------------------+--------+--------+--------+ 47 * | trigger meas times | 1 | 1 | 1 | 48 * +---------------------+--------+--------+--------+ 49 * | conv_limit_num | +1 | +1 | +1 | 50 * | dma_eof_num | +1 | +2 | +1 | 51 * | dma output (byte) | +2 | +4 | +2 | 52 * +---------------------+--------+--------+--------+ 53 */ 54 typedef struct { 55 bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times. 56 If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */ 57 uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */ 58 uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting). 59 The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection, 60 resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the 61 pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */ 62 uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */ 63 adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */ 64 adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */ 65 adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */ 66 adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */ 67 } adc_digi_config_t __attribute__((deprecated)); 68 #endif //#if CONFIG_IDF_TARGET_ESP32 69 70 71 #if CONFIG_IDF_TARGET_ESP32S2 72 /*--------------------------------------------------------------- 73 ESP32S2 Deprecated Types 74 ---------------------------------------------------------------*/ 75 /** 76 * @brief ADC digital controller (DMA mode) conversion rules setting. 77 */ 78 typedef struct { 79 union { 80 struct { 81 uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements. 82 0: measurement range 0 - 800mV, 83 1: measurement range 0 - 1100mV, 84 2: measurement range 0 - 1350mV, 85 3: measurement range 0 - 2600mV. */ 86 uint8_t reserved: 2; /*!< reserved0 */ 87 uint8_t channel: 4; /*!< ADC channel index. */ 88 }; 89 uint8_t val; /*!<Raw data value */ 90 }; 91 } adc_digi_pattern_table_t __attribute__((deprecated)); 92 93 /** 94 * @brief ADC digital controller (DMA mode) configuration parameters. 95 * 96 * Example setting: When using ADC1 channel0 to measure voltage, the sampling rate is required to be 1 kHz: 97 * 98 * +---------------------+--------+--------+--------+ 99 * | sample rate | 1 kHz | 1 kHz | 1 kHz | 100 * +---------------------+--------+--------+--------+ 101 * | conv_mode | single | both | alter | 102 * | adc1_pattern_len | 1 | 1 | 1 | 103 * | dig_clk.use_apll | 0 | 0 | 0 | 104 * | dig_clk.div_num | 99 | 99 | 99 | 105 * | dig_clk.div_b | 0 | 0 | 0 | 106 * | dig_clk.div_a | 0 | 0 | 0 | 107 * | interval | 400 | 400 | 200 | 108 * +---------------------+--------+--------+--------+ 109 * | `trigger_meas_freq` | 1 kHz | 1 kHz | 2 kHz | 110 * +---------------------+--------+--------+--------+ 111 * 112 * Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs: 113 * 114 * +---------------------+--------+--------+--------+ 115 * | conv_mode | single | both | alter | 116 * +---------------------+--------+--------+--------+ 117 * | trigger meas times | 1 | 1 | 1 | 118 * +---------------------+--------+--------+--------+ 119 * | conv_limit_num | +1 | +1 | +1 | 120 * | dma_eof_num | +1 | +2 | +1 | 121 * | dma output (byte) | +2 | +4 | +2 | 122 * +---------------------+--------+--------+--------+ 123 */ 124 typedef struct { 125 bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times. 126 If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */ 127 uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */ 128 uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting). 129 The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection, 130 resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the 131 pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */ 132 uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */ 133 adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */ 134 adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */ 135 adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */ 136 adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */ 137 uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement. 138 The unit is the divided clock. Range: 40 ~ 4095. 139 Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``. 140 Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */ 141 adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t``. 142 Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */ 143 uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller. 144 If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA. 145 Note: The converted data in the DMA in link buffer will be multiple of two bytes. */ 146 } adc_digi_config_t __attribute__((deprecated)); 147 148 /** 149 * @brief ADC digital controller (DMA mode) interrupt type options. 150 */ 151 typedef enum { 152 ADC_DIGI_INTR_MASK_MONITOR = 0x1, 153 ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2, 154 ADC_DIGI_INTR_MASK_ALL = 0x3, 155 } adc_digi_intr_t __attribute__((deprecated)); 156 FLAG_ATTR(adc_digi_intr_t) 157 #endif //#if CONFIG_IDF_TARGET_ESP32S2 158 159 160 #if CONFIG_IDF_TARGET_ESP32C3 161 /*--------------------------------------------------------------- 162 ESP32C3 Deprecated Types 163 ---------------------------------------------------------------*/ 164 /** 165 * @brief ADC digital controller (DMA mode) conversion rules setting. 166 */ 167 typedef struct { 168 union { 169 struct { 170 uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements. 171 0: measurement range 0 - 800mV, 172 1: measurement range 0 - 1100mV, 173 2: measurement range 0 - 1350mV, 174 3: measurement range 0 - 2600mV. */ 175 uint8_t channel: 3; /*!< ADC channel index. */ 176 uint8_t unit: 1; /*!< ADC unit index. */ 177 uint8_t reserved: 2; /*!< reserved0 */ 178 }; 179 uint8_t val; /*!<Raw data value */ 180 }; 181 } adc_digi_pattern_table_t __attribute__((deprecated)); 182 183 typedef struct { 184 bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times. 185 If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */ 186 uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */ 187 uint32_t adc_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 7 (0: Don't change the pattern table setting). 188 The pattern table that defines the conversion rules for each SAR ADC. Each table has 7 items, in which channel selection, 189 resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the 190 pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */ 191 adc_digi_pattern_table_t *adc_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc_pattern_len`. */ 192 uint32_t sample_freq_hz; /*!< The expected ADC sampling frequency in Hz. Range: 611Hz ~ 83333Hz 193 Fs = Fd / interval / 2 194 Fs: sampling frequency; 195 Fd: digital controller frequency, no larger than 5M for better performance 196 interval: interval between 2 measurement trigger signal, the smallest interval should not be smaller than the ADC measurement period, the largest interval should not be larger than 4095 */ 197 } adc_digi_config_t __attribute__((deprecated)); 198 #endif //#if CONFIG_IDF_TARGET_ESP32C3 199 200 201 #ifdef __cplusplus 202 } 203 #endif 204
