1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file dma.h
21 *
22 * @brief This is the header file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 /** @page DMA
28 *
29 * Introduction
30 * ===============
31 *
32 *
33 * API Reference
34 * ===============
35 * Header File: dma.h
36 */
37 #ifndef DMA_H_
38 #define DMA_H_
39 #include "reg_include/register_b91.h"
40 typedef enum{
41 DMA0=0,
42 DMA1,
43 DMA2,
44 DMA3,
45 DMA4,
46 DMA5,
47 DMA6,
48 DMA7,
49 }dma_chn_e;
50
51 typedef enum{
52 DMA_CHN0_IRQ = BIT(0),
53 DMA_CHN1_IRQ = BIT(1),
54 DMA_CHN2_IRQ = BIT(2),
55 DMA_CHN3_IRQ = BIT(3),
56 DMA_CHN4_IRQ = BIT(4),
57 DMA_CHN5_IRQ = BIT(5),
58 DMA_CHN6_IRQ = BIT(6),
59 DMA_CHN7_IRQ = BIT(7),
60 }dma_irq_chn_e;
61
62 typedef enum{
63 DMA_REQ_SPI_AHB_TX=0,
64 DMA_REQ_SPI_AHB_RX,
65 DMA_REQ_UART0_TX,
66 DMA_REQ_UART0_RX,
67 DMA_REQ_SPI_APB_TX,
68 DMA_REQ_SPI_APB_RX,
69 DMA_REQ_I2C_TX,
70 DMA_REQ_I2C_RX,
71 DMA_REQ_ZB_TX,
72 DMA_REQ_ZB_RX,
73 DMA_REQ_PWM_TX,
74 DMA_REQ_RESERVED,
75 DMA_REQ_ALGM_TX,
76 DMA_REQ_ALGM_RX,
77 DMA_REQ_UART1_TX,
78 DMA_REQ_UART1_RX,
79 DMA_REQ_AUDIO0_TX,
80 DMA_REQ_AUDIO0_RX,
81 DMA_REQ_AUDIO1_TX,
82 DMA_REQ_AUDIO1_RX,
83
84 }dma_req_sel_e;
85
86 typedef enum{
87 DMA_ADDR_INCREMENT=0,
88 DMA_ADDR_DECREMENT,
89 DMA_ADDR_FIX,
90 }
91 dma_addr_ctrl_e;
92
93
94 typedef enum{
95 DMA_NORMAL_MODE=0,
96 DMA_HANDSHAKE_MODE,
97 }
98 dma_mode_e;
99
100 typedef enum{
101 DMA_CTR_BYTE_WIDTH=0,
102 DMA_CTR_HWORD_WIDTH,
103 DMA_CTR_WORD_WIDTH,
104 }
105 dma_ctr_width_e;
106
107 typedef enum{
108 DMA_BYTE_WIDTH=1,
109 DMA_HWORD_WIDTH=2,
110 DMA_WORD_WIDTH=4,
111 }
112 dma_transfer_width_e;
113
114 typedef enum{
115 TC_MASK = BIT(1),
116 ERR_MASK = BIT(2),
117 ABT_MASK = BIT(3),
118 }dma_irq_mask_e;
119
120 typedef struct {
121 unsigned int dst_req_sel:5; /*DstReqSel :8:4 */
122 unsigned int src_req_sel:5; /*SrcReqSel :13:9 */
123 unsigned int dst_addr_ctrl:2;/*DstAddrCtrl :15:14 0:increment address 1: decrement address 2: fixed address */
124 unsigned int src_addr_ctrl:2;/*SrcAddrCtrl :17:16 0:increment address 1: decrement address 2: fixed address */
125 unsigned int dstmode:1; /*DstMode:18 0 normal mode 1 handshake*/
126 unsigned int srcmode:1; /*SrcMode :19 0 normal mode 1 handshake*/
127 unsigned int dstwidth:2; /*DstWidth :21:20 00:byte 01:hword 02:word*/
128 unsigned int srcwidth:2; /*SrcWidth :23:22 00:byte 01:hword 02:word*/
129 unsigned int src_burst_size:3; /*SrcBurstSize: 26:24*/
130 unsigned int vacant_bit :1;/*vacant:27*/
131 unsigned int read_num_en:1;/*Rnum_en :28*/
132 unsigned int priority:1; /*Pri :29*/
133 unsigned int write_num_en:1;/*wnum_en : 30*/
134 unsigned int auto_en:1;/*/*auto_en : 31*/
135 }dma_config_t;
136
137
138 typedef struct {
139 unsigned int dma_chain_ctl;
140 unsigned int dma_chain_src_addr;
141 unsigned int dma_chain_dst_addr;
142 unsigned int dma_chain_data_len;
143 unsigned int dma_chain_llp_ptr;
144 }dma_chain_config_t ;
145
146
147 /**
148 * @brief This function configures DMA control register.
149 * @param[in] chn - dma channel
150 * @param[in] config - the prt of dma_config that configured control register
151 * @return none
152 */
dma_config(dma_chn_e chn,dma_config_t * config)153 static inline void dma_config(dma_chn_e chn ,dma_config_t *config)
154 {
155 BM_CLR(reg_dma_ctrl(chn),BIT_RNG(4,31));
156 reg_dma_ctrl(chn) |= (*(unsigned int*)config)<<4;
157 }
158
159
160 /**
161 * @brief This function servers to enable dma that selected channel.
162 * @param[in] chn - dma channel.
163 * @return none
164 */
dma_chn_en(dma_chn_e chn)165 static inline void dma_chn_en(dma_chn_e chn)
166 {
167 BM_SET(reg_dma_ctr0(chn),BIT(0));
168 }
169
170 /**
171 * @brief This function servers to disable dma that selected channel.
172 * @param[in] chn - dma channel.
173 * @return none
174 */
dma_chn_dis(dma_chn_e chn)175 static inline void dma_chn_dis(dma_chn_e chn)
176 {
177 BM_CLR(reg_dma_ctr0(chn),BIT(0));
178 }
179
180 /**
181 * @brief This function servers to set dma irq mask.
182 * @param[in] chn - dma channel.
183 * @param[in] mask - dma irq mask.
184 * @return none
185 */
dma_set_irq_mask(dma_chn_e chn,dma_irq_mask_e mask)186 static inline void dma_set_irq_mask(dma_chn_e chn,dma_irq_mask_e mask)
187 {
188 reg_dma_ctr0(chn) = (reg_dma_ctr0(chn) | BIT_RNG(1,3)) & (~(mask));
189 }
190
191 /**
192 * @brief This function servers to clr dma irq mask.
193 * @param[in] chn - dma channel.
194 * @param[in] mask - dma irq mask.
195 * @return none
196 * attention the mask of dma tc/err/abt is enable default.we must disable when don'n use it.
197 */
dma_clr_irq_mask(dma_chn_e chn,dma_irq_mask_e mask)198 static inline void dma_clr_irq_mask(dma_chn_e chn,dma_irq_mask_e mask)
199 {
200 reg_dma_ctr0(chn) |= (mask);
201 }
202
203 /**
204 * @brief This function servers to get the terminal count irq status channel.
205 * @return the dma terminal count irq status channel.
206 */
dma_get_tc_irq_status(dma_irq_chn_e tc_chn)207 static inline unsigned char dma_get_tc_irq_status(dma_irq_chn_e tc_chn)
208 {
209 return reg_dma_tc_isr&tc_chn;
210 }
211
212
213 /**
214 * @brief This function servers to clear the irq of terminal count status.
215 * @param[in] tc_chn -terminal count irq status channel.
216 * @return none
217 */
dma_clr_tc_irq_status(dma_irq_chn_e tc_chn)218 static inline void dma_clr_tc_irq_status(dma_irq_chn_e tc_chn)
219 {
220 reg_dma_tc_isr = tc_chn;
221 }
222
223
224 /**
225 * @brief This function servers to get the error irq status channel.
226 * @return the dma error irq status channel.
227 */
dma_get_err_irq_status(dma_irq_chn_e err_chn)228 static inline unsigned char dma_get_err_irq_status(dma_irq_chn_e err_chn)
229 {
230 return reg_dma_err_isr&err_chn;
231 }
232
233
234 /**
235 * @brief This function servers to clear the abort status of channel.
236 * @param[in] err_chn -error status channel.
237 * @return none
238 */
dma_clr_err_irq_status(dma_irq_chn_e err_chn)239 static inline void dma_clr_err_irq_status(dma_irq_chn_e err_chn)
240 {
241 reg_dma_err_isr = err_chn;
242 }
243
244
245 /**
246 * @brief This function servers to get the abort status of channel.
247 * @return the dma abort irq status channel.
248 */
dma_get_abt_irq_status(dma_irq_chn_e abt_chn)249 static inline unsigned char dma_get_abt_irq_status(dma_irq_chn_e abt_chn)
250 {
251 return reg_dma_abt_isr&abt_chn;
252 }
253
254
255 /**
256 * @brief This function servers to clear the abort status of channel.
257 * @param[in] abt_chn -abort irq status channel.
258 * @return none
259 */
dma_clr_abt_irq_status(dma_irq_chn_e abt_chn)260 static inline void dma_clr_abt_irq_status(dma_irq_chn_e abt_chn)
261 {
262 reg_dma_abt_isr = abt_chn;
263 }
264
265 /**
266 * @brief this function set the DMA to tx/rx size byte.
267 * @param[in] chn - DMA channel
268 * @param[in] size_byte - the address of dma tx/rx size .The maximum transmission length of DMA is 0xFFFFFC bytes and cannot exceed this length.
269 * @param[in] byte_width - dma tx/rx width
270 * @return none
271 */
dma_set_size(dma_chn_e chn,unsigned int size_byte,dma_transfer_width_e byte_width)272 static inline void dma_set_size(dma_chn_e chn,unsigned int size_byte,dma_transfer_width_e byte_width)
273 {
274 reg_dma_size(chn) =((size_byte+byte_width-1)/byte_width)|( (size_byte % byte_width)<<22);
275 }
276
277
278 /**
279 * @brief this function calculate the DMA to tx/rx size byte.
280 * @param[in] size_byte - the address of dma tx/rx size
281 * @param[in] byte_width - dma tx/rx width
282 * @return none
283 */
dma_cal_size(unsigned int size_byte,dma_transfer_width_e byte_width)284 static inline unsigned int dma_cal_size(unsigned int size_byte,dma_transfer_width_e byte_width)
285 {
286 return (((size_byte+byte_width-1)/byte_width)|( (size_byte % byte_width)<<22));
287 }
288
289
290 /**
291 * @brief this function set source and destination address for DMA,
292 * src_address dst_address
293 * tx sram interface fifo.
294 * rx interface fifo sram
295 * @param[in] chn - DMA channel
296 * @param[in] src_addr - the address of source.
297 * @param[in] dst_addr - the address of destination.
298 * @return none
299 */
dma_set_address(dma_chn_e chn,unsigned int src_addr,unsigned int dst_addr)300 static inline void dma_set_address(dma_chn_e chn,unsigned int src_addr,unsigned int dst_addr)
301 {
302 reg_dma_src_addr(chn)=src_addr;
303 reg_dma_dst_addr(chn)=dst_addr;
304 }
305
306
307 /**
308 * @brief this function set source address for DMA,
309 * @param[in] chn - DMA channel
310 * @param[in] src_addr - the address of source.
311 * */
dma_set_src_address(dma_chn_e chn,unsigned int src_addr)312 static inline void dma_set_src_address(dma_chn_e chn,unsigned int src_addr)
313 {
314 reg_dma_src_addr(chn)=src_addr;
315 }
316
317 /**
318 * @brief this function set destination address for DMA,
319 * @param[in] chn - DMA channel
320 * @param[in] dst_addr - the address of destination.
321 * */
dma_set_dst_address(dma_chn_e chn,unsigned int dst_addr)322 static inline void dma_set_dst_address(dma_chn_e chn,unsigned int dst_addr)
323 {
324 reg_dma_dst_addr(chn)=dst_addr;
325 }
326
327
328 /**
329 * @brief this function set reset DMA,
330 * @return none
331 */
dma_reset(void)332 static inline void dma_reset(void)
333 {
334 reg_rst1 &= ~(FLD_RST1_DMA);
335 reg_rst1 |= FLD_RST1_DMA;
336 }
337
338
339 #endif
340
