1 /*
2 * Copyright (c) 2022-2023 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef __DMA350_CH_DRV_H
18 #define __DMA350_CH_DRV_H
19
20 #include "dma350_regdef.h"
21
22 /* For __STATIC_INLINE and __DMB */
23 #include "cmsis_compiler.h"
24
25 #include <stdbool.h>
26 #include <stdint.h>
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 /* DMA350_CH state definitions */
33 #define DMA350_CH_INITIALIZED (1UL << 0)
34
35 #define DMA350_CH_TMPLTCFG_SRCTMPLTSIZE_MAX 0x1FUL
36 #define DMA350_CH_TMPLTCFG_DESTMPLTSIZE_MAX 0x1FUL
37
38 #define DMA350_CH_CTRL_RESET_VALUE 0x00200200
39 #define DMA350_CH_INTREN_RESET_VALUE 0x00000000
40 #define DMA350_CH_LINKADDR_RESET_VALUE 0x00000000
41 #define DMA350_CH_DESTRANSCFG_RESET_VALUE 0x000F0400
42 #define DMA350_CH_SRCTRANSCFG_RESET_VALUE 0x000F0400
43 #define DMA350_CH_AUTOCFG_RESET_VALUE 0x00000000
44
45 #define DMA350_CMDLINK_REGCLEAR_SET (0x1UL)
46 #define DMA350_CMDLINK_INTREN_SET (0x1UL << 2)
47 #define DMA350_CMDLINK_CTRL_SET (0x1UL << 3)
48 #define DMA350_CMDLINK_SRC_ADDR_SET (0x1UL << 4)
49 #define DMA350_CMDLINK_SRC_ADDRHI_SET (0x1UL << 5)
50 #define DMA350_CMDLINK_DES_ADDR_SET (0x1UL << 6)
51 #define DMA350_CMDLINK_DES_ADDRHI_SET (0x1UL << 7)
52 #define DMA350_CMDLINK_XSIZE_SET (0x1UL << 8)
53 #define DMA350_CMDLINK_XSIZEHI_SET (0x1UL << 9)
54 #define DMA350_CMDLINK_SRCTRANSCFG_SET (0x1UL << 10)
55 #define DMA350_CMDLINK_DESTRANSCFG_SET (0x1UL << 11)
56 #define DMA350_CMDLINK_XADDRINC_SET (0x1UL << 12)
57 #define DMA350_CMDLINK_YADDRSTRIDE_SET (0x1UL << 13)
58 #define DMA350_CMDLINK_FILLVAL_SET (0x1UL << 14)
59 #define DMA350_CMDLINK_YSIZE_SET (0x1UL << 15)
60 #define DMA350_CMDLINK_TMPLTCFG_SET (0x1UL << 16)
61 #define DMA350_CMDLINK_SRCTMPLT_SET (0x1UL << 17)
62 #define DMA350_CMDLINK_DESTMPLT_SET (0x1UL << 18)
63 #define DMA350_CMDLINK_SRCTRIGINCFG_SET (0x1UL << 19)
64 #define DMA350_CMDLINK_DESTRIGINCFG_SET (0x1UL << 20)
65 #define DMA350_CMDLINK_TRIGOUTCFG_SET (0x1UL << 21)
66 #define DMA350_CMDLINK_GPOEN0_SET (0x1UL << 22)
67 #define DMA350_CMDLINK_GPOVAL0_SET (0x1UL << 24)
68 #define DMA350_CMDLINK_STREAMINTCFG_SET (0x1UL << 26)
69 #define DMA350_CMDLINK_LINKATTR_SET (0x1UL << 28)
70 #define DMA350_CMDLINK_AUTOCFG_SET (0x1UL << 29)
71 #define DMA350_CMDLINK_LINKADDR_SET (0x1UL << 30)
72 #define DMA350_CMDLINK_LINKADDRHI_SET (0x1UL << 31)
73
74 #define DMA350_CMD_1D_BASIC(_CH, _SRCADDR, _DESADDR, _SRCXSIZE, _DSTXSIZE) \
75 { \
76 DMA350_CMDLINK_SRC_ADDR_SET | DMA350_CMDLINK_DES_ADDR_SET | \
77 DMA350_CMDLINK_XSIZE_SET, \
78 (uint32_t)(_SRCADDR), (uint32_t)(_DESADDR), \
79 ((_SRCXSIZE) << 16U) | (_DSTXSIZE), \
80 }
81
82 /* Update a register (REG) at position (POS) with value (VAL).
83 * Affected bits are defined by a mask (MSK) */
84 #define SET_FIELD(REG, VAL, POS, MSK) \
85 do { \
86 REG = (REG & ~MSK) | (((uint32_t)(VAL) << POS) & MSK); \
87 } while (0)
88
89 /* DMA350 DMA Channel error enumeration types */
90 enum dma350_ch_error_t {
91 DMA350_CH_ERR_NONE = 0, /*!< No error */
92 DMA350_CH_ERR_IIDR_MISMATCH, /*!< Error: DMA350 driver does not support this
93 * implementer of the hardware */
94 DMA350_CH_ERR_AIDR_MISMATCH, /*!< Error: DMA350 driver does not support this
95 * architecture revision */
96 DMA350_CH_ERR_INVALID_ARG, /*!< Error: invalid input argument */
97 DMA350_CH_ERR_INVALID_CMD, /*!< Error: invalid command */
98 DMA350_CH_ERR_NOT_READY, /*!< Error: DMA350 not ready */
99 DMA350_CH_ERR_UNSUP_CH, /*!< Error: DMA350 Channel not supported */
100 };
101
102 /* ARM DMA350 DMA Channel device configuration structure */
103 struct dma350_ch_dev_cfg_t {
104 DMACH_TypeDef *const ch_base; /*!< DMA350 DMA Channel base address */
105 const uint8_t channel; /*!< DMA350 DMA Channel number */
106 };
107
108 /* ARM DMA350 DMA Channel device data structure */
109 struct dma350_ch_dev_data_t {
110 uint32_t state; /*!< Indicates if the DMA350 Channel driver
111 * is initialized and enabled */
112 };
113
114 /* ARM DMA350 DMA Channel device structure */
115 struct dma350_ch_dev_t {
116 const struct dma350_ch_dev_cfg_t cfg; /*!< DMA350 DMA Channel Config */
117 struct dma350_ch_dev_data_t data; /*!< DMA350 DMA Channel Data */
118 };
119
120 /* ARM DMA350 DMA Channel commands */
121 enum dma350_ch_cmd_t {
122 DMA350_CH_CMD_ENABLECMD = DMA_CH_CMD_ENABLECMD,
123 DMA350_CH_CMD_CLEARCMD = DMA_CH_CMD_CLEARCMD,
124 DMA350_CH_CMD_DISABLECMD = DMA_CH_CMD_DISABLECMD,
125 DMA350_CH_CMD_STOPCMD = DMA_CH_CMD_STOPCMD,
126 DMA350_CH_CMD_PAUSECMD = DMA_CH_CMD_PAUSECMD,
127 DMA350_CH_CMD_RESUMECMD = DMA_CH_CMD_RESUMECMD,
128 DMA350_CH_CMD_SRCSWTRIGINREQ = DMA_CH_CMD_SRCSWTRIGINREQ,
129 DMA350_CH_CMD_SRCSWTRIGINREQ_LAST =
130 DMA_CH_CMD_SRCSWTRIGINREQ | DMA_CH_CMD_SRCSWTRIGINTYPE_0,
131 DMA350_CH_CMD_SRCSWTRIGINREQ_BLOCK =
132 DMA_CH_CMD_SRCSWTRIGINREQ | DMA_CH_CMD_SRCSWTRIGINTYPE_1,
133 DMA350_CH_CMD_SRCSWTRIGINREQ_BLOCK_LAST = DMA_CH_CMD_SRCSWTRIGINREQ |
134 DMA_CH_CMD_SRCSWTRIGINTYPE_1 |
135 DMA_CH_CMD_SRCSWTRIGINTYPE_0,
136 DMA350_CH_CMD_DESSWTRIGINREQ = DMA_CH_CMD_DESSWTRIGINREQ,
137 DMA350_CH_CMD_DESSWTRIGINREQ_LAST =
138 DMA_CH_CMD_DESSWTRIGINREQ | DMA_CH_CMD_DESSWTRIGINTYPE_0,
139 DMA350_CH_CMD_DESSWTRIGINREQ_BLOCK =
140 DMA_CH_CMD_DESSWTRIGINREQ | DMA_CH_CMD_DESSWTRIGINTYPE_1,
141 DMA350_CH_CMD_DESSWTRIGINREQ_BLOCK_LAST = DMA_CH_CMD_DESSWTRIGINREQ |
142 DMA_CH_CMD_DESSWTRIGINTYPE_1 |
143 DMA_CH_CMD_DESSWTRIGINTYPE_0,
144 DMA350_CH_CMD_SWTRIGOUTACK = DMA_CH_CMD_SWTRIGOUTACK
145 };
146
147 /* ARM DMA350 DMA Channel status bits */
148 enum dma350_ch_stat_t {
149 DMA350_CH_STAT_DONE = DMA_CH_STATUS_STAT_DONE,
150 DMA350_CH_STAT_ERR = DMA_CH_STATUS_STAT_ERR,
151 DMA350_CH_STAT_DISABLED = DMA_CH_STATUS_STAT_DISABLED,
152 DMA350_CH_STAT_STOPPED = DMA_CH_STATUS_STAT_STOPPED,
153 DMA350_CH_STAT_SRCTRIGINWAIT = DMA_CH_STATUS_STAT_SRCTRIGINWAIT,
154 DMA350_CH_STAT_DESTRIGINWAIT = DMA_CH_STATUS_STAT_DESTRIGINWAIT,
155 DMA350_CH_STAT_TRIGOUTACKWAIT = DMA_CH_STATUS_STAT_TRIGOUTACKWAIT,
156 DMA350_CH_STAT_ALL =
157 DMA_CH_STATUS_STAT_DONE | DMA_CH_STATUS_STAT_ERR |
158 DMA_CH_STATUS_STAT_DISABLED | DMA_CH_STATUS_STAT_STOPPED |
159 DMA_CH_STATUS_STAT_SRCTRIGINWAIT | DMA_CH_STATUS_STAT_DESTRIGINWAIT |
160 DMA_CH_STATUS_STAT_TRIGOUTACKWAIT
161 };
162
163 /* ARM DMA350 DMA Channel interrupt bits */
164 enum dma350_ch_intr_t {
165 DMA350_CH_INTREN_DONE = DMA_CH_INTREN_INTREN_DONE,
166 DMA350_CH_INTREN_ERR = DMA_CH_INTREN_INTREN_ERR,
167 DMA350_CH_INTREN_DISABLED = DMA_CH_INTREN_INTREN_DISABLED,
168 DMA350_CH_INTREN_STOPPED = DMA_CH_INTREN_INTREN_STOPPED,
169 DMA350_CH_INTREN_SRCTRIGINWAIT = DMA_CH_INTREN_INTREN_SRCTRIGINWAIT,
170 DMA350_CH_INTREN_DESTRIGINWAIT = DMA_CH_INTREN_INTREN_DESTRIGINWAIT,
171 DMA350_CH_INTREN_TRIGOUTACKWAIT = DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT,
172 DMA350_CH_INTREN_ALL =
173 DMA_CH_INTREN_INTREN_DONE | DMA_CH_INTREN_INTREN_ERR |
174 DMA_CH_INTREN_INTREN_DISABLED | DMA_CH_INTREN_INTREN_STOPPED |
175 DMA_CH_INTREN_INTREN_SRCTRIGINWAIT |
176 DMA_CH_INTREN_INTREN_DESTRIGINWAIT | DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT
177 };
178
179 /* ARM DMA350 DMA Channel Transfer size */
180 enum dma350_ch_transize_t {
181 DMA350_CH_TRANSIZE_8BITS = 0,
182 DMA350_CH_TRANSIZE_16BITS = DMA_CH_CTRL_TRANSIZE_0,
183 DMA350_CH_TRANSIZE_32BITS = DMA_CH_CTRL_TRANSIZE_1,
184 DMA350_CH_TRANSIZE_64BITS = DMA_CH_CTRL_TRANSIZE_1 | DMA_CH_CTRL_TRANSIZE_0,
185 DMA350_CH_TRANSIZE_128BITS = DMA_CH_CTRL_TRANSIZE_2,
186 DMA350_CH_TRANSIZE_256BITS =
187 DMA_CH_CTRL_TRANSIZE_2 | DMA_CH_CTRL_TRANSIZE_0,
188 DMA350_CH_TRANSIZE_512BITS =
189 DMA_CH_CTRL_TRANSIZE_2 | DMA_CH_CTRL_TRANSIZE_1,
190 DMA350_CH_TRANSIZE_1024BITS =
191 DMA_CH_CTRL_TRANSIZE_2 | DMA_CH_CTRL_TRANSIZE_1 | DMA_CH_CTRL_TRANSIZE_0
192 };
193
194 /* ARM DMA350 DMA Channel XTYPE */
195 enum dma350_ch_xtype_t {
196 DMA350_CH_XTYPE_DISABLE = 0,
197 DMA350_CH_XTYPE_CONTINUE = DMA_CH_CTRL_XTYPE_0,
198 DMA350_CH_XTYPE_WRAP = DMA_CH_CTRL_XTYPE_1,
199 DMA350_CH_XTYPE_FILL = DMA_CH_CTRL_XTYPE_1 | DMA_CH_CTRL_XTYPE_0
200 };
201
202 /* ARM DMA350 DMA Channel YTYPE */
203 enum dma350_ch_ytype_t {
204 DMA350_CH_YTYPE_DISABLE = 0,
205 DMA350_CH_YTYPE_CONTINUE = DMA_CH_CTRL_YTYPE_0,
206 DMA350_CH_YTYPE_WRAP = DMA_CH_CTRL_YTYPE_1,
207 DMA350_CH_YTYPE_FILL = DMA_CH_CTRL_YTYPE_1 | DMA_CH_CTRL_YTYPE_0
208 };
209
210 /* ARM DMA350 DMA Channel Automatic register reload type */
211 enum dma350_ch_regreloadtype_t {
212 DMA350_CH_REGRELOADTYPE_DISABLE = 0,
213 DMA350_CH_REGRELOADTYPE_SRC_DES_SIZE = DMA_CH_CTRL_REGRELOADTYPE_0,
214 DMA350_CH_REGRELOADTYPE_SRC_ADDR_SRC_DES_SIZE =
215 DMA_CH_CTRL_REGRELOADTYPE_1 | DMA_CH_CTRL_REGRELOADTYPE_0,
216 DMA350_CH_REGRELOADTYPE_DES_ADDR_SRC_DES_SIZE =
217 DMA_CH_CTRL_REGRELOADTYPE_2 | DMA_CH_CTRL_REGRELOADTYPE_0,
218 DMA350_CH_REGRELOADTYPE_SRC_DES_ADDR_AND_SIZE =
219 DMA_CH_CTRL_REGRELOADTYPE_2 | DMA_CH_CTRL_REGRELOADTYPE_1 |
220 DMA_CH_CTRL_REGRELOADTYPE_0
221 };
222
223 /* ARM DMA350 DMA Channel Done type */
224 enum dma350_ch_donetype_t {
225 DMA350_CH_DONETYPE_NONE = 0,
226 DMA350_CH_DONETYPE_END_OF_CMD = DMA_CH_CTRL_DONETYPE_0,
227 DMA350_CH_DONETYPE_END_OF_AUTORESTART =
228 DMA_CH_CTRL_DONETYPE_1 | DMA_CH_CTRL_DONETYPE_0
229 };
230
231 /* ARM DMA350 DMA Channel Source Trigger Input Type */
232 enum dma350_ch_srctrigintype_t {
233 DMA350_CH_SRCTRIGINTYPE_SOFTWARE_ONLY = 0,
234 DMA350_CH_SRCTRIGINTYPE_HW = DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_1,
235 DMA350_CH_SRCTRIGINTYPE_INTERNAL = DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_1 |
236 DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_0
237 };
238
239 /* ARM DMA350 DMA Channel Source Trigger Input Mode */
240 enum dma350_ch_srctriginmode_t {
241 DMA350_CH_SRCTRIGINMODE_CMD = 0,
242 DMA350_CH_SRCTRIGINMODE_DMA_FLOW_CTRL = DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_1,
243 DMA350_CH_SRCTRIGINMODE_PERIPH_FLOW_CTRL =
244 DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_1 |
245 DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_0
246 };
247
248 /* ARM DMA350 DMA Channel Destination Trigger Input Type */
249 enum dma350_ch_destrigintype_t {
250 DMA350_CH_DESTRIGINTYPE_SOFTWARE_ONLY = 0,
251 DMA350_CH_DESTRIGINTYPE_HW = DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_1,
252 DMA350_CH_DESTRIGINTYPE_INTERNAL = DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_1 |
253 DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_0
254 };
255
256 /* ARM DMA350 DMA Channel Destination Trigger Input Mode */
257 enum dma350_ch_destriginmode_t {
258 DMA350_CH_DESTRIGINMODE_CMD = 0,
259 DMA350_CH_DESTRIGINMODE_DMA_FLOW_CTRL = DMA_CH_DESTRIGINCFG_DESTRIGINMODE_1,
260 DMA350_CH_DESTRIGINMODE_PERIPH_FLOW_CTRL =
261 DMA_CH_DESTRIGINCFG_DESTRIGINMODE_1 |
262 DMA_CH_DESTRIGINCFG_DESTRIGINMODE_0
263 };
264
265 /* ARM DMA350 DMA Channel Trigger Output Type */
266 enum dma350_ch_trigouttype_t {
267 DMA350_CH_TRIGOUTTYPE_SOFTWARE_ONLY = 0,
268 DMA350_CH_TRIGOUTTYPE_HW = DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_1,
269 DMA350_CH_TRIGOUTTYPE_INTERNAL =
270 DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_1 | DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_0
271 };
272
273 /* ARM DMA350 DMA Channel Stream Interface operation Type */
274 enum dma350_ch_streamtype_t {
275 DMA350_CH_STREAMTYPE_IN_OUT = 0,
276 DMA350_CH_STREAMTYPE_OUT_ONLY = DMA_CH_STREAMINTCFG_STREAMTYPE_0,
277 DMA350_CH_STREAMTYPE_IN_ONLY = DMA_CH_STREAMINTCFG_STREAMTYPE_1
278 };
279
280 /* ARM DMA350 DMA Channel Status Type */
281 union dma350_ch_status_t {
282 struct {
283 uint32_t INTR_DONE:1; /*!< bit: 0 INTR_DONE */
284 uint32_t INTR_ERR:1; /*!< bit: 1 INTR_ERR */
285 uint32_t INTR_DISABLED:1; /*!< bit: 2 INTR_DISABLED */
286 uint32_t INTR_STOPPED:1; /*!< bit: 3 INTR_STOPPED */
287 uint32_t RESERVED0:4; /*!< bit: 4.. 7 RESERVED0[ 3:0] */
288 uint32_t INTR_SRCTRIGINWAIT:1; /*!< bit: 8 INTR_SRCTRIGINWAIT */
289 uint32_t INTR_DESTRIGINWAIT:1; /*!< bit: 9 INTR_DESTRIGINWAIT */
290 uint32_t INTR_TRIGOUTACKWAIT:1; /*!< bit: 10 INTR_TRIGOUTACKWAIT */
291 uint32_t RESERVED1:5; /*!< bit: 11..15 RESERVED1[ 4:0] */
292 uint32_t STAT_DONE:1; /*!< bit: 16 STAT_DONE */
293 uint32_t STAT_ERR:1; /*!< bit: 17 STAT_ERR */
294 uint32_t STAT_DISABLED:1; /*!< bit: 18 STAT_DISABLED */
295 uint32_t STAT_STOPPED:1; /*!< bit: 19 STAT_STOPPED */
296 uint32_t STAT_PAUSED:1; /*!< bit: 20 STAT_PAUSED */
297 uint32_t STAT_RESUMEWAIT:1; /*!< bit: 21 STAT_RESUMEWAIT */
298 uint32_t RESERVED2:2; /*!< bit: 22..23 RESERVED2[ 1:0] */
299 uint32_t STAT_SRCTRIGINWAIT:1; /*!< bit: 24 STAT_SRCTRIGINWAIT */
300 uint32_t STAT_DESTRIGINWAIT:1; /*!< bit: 25 STAT_DESTRIGINWAIT */
301 uint32_t STAT_TRIGOUTACKWAIT:1; /*!< bit: 26 STAT_TRIGOUTACKWAIT */
302 uint32_t RESERVED3:5; /*!< bit: 27..31 RESERVED3[ 4:0] */
303 } b; /*!< Structure used for bit access */
304 uint32_t w; /*!< Type used for word access */
305 };
306
307 /* ARM DMA350 DMA Command link register structure */
308 /* Note: Field order must match the order of the bits in the header */
309 struct dma350_cmdlink_reg_t {
310 /* Note: REGCLEAR (Bit 0) has no associated field and Bit 1 is reserved */
311 uint32_t intren; /* Bit 2 */
312 uint32_t ctrl; /* Bit 3 */
313 uint32_t srcaddr; /* Bit 4 */
314 uint32_t srcaddrhi; /* Bit 5 */
315 uint32_t desaddr; /* Bit 6 */
316 uint32_t desaddrhi; /* Bit 7 */
317 uint32_t xsize; /* Bit 8 */
318 uint32_t xsizehi; /* Bit 9 */
319 uint32_t srctranscfg; /* Bit 10 */
320 uint32_t destranscfg; /* Bit 11 */
321 uint32_t xaddrinc; /* Bit 12 */
322 uint32_t yaddrstride; /* Bit 13 */
323 uint32_t fillval; /* Bit 14 */
324 uint32_t ysize; /* Bit 15 */
325 uint32_t tmpltcfg; /* Bit 16 */
326 uint32_t srctmplt; /* Bit 17 */
327 uint32_t destmplt; /* Bit 18 */
328 uint32_t srctrigincfg; /* Bit 19 */
329 uint32_t destrigincfg; /* Bit 20 */
330 uint32_t trigoutcfg; /* Bit 21 */
331 uint32_t gpoen0; /* Bit 22 */
332 uint32_t reserved0; /* Bit 23 */
333 uint32_t gpoval0; /* Bit 24 */
334 uint32_t reserved1; /* Bit 25 */
335 uint32_t streamintcfg; /* Bit 26 */
336 uint32_t reserved2; /* Bit 27 */
337 uint32_t linkattr; /* Bit 28 */
338 uint32_t autocfg; /* Bit 29 */
339 uint32_t linkaddr; /* Bit 30 */
340 uint32_t linkaddrhi; /* Bit 31 */
341 };
342
343 /* ARM DMA350 DMA Command link generator config structure */
344 struct dma350_cmdlink_gencfg_t {
345 uint32_t header;
346 struct dma350_cmdlink_reg_t cfg;
347 };
348
349 /**
350 * \brief Initializes DMA350 DMA Channel
351 *
352 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
353 *
354 * \return Returns error code as specified in \ref dma350_ch_error_t
355 *
356 * \note This function doesn't check if dev is NULL.
357 */
358 enum dma350_ch_error_t dma350_ch_init(struct dma350_ch_dev_t *dev);
359
360 /**
361 * \brief Checks if DMA350 device is initialised
362 *
363 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
364 *
365 * \return Returns true if device is initialized
366 *
367 * \note This function doesn't check if dev is NULL.
368 */
369 __STATIC_INLINE
370 bool dma350_ch_is_init(const struct dma350_ch_dev_t *dev);
371
372 /**
373 * \brief Sets source address[31:0] of channel
374 *
375 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
376 * \param[in] src_addr source address, where to copy from
377 *
378 * \return void
379 *
380 * \note This function doesn't check if dev is NULL or if it has been init.
381 */
382 __STATIC_INLINE
383 void dma350_ch_set_src(struct dma350_ch_dev_t *dev, uint32_t src_addr);
384
385 /**
386 * \brief Sets destination address[31:0] of channel
387 *
388 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
389 * \param[in] des_addr destination address, where to copy to
390 *
391 * \return void
392 *
393 * \note This function doesn't check if dev is NULL or if it has been init.
394 */
395 __STATIC_INLINE
396 void dma350_ch_set_des(struct dma350_ch_dev_t *dev, uint32_t des_addr);
397
398 /**
399 * \brief Sets Channel Priority
400 *
401 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
402 * \param[in] chprio Number of priority
403 *
404 * \return void
405 */
406 __STATIC_INLINE
407 void dma350_ch_set_chprio(struct dma350_ch_dev_t *dev, uint8_t chprio);
408
409 /**
410 * \brief Sets number of copies in the x dimension
411 *
412 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
413 * \param[in] src_xsize number of source elements in the x dimension
414 * \param[in] des_xsize number of destination elements in the x dimension
415 *
416 * \return void
417 *
418 * \note This function doesn't check if dev is NULL or if it has been init.
419 */
420 __STATIC_INLINE
421 void dma350_ch_set_xsize16(struct dma350_ch_dev_t *dev, uint16_t src_xsize,
422 uint16_t des_xsize);
423
424 /**
425 * \brief Sets number of copies in the x dimension
426 *
427 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
428 * \param[in] src_xsize number of source elements in the x dimension
429 * \param[in] des_xsize number of destination elements in the x dimension
430 *
431 * \return void
432 *
433 * \note This function doesn't check if dev is NULL or if it has been init.
434 */
435 __STATIC_INLINE
436 void dma350_ch_set_xsize32(struct dma350_ch_dev_t *dev, uint32_t src_xsize,
437 uint32_t des_xsize);
438
439 /**
440 * \brief Sets number of copies in the y dimension
441 *
442 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
443 * \param[in] src_ysize number of source elements in the y dimension
444 * \param[in] des_ysize number of destination elements in the y dimension
445 *
446 * \return void
447 *
448 * \note This function doesn't check if dev is NULL or if it has been init.
449 */
450 __STATIC_INLINE
451 void dma350_ch_set_ysize16(struct dma350_ch_dev_t *dev, uint16_t src_ysize,
452 uint16_t des_ysize);
453
454 /**
455 * \brief Sets address stride between pixels of adjacent lines
456 *
457 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
458 * \param[in] src_yaddrstride address stride of source
459 * \param[in] des_yaddrstride address stride of destination
460 *
461 * \return void
462 *
463 * \note This function doesn't check if dev is NULL or if it has been init.
464 */
465 __STATIC_INLINE
466 void dma350_ch_set_yaddrstride(struct dma350_ch_dev_t *dev,
467 uint16_t src_yaddrstride,
468 uint16_t des_yaddrstride);
469
470 /**
471 * \brief Sets size of each transfer
472 *
473 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
474 * \param[in] transize size of each transfer \ref dma350_ch_transize_t
475 *
476 * \return void
477 *
478 * \note This function doesn't check if dev is NULL or if it has been init.
479 */
480 __STATIC_INLINE
481 void dma350_ch_set_transize(struct dma350_ch_dev_t *dev,
482 enum dma350_ch_transize_t transize);
483
484 /**
485 * \brief Sets type of operation in the x dimension
486 *
487 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
488 * \param[in] xtype type of operation in the x dimension
489 * \ref dma350_ch_xtype_t
490 *
491 * \return void
492 *
493 * \note This function doesn't check if dev is NULL or if it has been init.
494 */
495 __STATIC_INLINE
496 void dma350_ch_set_xtype(struct dma350_ch_dev_t *dev,
497 enum dma350_ch_xtype_t xtype);
498
499 /**
500 * \brief Sets type of operation in the y dimension
501 *
502 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
503 * \param[in] ytype type of operation in the y dimension
504 * \ref dma350_ch_ytype_t
505 *
506 * \return void
507 *
508 * \note Set to disabled (default) means 1D copy.
509 * \note This function doesn't check if dev is NULL or if it has been init.
510 */
511 __STATIC_INLINE
512 void dma350_ch_set_ytype(struct dma350_ch_dev_t *dev,
513 enum dma350_ch_ytype_t ytype);
514
515 /**
516 * \brief Sets type of automatic register reloading
517 *
518 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
519 * \param[in] regreloadtype type of autoreload \ref dma350_ch_regreloadtype_t
520 *
521 * \return void
522 *
523 * \note This function doesn't check if dev is NULL or if it has been init.
524 */
525 __STATIC_INLINE
526 void dma350_ch_set_regreloadtype(struct dma350_ch_dev_t *dev,
527 enum dma350_ch_regreloadtype_t regreloadtype);
528
529 /**
530 * \brief Configures when STAT_DONE flag is asserted for this command
531 *
532 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
533 * \param[in] donetype donetype of command \ref dma350_ch_donetype_t
534 *
535 * \return void
536 *
537 * \note This function doesn't check if dev is NULL or if it has been init.
538 */
539 __STATIC_INLINE
540 void dma350_ch_set_donetype(struct dma350_ch_dev_t *dev,
541 enum dma350_ch_donetype_t donetype);
542
543 /**
544 * \brief Enables Done pause use for this command
545 *
546 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
547 *
548 * \return void
549 *
550 * \note This function doesn't check if dev is NULL or if it has been init.
551 */
552 __STATIC_INLINE
553 void dma350_ch_enable_donepause(struct dma350_ch_dev_t *dev);
554
555 /**
556 * \brief Disables Done pause use for this command
557 *
558 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
559 *
560 * \return void
561 *
562 * \note This function doesn't check if dev is NULL or if it has been init.
563 */
564 __STATIC_INLINE
565 void dma350_ch_disable_donepause(struct dma350_ch_dev_t *dev);
566
567 /**
568 * \brief Enables Source Trigger Input use for this command
569 *
570 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
571 *
572 * \return void
573 *
574 * \note This function doesn't check if dev is NULL or if it has been init.
575 */
576 __STATIC_INLINE
577 void dma350_ch_enable_srctrigin(struct dma350_ch_dev_t *dev);
578
579 /**
580 * \brief Disables Source Trigger Input use for this command
581 *
582 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
583 *
584 * \return void
585 *
586 * \note This function doesn't check if dev is NULL or if it has been init.
587 */
588 __STATIC_INLINE
589 void dma350_ch_disable_srctrigin(struct dma350_ch_dev_t *dev);
590
591 /**
592 * \brief Enables Destination Trigger Input use for this command
593 *
594 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
595 *
596 * \return void
597 *
598 * \note This function doesn't check if dev is NULL or if it has been init.
599 */
600 __STATIC_INLINE
601 void dma350_ch_enable_destrigin(struct dma350_ch_dev_t *dev);
602
603 /**
604 * \brief Disables Destination Trigger Input use for this command
605 *
606 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
607 *
608 * \return void
609 *
610 * \note This function doesn't check if dev is NULL or if it has been init.
611 */
612 __STATIC_INLINE
613 void dma350_ch_disable_destrigin(struct dma350_ch_dev_t *dev);
614
615 /**
616 * \brief Enables Trigger Onput use for this command
617 *
618 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
619 *
620 * \return void
621 *
622 * \note This function doesn't check if dev is NULL or if it has been init.
623 */
624 __STATIC_INLINE
625 void dma350_ch_enable_trigout(struct dma350_ch_dev_t *dev);
626
627 /**
628 * \brief Disables Trigger Onput use for this command
629 *
630 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
631 *
632 * \return void
633 *
634 * \note This function doesn't check if dev is NULL or if it has been init.
635 */
636 __STATIC_INLINE
637 void dma350_ch_disable_trigout(struct dma350_ch_dev_t *dev);
638
639 /**
640 * \brief Enables GPO use for this command
641 *
642 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
643 *
644 * \return void
645 *
646 * \note This function doesn't check if dev is NULL or if it has been init.
647 */
648 __STATIC_INLINE
649 void dma350_ch_enable_gpo(struct dma350_ch_dev_t *dev);
650
651 /**
652 * \brief Disables GPO use for this command
653 *
654 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
655 *
656 * \return void
657 *
658 * \note This function doesn't check if dev is NULL or if it has been init.
659 */
660 __STATIC_INLINE
661 void dma350_ch_disable_gpo(struct dma350_ch_dev_t *dev);
662
663 /**
664 * \brief Enables Stream Interface use for this command
665 *
666 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
667 *
668 * \return void
669 *
670 * \note This function doesn't check if dev is NULL or if it has been init.
671 */
672 __STATIC_INLINE
673 void dma350_ch_enable_stream(struct dma350_ch_dev_t *dev);
674
675 /**
676 * \brief Disables Stream Interface use for this command
677 *
678 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
679 *
680 * \return void
681 *
682 * \note This function doesn't check if dev is NULL or if it has been init.
683 */
684 __STATIC_INLINE
685 void dma350_ch_disable_stream(struct dma350_ch_dev_t *dev);
686
687 /**
688 * \brief Sets Source Transfer Memory Attribute and shareability
689 *
690 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
691 * \param[in] memattr Attribute field
692 * \param[in] shareattr Shareability attribute field (2 bits)
693 *
694 * \return void
695 */
696 __STATIC_INLINE
697 void dma350_ch_set_srcmemattr(struct dma350_ch_dev_t *dev, uint8_t memattr,
698 uint8_t shareattr);
699
700 /**
701 * \brief Sets Source Transfer Memory Attribute field[3:0]
702 *
703 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
704 * \param[in] memattrlo Attribute field (4 bits)
705 *
706 * \return void
707 */
708 __STATIC_INLINE
709 void dma350_ch_set_srcmemattrlo(struct dma350_ch_dev_t *dev, uint8_t memattrlo);
710
711 /**
712 * \brief Sets Source Transfer Memory Attribute field[7:4]
713 *
714 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
715 * \param[in] memattrhi Attribute field (4 bits)
716 *
717 * \return void
718 */
719 __STATIC_INLINE
720 void dma350_ch_set_srcmemattrhi(struct dma350_ch_dev_t *dev, uint8_t memattrhi);
721
722 /**
723 * \brief Sets Source Transfer Shareability Attribute
724 *
725 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
726 * \param[in] shareattr Shareability attribute field (2 bits)
727 *
728 * \return void
729 */
730 __STATIC_INLINE
731 void dma350_ch_set_srcshareattr(struct dma350_ch_dev_t *dev, uint8_t shareattr);
732
733 /**
734 * \brief Sets Destination Transfer Memory Attribute and shareability
735 *
736 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
737 * \param[in] memattr Attribute field
738 * \param[in] shareattr Shareability attribute field (2 bits)
739 *
740 * \return void
741 */
742 __STATIC_INLINE
743 void dma350_ch_set_desmemattr(struct dma350_ch_dev_t *dev, uint8_t memattr,
744 uint8_t shareattr);
745
746 /**
747 * \brief Sets Destination Transfer Memory Attribute field[3:0]
748 *
749 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
750 * \param[in] memattrlo Attribute field (4 bits)
751 *
752 * \return void
753 */
754 __STATIC_INLINE
755 void dma350_ch_set_desmemattrlo(struct dma350_ch_dev_t *dev, uint8_t memattrlo);
756
757 /**
758 * \brief Sets Destination Transfer Memory Attribute field[7:4]
759 *
760 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
761 * \param[in] memattrhi Attribute field (4 bits)
762 *
763 * \return void
764 */
765 __STATIC_INLINE
766 void dma350_ch_set_desmemattrhi(struct dma350_ch_dev_t *dev, uint8_t memattrhi);
767
768 /**
769 * \brief Sets Destination Transfer Shareability Attribute
770 *
771 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
772 * \param[in] shareattr Attribute field (2 bits)
773 *
774 * \return void
775 */
776 __STATIC_INLINE
777 void dma350_ch_set_desshareattr(struct dma350_ch_dev_t *dev, uint8_t shareattr);
778
779 /**
780 * \brief Sets source transfer to be secure
781 *
782 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
783 *
784 * \return void
785 *
786 * \note This function doesn't check if dev is NULL or if it has been init.
787 */
788 __STATIC_INLINE
789 void dma350_ch_set_src_trans_secure(struct dma350_ch_dev_t *dev);
790
791 /**
792 * \brief Sets source transfer to be non-secure
793 *
794 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
795 *
796 * \return void
797 *
798 * \note This function doesn't check if dev is NULL or if it has been init.
799 */
800 __STATIC_INLINE
801 void dma350_ch_set_src_trans_nonsecure(struct dma350_ch_dev_t *dev);
802
803 /**
804 * \brief Sets destination transfer to be secure
805 *
806 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
807 *
808 * \return void
809 *
810 * \note This function doesn't check if dev is NULL or if it has been init.
811 */
812 __STATIC_INLINE
813 void dma350_ch_set_des_trans_secure(struct dma350_ch_dev_t *dev);
814
815 /**
816 * \brief Sets destination transfer to be non-secure
817 *
818 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
819 *
820 * \return void
821 *
822 * \note This function doesn't check if dev is NULL or if it has been init.
823 */
824 __STATIC_INLINE
825 void dma350_ch_set_des_trans_nonsecure(struct dma350_ch_dev_t *dev);
826
827 /**
828 * \brief Sets source transfer to be privileged
829 *
830 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
831 *
832 * \return void
833 *
834 * \note This function doesn't check if dev is NULL or if it has been init.
835 */
836 __STATIC_INLINE
837 void dma350_ch_set_src_trans_privileged(struct dma350_ch_dev_t *dev);
838
839 /**
840 * \brief Sets source transfer to be unprivileged
841 *
842 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
843 *
844 * \return void
845 *
846 * \note This function doesn't check if dev is NULL or if it has been init.
847 */
848 __STATIC_INLINE
849 void dma350_ch_set_src_trans_unprivileged(struct dma350_ch_dev_t *dev);
850
851 /**
852 * \brief Sets destination transfer to be privileged
853 *
854 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
855 *
856 * \return void
857 *
858 * \note This function doesn't check if dev is NULL or if it has been init.
859 */
860 __STATIC_INLINE
861 void dma350_ch_set_des_trans_privileged(struct dma350_ch_dev_t *dev);
862
863 /**
864 * \brief Sets destination transfer to be unprivileged
865 *
866 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
867 *
868 * \return void
869 *
870 * \note This function doesn't check if dev is NULL or if it has been init.
871 */
872 __STATIC_INLINE
873 void dma350_ch_set_des_trans_unprivileged(struct dma350_ch_dev_t *dev);
874
875 /**
876 * \brief Sets Source Max Burst Lenght
877 *
878 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
879 * \param[in] length Value of max burst length
880 *
881 * \return void
882 */
883 __STATIC_INLINE
884 void dma350_ch_set_srcmaxburstlen(struct dma350_ch_dev_t *dev, uint8_t length);
885
886 /**
887 * \brief Sets Destination Max Burst Lenght
888 *
889 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
890 * \param[in] length Value of max burst length
891 *
892 * \return void
893 */
894 __STATIC_INLINE
895 void dma350_ch_set_desmaxburstlen(struct dma350_ch_dev_t *dev, uint8_t length);
896
897 /**
898 * \brief Sets source address increment after each transfer
899 *
900 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
901 * \param[in] src_xaddr_inc increment of source address
902 *
903 * \return void
904 *
905 * \note This function doesn't check if dev is NULL or if it has been init.
906 */
907 __STATIC_INLINE
908 void dma350_ch_set_src_xaddr_inc(struct dma350_ch_dev_t *dev,
909 int16_t src_xaddr_inc);
910
911 /**
912 * \brief Sets destination address increment after each transfer
913 *
914 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
915 * \param[in] des_xaddr_inc increment of destination address
916 *
917 * \return void
918 *
919 * \note This function doesn't check if dev is NULL or if it has been init.
920 */
921 __STATIC_INLINE
922 void dma350_ch_set_des_xaddr_inc(struct dma350_ch_dev_t *dev,
923 int16_t des_xaddr_inc);
924
925 /**
926 * \brief Sets source and destination address increment after each transfer
927 *
928 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
929 * \param[in] src_xaddr_inc increment of source address
930 * \param[in] des_xaddr_inc increment of destination address
931 *
932 * \return void
933 *
934 * \note This function doesn't check if dev is NULL or if it has been init.
935 */
936 __STATIC_INLINE
937 void dma350_ch_set_xaddr_inc(struct dma350_ch_dev_t *dev, int16_t src_xaddr_inc,
938 int16_t des_xaddr_inc);
939
940 /**
941 * \brief Sets fill value
942 *
943 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
944 * \param[in] fill_value fill value
945 *
946 * \return void
947 *
948 * \note This function doesn't check if dev is NULL or if it has been init.
949 */
950 __STATIC_INLINE
951 void dma350_ch_set_fill_value(struct dma350_ch_dev_t *dev, uint32_t fill_value);
952
953 /**
954 * \brief Commands a channel of DMA350 DMA.
955 *
956 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
957 * \param[in] cmd DMA350 DMA channel command \ref dma350_ch_cmd_t
958 *
959 * \return void
960 *
961 * \note This function doesn't check if dev is NULL or if it has been init.
962 */
963 __STATIC_INLINE
964 void dma350_ch_cmd(struct dma350_ch_dev_t *dev, enum dma350_ch_cmd_t cmd);
965
966 /**
967 * \brief Gets current command of DMA350 DMA channel.
968 *
969 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
970 *
971 * \return Returns channel command specified in \ref dma350_ch_cmd_t
972 *
973 * \note This function doesn't check if dev is NULL.
974 */
975 __STATIC_INLINE
976 enum dma350_ch_cmd_t dma350_ch_get_cmd(struct dma350_ch_dev_t *dev);
977
978 /**
979 * \brief Enables Interrupt for DMA350 DMA channel
980 *
981 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
982 * \param[in] intr Interrupt(s) to enable \ref dma350_ch_intr_t
983 *
984 * \return void
985 *
986 * \note This function doesn't check if dev is NULL or if it has been init.
987 */
988 __STATIC_INLINE
989 void dma350_ch_enable_intr(struct dma350_ch_dev_t *dev,
990 enum dma350_ch_intr_t intr);
991
992 /**
993 * \brief Disables Interrupt for DMA350 DMA channel
994 *
995 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
996 * \param[in] intr Interrupt(s) to disable \ref dma350_ch_intr_t
997 *
998 * \return void
999 *
1000 * \note This function doesn't check if dev is NULL or if it has been init.
1001 */
1002 __STATIC_INLINE
1003 void dma350_ch_disable_intr(struct dma350_ch_dev_t *dev,
1004 enum dma350_ch_intr_t intr);
1005
1006 /**
1007 * \brief Get Interrupt status of DMA350 DMA channel
1008 *
1009 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1010 * \param[in] intr Interrupt to check \ref dma350_ch_intr_t
1011 *
1012 * \return Returns True if interrupt is active, False otherwise
1013 *
1014 * \note Interrupt had to be enabled prior for this function to return True.
1015 * This function doesn't check if dev is NULL or if it has been init.
1016 */
1017 __STATIC_INLINE
1018 bool dma350_ch_is_intr_set(struct dma350_ch_dev_t *dev,
1019 enum dma350_ch_intr_t intr);
1020
1021 /**
1022 * \brief Get Status bit of DMA350 DMA channel
1023 *
1024 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1025 * \param[in] stat Status bit(s) to check \ref dma350_ch_stat_t
1026 *
1027 * \return Returns True if status of interrupt is active, False otherwise.
1028 *
1029 * \note Status of interrupt is independent from whether the interrupt is
1030 * enabled.
1031 * This function doesn't check if dev is NULL or if it has been init.
1032 */
1033 __STATIC_INLINE
1034 bool dma350_ch_is_stat_set(struct dma350_ch_dev_t *dev,
1035 enum dma350_ch_stat_t stat);
1036
1037 /**
1038 * \brief Clear Status bit of DMA350 DMA channel
1039 *
1040 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1041 * \param[in] stat Status bit(s) to clear \ref dma350_ch_stat_t
1042 *
1043 * \return void
1044 *
1045 * \note This function doesn't check if dev is NULL or if it has been init.
1046 */
1047 __STATIC_INLINE
1048 void dma350_ch_clear_stat(struct dma350_ch_dev_t *dev,
1049 enum dma350_ch_stat_t stat);
1050
1051 /**
1052 * \brief Set automatic command reload count for DMA350 DMA channel
1053 *
1054 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1055 * \param[in] cnt Number of command reloads
1056 *
1057 * \return void
1058 *
1059 * \note This command implicitly disables infinite command reload.
1060 * This function doesn't check if dev is NULL or if it has been init.
1061 */
1062 __STATIC_INLINE
1063 void dma350_ch_set_autocfg_restart_cnt(struct dma350_ch_dev_t *dev,
1064 uint16_t cnt);
1065
1066 /**
1067 * \brief Set infinite command reload for DMA350 DMA channel
1068 *
1069 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1070 *
1071 * \return void
1072 *
1073 * \note This command implicitly clears command reload count.
1074 * Infinite restart can be cleared by setting counter to 0.
1075 * This function doesn't check if dev is NULL or if it has been init.
1076 */
1077 __STATIC_INLINE
1078 void dma350_ch_set_autocfg_restart_inf(struct dma350_ch_dev_t *dev);
1079
1080 /**
1081 * \brief Set source template size of DMA350 DMA channel
1082 *
1083 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1084 * \param[in] size Number of 1s in template minus 1. 0 means disabled.
1085 *
1086 * \return void
1087 *
1088 * \note This function doesn't check if dev is NULL or if it has been init.
1089 */
1090 __STATIC_INLINE
1091 void dma350_ch_set_tmplt_src_size(struct dma350_ch_dev_t *dev, uint32_t size);
1092
1093 /**
1094 * \brief Set destination template size of DMA350 DMA channel
1095 *
1096 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1097 * \param[in] size Number of 1s in template minus 1. 0 means disabled.
1098 *
1099 * \return void
1100 *
1101 * \note This function doesn't check if dev is NULL or if it has been init.
1102 */
1103 __STATIC_INLINE
1104 void dma350_ch_set_tmplt_des_size(struct dma350_ch_dev_t *dev, uint32_t size);
1105
1106 /**
1107 * \brief Set source template of DMA350 DMA channel
1108 *
1109 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1110 * \param[in] tmplt Template of the source side. Bit[0] is ignored, it is
1111 * always 1.
1112 *
1113 * \return void
1114 *
1115 * \note This function doesn't check if dev is NULL or if it has been init.
1116 */
1117 __STATIC_INLINE
1118 void dma350_ch_set_tmplt_src(struct dma350_ch_dev_t *dev, uint32_t tmplt);
1119
1120 /**
1121 * \brief Set destination template of DMA350 DMA channel
1122 *
1123 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1124 * \param[in] tmplt Template of the destination side. Bit[0] is ignored,
1125 * it is always 1.
1126 *
1127 * \return void
1128 *
1129 * \note This function doesn't check if dev is NULL or if it has been init.
1130 */
1131 __STATIC_INLINE
1132 void dma350_ch_set_tmplt_des(struct dma350_ch_dev_t *dev, uint32_t tmplt);
1133
1134 /**
1135 * \brief Get source template of DMA350 DMA channel
1136 *
1137 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1138 *
1139 * \return Template of the source side
1140 *
1141 * \note This function doesn't check if dev is NULL or if it has been init.
1142 */
1143 __STATIC_INLINE
1144 uint32_t dma350_ch_get_tmplt_src(struct dma350_ch_dev_t *dev);
1145
1146 /**
1147 * \brief Get destination template of DMA350 DMA channel
1148 *
1149 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1150 *
1151 * \return Template of the destination side
1152 *
1153 * \note This function doesn't check if dev is NULL or if it has been init.
1154 */
1155 __STATIC_INLINE
1156 uint32_t dma350_ch_get_tmplt_des(struct dma350_ch_dev_t *dev);
1157
1158 /**
1159 * \brief Sets Source Trigger Input Select
1160 *
1161 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1162 * \param[in] srctriginsel Input Select value
1163 *
1164 * \return void
1165 */
1166 __STATIC_INLINE
1167 void dma350_ch_set_srctriginsel(struct dma350_ch_dev_t *dev,
1168 uint8_t srctriginsel);
1169
1170 /**
1171 * \brief Sets Source Trigger Input Type
1172 *
1173 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1174 * \param[in] type Input type \ref dma350_ch_srctrigintype_t
1175 *
1176 * \return void
1177 */
1178 __STATIC_INLINE
1179 void dma350_ch_set_srctrigintype(struct dma350_ch_dev_t *dev,
1180 enum dma350_ch_srctrigintype_t type);
1181
1182 /**
1183 * \brief Sets Source Trigger Input Mode
1184 *
1185 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1186 * \param[in] mode Mode \ref dma350_ch_srctriginmode_t
1187 *
1188 * \return void
1189 */
1190 __STATIC_INLINE
1191 void dma350_ch_set_srctriginmode(struct dma350_ch_dev_t *dev,
1192 enum dma350_ch_srctriginmode_t mode);
1193
1194 /**
1195 * \brief Sets Source Trigger Input Default Transfer Size
1196 *
1197 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1198 * \param[in] blksize Size value
1199 *
1200 * \return void
1201 */
1202 __STATIC_INLINE
1203 void dma350_ch_set_srctriginblksize(struct dma350_ch_dev_t *dev,
1204 uint8_t blksize);
1205
1206 /**
1207 * \brief Sets Destination Trigger Input Select
1208 *
1209 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1210 * \param[in] destriginsel Input Select value
1211 *
1212 * \return void
1213 */
1214 __STATIC_INLINE
1215 void dma350_ch_set_destriginsel(struct dma350_ch_dev_t *dev,
1216 uint8_t destriginsel);
1217
1218 /**
1219 * \brief Sets Destination Trigger Input Type
1220 *
1221 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1222 * \param[in] type Input type \ref dma350_ch_destrigintype_t
1223 *
1224 * \return void
1225 */
1226 __STATIC_INLINE
1227 void dma350_ch_set_destrigintype(struct dma350_ch_dev_t *dev,
1228 enum dma350_ch_destrigintype_t type);
1229
1230 /**
1231 * \brief Sets Destination Trigger Input Mode
1232 *
1233 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1234 * \param[in] mode Mode \ref dma350_ch_destriginmode_t
1235 *
1236 * \return void
1237 */
1238 __STATIC_INLINE
1239 void dma350_ch_set_destriginmode(struct dma350_ch_dev_t *dev,
1240 enum dma350_ch_destriginmode_t mode);
1241
1242 /**
1243 * \brief Sets Destination Trigger Input Default Transfer Size
1244 *
1245 *
1246 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1247 * \param[in] blksize Size value
1248 *
1249 * \return void
1250 */
1251 __STATIC_INLINE
1252 void dma350_ch_set_destriginblksize(struct dma350_ch_dev_t *dev,
1253 uint8_t blksize);
1254
1255 /**
1256 * \brief Sets Trigger Output Select
1257 *
1258 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1259 * \param[in] trigoutsel Select value
1260 *
1261 * \return void
1262 */
1263 __STATIC_INLINE
1264 void dma350_ch_set_trigoutsel(struct dma350_ch_dev_t *dev, uint8_t trigoutsel);
1265
1266 /**
1267 * \brief Sets Trigger Output Type
1268 *
1269 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1270 * \param[in] type Output type \ref dma350_ch_trigouttype_t
1271 *
1272 * \return void
1273 */
1274 __STATIC_INLINE
1275 void dma350_ch_set_trigouttype(struct dma350_ch_dev_t *dev,
1276 enum dma350_ch_trigouttype_t type);
1277
1278 /**
1279 * \brief Sets which GPO ports 0-31 are enabled to change at the beginning
1280 * of current DMA command
1281 *
1282 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1283 * \param[in] gpoen0 Enable mask value
1284 *
1285 * \return void
1286 */
1287 __STATIC_INLINE
1288 void dma350_ch_set_gpoen0(struct dma350_ch_dev_t *dev, uint32_t gpoen0);
1289
1290 /**
1291 * \brief Sets the value to be driven on the GPO ports 0-31 that are enabled
1292 *
1293 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1294 * \param[in] gpoval0 General Purpose Output Value GPO[31:0]
1295 *
1296 * \return void
1297 */
1298 __STATIC_INLINE
1299 void dma350_ch_set_gpoval0(struct dma350_ch_dev_t *dev, uint32_t gpoval0);
1300
1301 /**
1302 * \brief Gets the current value of the GPO ports, bits 0-31
1303 *
1304 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1305 *
1306 * \return General Purpose Output Value GPO[31:0]
1307 */
1308 __STATIC_INLINE
1309 uint32_t dma350_ch_get_gpoval0(struct dma350_ch_dev_t *dev);
1310
1311 /**
1312 * \brief Sets Stream Interface operation Type
1313 *
1314 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1315 * \param[in] type Type \ref dma350_ch_streamtype_t
1316 *
1317 * \return void
1318 */
1319 __STATIC_INLINE
1320 void dma350_ch_set_streamtype(struct dma350_ch_dev_t *dev,
1321 enum dma350_ch_streamtype_t type);
1322
1323 /**
1324 * \brief Sets Link Address Read Transfer Memory Attribute[3:0] field
1325 *
1326 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1327 * \param[in] memattrlo Attribute field
1328 *
1329 * \return void
1330 */
1331 __STATIC_INLINE
1332 void dma350_ch_set_linkmemattrlo(struct dma350_ch_dev_t *dev,
1333 uint8_t memattrlo);
1334
1335 /**
1336 * \brief Sets Link Address Read Transfer Memory Attribute[7:4] field
1337 *
1338 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1339 * \param[in] memattrlo Attribute field
1340 *
1341 * \return void
1342 */
1343 __STATIC_INLINE
1344 void dma350_ch_set_linkmemattrhi(struct dma350_ch_dev_t *dev,
1345 uint8_t memattrhi);
1346
1347 /**
1348 * \brief Sets Link Address Transfer Shareability Attribute
1349 *
1350 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1351 * \param[in] shareattr Attribute field
1352 *
1353 * \return void
1354 */
1355 __STATIC_INLINE
1356 void dma350_ch_set_linkshareattr(struct dma350_ch_dev_t *dev,
1357 uint8_t shareattr);
1358
1359 /**
1360 * \brief Enables Link Address
1361 *
1362 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1363 *
1364 * \return void
1365 */
1366 __STATIC_INLINE
1367 void dma350_ch_enable_linkaddr(struct dma350_ch_dev_t *dev);
1368
1369 /**
1370 * \brief Disables Link Address
1371 *
1372 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1373 *
1374 * \return void
1375 */
1376 __STATIC_INLINE
1377 void dma350_ch_disable_linkaddr(struct dma350_ch_dev_t *dev);
1378
1379 /**
1380 * \brief Sets Link Address Pointer [31:2]
1381 *
1382 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1383 * \param[in] linkaddr Memory location of the destination
1384 *
1385 * \return void
1386 */
1387 __STATIC_INLINE
1388 void dma350_ch_set_linkaddr32(struct dma350_ch_dev_t *dev, uint32_t linkaddr);
1389
1390 /**
1391 * \brief Checks if DMA350 DMA channel is busy.
1392 *
1393 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1394 *
1395 * \return Returns True if channel is busy, False if ready
1396 *
1397 * \note This function doesn't check if dev is NULL.
1398 */
1399 __STATIC_INLINE
1400 bool dma350_ch_is_busy(struct dma350_ch_dev_t *dev);
1401
1402 /**
1403 * \brief Checks if DMA350 DMA channel is ready.
1404 *
1405 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1406 *
1407 * \return Returns True if channel is ready, False if busy
1408 *
1409 * \note This function doesn't check if dev is NULL.
1410 */
1411 __STATIC_INLINE
1412 bool dma350_ch_is_ready(struct dma350_ch_dev_t *dev);
1413
1414 /**
1415 * \brief Gets status of DMA350 DMA channel.
1416 *
1417 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1418 *
1419 * \return Returns status specified in \ref dma350_ch_status_t
1420 *
1421 * \note This function doesn't check if dev is NULL.
1422 */
1423 __STATIC_INLINE
1424 union dma350_ch_status_t dma350_ch_get_status(struct dma350_ch_dev_t *dev);
1425
1426 /**
1427 * \brief Waits for DMA350 DMA channel to be ready, return status when done.
1428 *
1429 * \param[in] dev DMA350 channel device struct \ref dma350_ch_dev_t
1430 *
1431 * \return Returns status specified in \ref dma350_ch_status_t
1432 *
1433 * \note This function doesn't check if dev is NULL or if it has been init.
1434 */
1435 union dma350_ch_status_t dma350_ch_wait_status(struct dma350_ch_dev_t *dev);
1436
1437 /**
1438 * \brief Sets REGCLEAR header bit in the command structure which clears all
1439 * previous settings from the channel registers
1440 *
1441 * \param[in] cmldink_cfg Command structure for DMA350 DMA command linking
1442 * feature \ref dma350_cmdlink_gencfg_t
1443 *
1444 * \return void
1445 */
1446 __STATIC_INLINE
1447 void dma350_cmdlink_set_regclear(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1448
1449 /**
1450 * \brief Enables Interrupt for DMA350 DMA channel in the command structure
1451 *
1452 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1453 * \ref dma350_cmdlink_gencfg_t
1454 * \param[in] intr Interrupt(s) to enable \ref dma350_ch_intr_t
1455 *
1456 * \return void
1457 */
1458 __STATIC_INLINE
1459 void dma350_cmdlink_enable_intr(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1460 enum dma350_ch_intr_t intr);
1461
1462 /**
1463 * \brief Disables Interrupt for DMA350 DMA channel in the command structure
1464 *
1465 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1466 * \ref dma350_cmdlink_gencfg_t
1467 * \param[in] intr Interrupt(s) to disable \ref dma350_ch_intr_t
1468 *
1469 * \return void
1470 */
1471 __STATIC_INLINE
1472 void dma350_cmdlink_disable_intr(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1473 enum dma350_ch_intr_t intr);
1474
1475 /**
1476 * \brief Sets Transfer Enitity Size in the command structure
1477 *
1478 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1479 * \ref dma350_cmdlink_gencfg_t
1480 * \param[in] transize size in bytes \ref dma350_ch_transize_t
1481 *
1482 * \return void
1483 */
1484 __STATIC_INLINE
1485 void dma350_cmdlink_set_transize(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1486 enum dma350_ch_transize_t transize);
1487
1488 /**
1489 * \brief Sets Channel Priority in the command structure
1490 *
1491 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1492 * \ref dma350_cmdlink_gencfg_t
1493 * \param[in] chprio Number of priority
1494 *
1495 * \return void
1496 */
1497 __STATIC_INLINE
1498 void dma350_cmdlink_set_chprio(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1499 uint8_t chprio);
1500
1501 /**
1502 * \brief Sets operation type for X direction in the command structure
1503 *
1504 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1505 * \ref dma350_cmdlink_gencfg_t
1506 * \param[in] xtype type \ref dma350_ch_xtype_t
1507 *
1508 * \return void
1509 */
1510 __STATIC_INLINE
1511 void dma350_cmdlink_set_xtype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1512 enum dma350_ch_xtype_t xtype);
1513
1514 /**
1515 * \brief Sets operation type for Y direction in the command structure
1516 *
1517 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1518 * \ref dma350_cmdlink_gencfg_t
1519 * \param[in] ytype type \ref dma350_ch_ytype_t
1520 *
1521 * \return void
1522 */
1523 __STATIC_INLINE
1524 void dma350_cmdlink_set_ytype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1525 enum dma350_ch_ytype_t ytype);
1526
1527 /**
1528 * \brief Sets Automatic Register reload type in the command structure
1529 *
1530 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1531 * \ref dma350_cmdlink_gencfg_t
1532 * \param[in] regreloadtype Reload type \ref dma350_ch_regreloadtype_t
1533 *
1534 * \return void
1535 */
1536 __STATIC_INLINE
1537 void dma350_cmdlink_set_regreloadtype(
1538 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1539 enum dma350_ch_regreloadtype_t regreloadtype);
1540
1541 /**
1542 * \brief Sets when the STAT_DONE status flag is asserted during the command
1543 * operation in the command structure
1544 *
1545 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1546 * \ref dma350_cmdlink_gencfg_t
1547 * \param[in] donetype Done type selection \ref dma350_ch_donetype_t
1548 *
1549 * \return void
1550 */
1551 __STATIC_INLINE
1552 void dma350_cmdlink_set_donetype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1553 enum dma350_ch_donetype_t donetype);
1554
1555 /**
1556 * \brief Enables the automatic pause request for the current DMA operation
1557 * if the STAT_DONE flag is asserted in the command structure
1558 *
1559 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1560 * \ref dma350_cmdlink_gencfg_t
1561 *
1562 * \return void
1563 */
1564 __STATIC_INLINE
1565 void dma350_cmdlink_enable_donepause(
1566 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1567
1568 /**
1569 * \brief Disables the automatic pause request for the current DMA operation
1570 * if the STAT_DONE flag is asserted in the command structure
1571 *
1572 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1573 * \ref dma350_cmdlink_gencfg_t
1574 *
1575 * \return void
1576 */
1577 __STATIC_INLINE
1578 void dma350_cmdlink_disable_donepause(
1579 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1580
1581 /**
1582 * \brief Enables Source Trigger Input use in the command structure
1583 *
1584 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1585 * \ref dma350_cmdlink_gencfg_t
1586 *
1587 * \return void
1588 */
1589 __STATIC_INLINE
1590 void dma350_cmdlink_enable_srctrigin(
1591 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1592
1593 /**
1594 * \brief Disables Source Trigger Input use in the command structure
1595 *
1596 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1597 * \ref dma350_cmdlink_gencfg_t
1598 *
1599 * \return void
1600 */
1601 __STATIC_INLINE
1602 void dma350_cmdlink_disable_srctrigin(
1603 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1604
1605 /**
1606 * \brief Enables Destination Trigger Input use in the command structure
1607 *
1608 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1609 * \ref dma350_cmdlink_gencfg_t
1610 *
1611 * \return void
1612 */
1613 __STATIC_INLINE
1614 void dma350_cmdlink_enable_destrigin(
1615 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1616
1617 /**
1618 * \brief Disables Destination Trigger Input use in the command structure
1619 *
1620 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1621 * \ref dma350_cmdlink_gencfg_t
1622 *
1623 * \return void
1624 */
1625 __STATIC_INLINE
1626 void dma350_cmdlink_disable_destrigin(
1627 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1628
1629 /**
1630 * \brief Enables Trigger Output use in the command structure
1631 *
1632 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1633 * \ref dma350_cmdlink_gencfg_t
1634 *
1635 * \return void
1636 */
1637 __STATIC_INLINE
1638 void dma350_cmdlink_enable_trigout(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1639
1640 /**
1641 * \brief Disables Trigger Output for use in the command structure
1642 *
1643 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1644 * \ref dma350_cmdlink_gencfg_t
1645 *
1646 * \return void
1647 */
1648 __STATIC_INLINE
1649 void dma350_cmdlink_disable_trigout(
1650 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1651
1652 /**
1653 * \brief Enables GPO use in the command structure
1654 *
1655 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1656 * \ref dma350_cmdlink_gencfg_t
1657 *
1658 * \return void
1659 */
1660 __STATIC_INLINE
1661 void dma350_cmdlink_enable_gpo(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1662
1663 /**
1664 * \brief Disables GPO use in the command structure
1665 *
1666 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1667 * \ref dma350_cmdlink_gencfg_t
1668 *
1669 * \return void
1670 */
1671 __STATIC_INLINE
1672 void dma350_cmdlink_disable_gpo(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1673
1674 /**
1675 * \brief Enables Stream Interface use in the command structure
1676 *
1677 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1678 * \ref dma350_cmdlink_gencfg_t
1679 *
1680 * \return void
1681 */
1682 __STATIC_INLINE
1683 void dma350_cmdlink_enable_stream(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1684
1685 /**
1686 * \brief Disables Stream Interface use in the command structure
1687 *
1688 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1689 * \ref dma350_cmdlink_gencfg_t
1690 *
1691 * \return void
1692 */
1693 __STATIC_INLINE
1694 void dma350_cmdlink_disable_stream(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1695
1696 /**
1697 * \brief Sets Source Address[31:0] in the command structure
1698 *
1699 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1700 * \ref dma350_cmdlink_gencfg_t
1701 * \param[in] src_addr Memory location of the source
1702 *
1703 * \return void
1704 */
1705 __STATIC_INLINE
1706 void dma350_cmdlink_set_srcaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1707 uint32_t src_addr);
1708
1709 /**
1710 * \brief Sets Destination Address[31:0] in the command structure
1711 *
1712 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1713 * \ref dma350_cmdlink_gencfg_t
1714 * \param[in] des_addr Memory location of the destination
1715 *
1716 * \return void
1717 */
1718 __STATIC_INLINE
1719 void dma350_cmdlink_set_desaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1720 uint32_t des_addr);
1721
1722 /**
1723 * \brief Sets the number of data in the command structure units
1724 * copied during the DMA command up to 16 bits in the X dimension
1725 *
1726 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1727 * \ref dma350_cmdlink_gencfg_t
1728 * \param[in] src_xsize Source number of transfers
1729 * \param[in] des_xsize Destination number of transfers
1730 *
1731 * \return void
1732 */
1733 __STATIC_INLINE
1734 void dma350_cmdlink_set_xsize16(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1735 uint16_t src_xsize, uint16_t des_xsize);
1736
1737 /**
1738 * \brief Sets the number of data in the command structure units
1739 * copied during the DMA command up to 32 bits in the X dimension
1740 *
1741 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1742 * \ref dma350_cmdlink_gencfg_t
1743 * \param[in] src_xsize Source number of transfers
1744 * \param[in] des_xsize Destination number of transfers
1745 *
1746 * \return void
1747 */
1748 __STATIC_INLINE
1749 void dma350_cmdlink_set_xsize32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1750 uint32_t src_xsize, uint32_t des_xsize);
1751
1752 /**
1753 * \brief Sets Source Transfer Memory Attribute field[3:0]
1754 * in the command structure
1755 *
1756 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1757 * \ref dma350_cmdlink_gencfg_t
1758 * \param[in] memattrlo Attribute field
1759 *
1760 * \return void
1761 */
1762 __STATIC_INLINE
1763 void dma350_cmdlink_set_srcmemattrlo(
1764 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo);
1765
1766 /**
1767 * \brief Sets Source Transfer Memory Attribute field[7:4]
1768 * in the command structure
1769 *
1770 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1771 * \ref dma350_cmdlink_gencfg_t
1772 * \param[in] memattrhi Attribute field
1773 *
1774 * \return void
1775 */
1776 __STATIC_INLINE
1777 void dma350_cmdlink_set_srcmemattrhi(
1778 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi);
1779
1780 /**
1781 * \brief Sets Source Transfer Shareability Attribute in the command structure
1782 *
1783 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1784 * \ref dma350_cmdlink_gencfg_t
1785 * \param[in] shareattr Attribute field
1786 *
1787 * \return void
1788 */
1789 __STATIC_INLINE
1790 void dma350_cmdlink_set_srcshareattr(
1791 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr);
1792
1793 /**
1794 * \brief Sets Destination Transfer Memory Attribute field[3:0] in the command
1795 * structure
1796 *
1797 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1798 * \ref dma350_cmdlink_gencfg_t
1799 * \param[in] memattrlo Attribute field
1800 *
1801 * \return void
1802 */
1803 __STATIC_INLINE
1804 void dma350_cmdlink_set_desmemattrlo(
1805 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo);
1806
1807 /**
1808 * \brief Sets Destination Transfer Memory Attribute field[7:4] in the command
1809 * structure
1810 *
1811 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1812 * \ref dma350_cmdlink_gencfg_t
1813 * \param[in] memattrhi Attribute field
1814 *
1815 * \return void
1816 */
1817 __STATIC_INLINE
1818 void dma350_cmdlink_set_desmemattrhi(
1819 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi);
1820
1821 /**
1822 * \brief Sets Destination Transfer Shareability Attribute in the command
1823 * structure
1824 *
1825 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1826 * \ref dma350_cmdlink_gencfg_t
1827 * \param[in] shareattr Attribute field
1828 *
1829 * \return void
1830 */
1831 __STATIC_INLINE
1832 void dma350_cmdlink_set_desshareattr(
1833 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr);
1834
1835 /**
1836 * \brief Sets Source Transfer Attribute to secure in the command structure
1837 *
1838 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1839 * \ref dma350_cmdlink_gencfg_t
1840 *
1841 * \return void
1842 */
1843 __STATIC_INLINE
1844 void dma350_cmdlink_set_src_trans_secure(
1845 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1846
1847 /**
1848 * \brief Sets Source Transfer Attribute to non secure in the command structure
1849 *
1850 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1851 * \ref dma350_cmdlink_gencfg_t
1852 *
1853 * \return void
1854 */
1855 __STATIC_INLINE
1856 void dma350_cmdlink_set_src_trans_nonsecure(
1857 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1858
1859 /**
1860 * \brief Sets Destination Transfer Attribute to secure in the command structure
1861 *
1862 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1863 * \ref dma350_cmdlink_gencfg_t
1864 *
1865 * \return void
1866 */
1867 __STATIC_INLINE
1868 void dma350_cmdlink_set_des_trans_secure(
1869 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1870
1871 /**
1872 * \brief Sets Destination Transfer Attribute to non secure
1873 * in the command structure
1874 *
1875 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1876 * \ref dma350_cmdlink_gencfg_t
1877 *
1878 * \return void
1879 */
1880 __STATIC_INLINE
1881 void dma350_cmdlink_set_des_trans_nonsecure(
1882 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1883
1884 /**
1885 * \brief Sets Source Transfer Privilege to privileged
1886 * in the command structure
1887 *
1888 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1889 * \ref dma350_cmdlink_gencfg_t
1890 *
1891 * \return void
1892 */
1893 __STATIC_INLINE
1894 void dma350_cmdlink_set_src_trans_privileged(
1895 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1896
1897 /**
1898 * \brief Sets Source Transfer Privilege to unprivileged
1899 * in the command structure
1900 *
1901 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1902 * \ref dma350_cmdlink_gencfg_t
1903 *
1904 * \return void
1905 */
1906 __STATIC_INLINE
1907 void dma350_cmdlink_set_src_trans_unprivileged(
1908 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1909
1910 /**
1911 * \brief Sets Destination Transfer Privilege to privileged
1912 * in the command structure
1913 *
1914 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1915 * \ref dma350_cmdlink_gencfg_t
1916 *
1917 * \return void
1918 */
1919 __STATIC_INLINE
1920 void dma350_cmdlink_set_des_trans_privileged(
1921 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1922
1923 /**
1924 * \brief Sets Destination Transfer Privilege to unprivileged
1925 * in the command structure
1926 *
1927 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1928 * \ref dma350_cmdlink_gencfg_t
1929 *
1930 * \return void
1931 */
1932 __STATIC_INLINE
1933 void dma350_cmdlink_set_des_trans_unprivileged(
1934 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
1935
1936 /**
1937 * \brief Sets Source Max Burst Lenght in the command structure
1938 *
1939 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1940 * \ref dma350_cmdlink_gencfg_t
1941 * \param[in] length Value of max burst length
1942 *
1943 * \return void
1944 */
1945 __STATIC_INLINE
1946 void dma350_cmdlink_set_srcmaxburstlen(
1947 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t length);
1948
1949 /**
1950 * \brief Sets Destination Max Burst Lenght in the command structure
1951 *
1952 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1953 * \ref dma350_cmdlink_gencfg_t
1954 * \param[in] length Value of max burst length
1955 *
1956 * \return void
1957 */
1958 __STATIC_INLINE
1959 void dma350_cmdlink_set_desmaxburstlen(
1960 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t length);
1961
1962 /**
1963 * \brief Sets the increment value in the command structure that is used to
1964 * update the source and the destination addresses after each
1965 * transfered data unit
1966 *
1967 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1968 * \ref dma350_cmdlink_gencfg_t
1969 * \param[in] src_xaddrinc Source X dimension address increment value
1970 * \param[in] des_xaddrinc Destination X dimension address increment value
1971 *
1972 * \return void
1973 */
1974 __STATIC_INLINE
1975 void dma350_cmdlink_set_xaddrinc(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1976 uint16_t src_xaddrinc, uint16_t des_xaddrinc);
1977
1978 /**
1979 * \brief Sets the increment value in the command structure that is used to
1980 * update the source and the destination line base addresses after
1981 * each line is transferred in the command structure
1982 *
1983 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
1984 * \ref dma350_cmdlink_gencfg_t
1985 * \param[in] src_yaddrstride Source Address Stride value
1986 * \param[in] des_yaddrstride Destination Address Stride value
1987 *
1988 * \return void
1989 */
1990 __STATIC_INLINE
1991 void dma350_cmdlink_set_yaddrstride(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
1992 uint16_t src_yaddrstride,
1993 uint16_t des_yaddrstride);
1994
1995 /**
1996 * \brief Sets the value in the command structure to be used to fill the
1997 * remaining part of the destination memory area
1998 *
1999 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2000 * \ref dma350_cmdlink_gencfg_t
2001 * \param[in] fillval Fill pattern value
2002 *
2003 * \return void
2004 */
2005 __STATIC_INLINE
2006 void dma350_cmdlink_set_fillval(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2007 uint32_t fillval);
2008
2009 /**
2010 * \brief Sets the number of data units copied during the DMA command
2011 * up to 16 bits in the Y dimension in the command structure
2012 *
2013 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2014 * \ref dma350_cmdlink_gencfg_t
2015 * \param[in] src_ysize number of source elements in the y dimension
2016 * \param[in] des_ysize number of destination elements in the y dimension
2017 *
2018 * \return void
2019 */
2020 __STATIC_INLINE
2021 void dma350_cmdlink_set_ysize16(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2022 uint16_t src_ysize, uint16_t des_ysize);
2023
2024 /**
2025 * \brief Sets template size in the command structure
2026 *
2027 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2028 * \ref dma350_cmdlink_gencfg_t
2029 * \param[in] scr_tmpltsize Source Template size in numbers
2030 * \param[in] des_tmpltsize Destination Template size in numbers
2031 *
2032 * \return void
2033 */
2034 __STATIC_INLINE
2035 void dma350_cmdlink_set_tmpltsize(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2036 uint8_t scr_tmpltsize, uint8_t des_tmpltsize);
2037
2038 /**
2039 * \brief Sets the template pattern in the command structure
2040 * used for reading the source memory area
2041 *
2042 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2043 * \ref dma350_cmdlink_gencfg_t
2044 * \param[in] src_tmplt Source Packing Template
2045 *
2046 * \return void
2047 */
2048 __STATIC_INLINE
2049 void dma350_cmdlink_set_srctmplt(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2050 uint32_t src_tmplt);
2051
2052 /**
2053 * \brief Sets the template pattern in the command structure
2054 * used for reading the destination memory area
2055 *
2056 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2057 * \ref dma350_cmdlink_gencfg_t
2058 * \param[in] des_tmplt Destination Packing Template
2059 *
2060 * \return void
2061 */
2062 __STATIC_INLINE
2063 void dma350_cmdlink_set_destmplt(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2064 uint32_t des_tmplt);
2065
2066 /**
2067 * \brief Sets Source Trigger Input Select in the command structure
2068 *
2069 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2070 * \ref dma350_cmdlink_gencfg_t
2071 * \param[in] srctriginsel Input Select value
2072 *
2073 * \return void
2074 */
2075 __STATIC_INLINE
2076 void dma350_cmdlink_set_srctriginsel(
2077 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t srctriginsel);
2078
2079 /**
2080 * \brief Sets Source Trigger Input Type in the command structure
2081 *
2082 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2083 * \ref dma350_cmdlink_gencfg_t
2084 * \param[in] type Input type \ref dma350_ch_srctrigintype_t
2085 *
2086 * \return void
2087 */
2088 __STATIC_INLINE
2089 void dma350_cmdlink_set_srctrigintype(
2090 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2091 enum dma350_ch_srctrigintype_t type);
2092
2093 /**
2094 * \brief Sets Source Trigger Input Mode in the command structure
2095 *
2096 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2097 * \ref dma350_cmdlink_gencfg_t
2098 * \param[in] mode Mode \ref dma350_ch_srctriginmode_t
2099 *
2100 * \return void
2101 */
2102 __STATIC_INLINE
2103 void dma350_cmdlink_set_srctriginmode(
2104 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2105 enum dma350_ch_srctriginmode_t mode);
2106
2107 /**
2108 * \brief Sets Source Trigger Input Default Transfer Size
2109 * in the command structure
2110 *
2111 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2112 * \ref dma350_cmdlink_gencfg_t
2113 * \param[in] blksize Size value
2114 *
2115 * \return void
2116 */
2117 __STATIC_INLINE
2118 void dma350_cmdlink_set_srctriginblksize(
2119 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t blksize);
2120
2121 /**
2122 * \brief Sets Destination Trigger Input Select in the command structure
2123 *
2124 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2125 * \ref dma350_cmdlink_gencfg_t
2126 * \param[in] destriginsel Input Select value
2127 *
2128 * \return void
2129 */
2130 __STATIC_INLINE
2131 void dma350_cmdlink_set_destriginsel(
2132 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t destriginsel);
2133
2134 /**
2135 * \brief Sets Destination Trigger Input Type in the command structure
2136 *
2137 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2138 * \ref dma350_cmdlink_gencfg_t
2139 * \param[in] type Input type \ref dma350_ch_destrigintype_t
2140 *
2141 * \return void
2142 */
2143 __STATIC_INLINE
2144 void dma350_cmdlink_set_destrigintype(
2145 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2146 enum dma350_ch_destrigintype_t type);
2147
2148 /**
2149 * \brief Sets Destination Trigger Input Mode in the command structure
2150 *
2151 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2152 * \ref dma350_cmdlink_gencfg_t
2153 * \param[in] mode Mode \ref dma350_ch_destriginmode_t
2154 *
2155 * \return void
2156 */
2157 __STATIC_INLINE
2158 void dma350_cmdlink_set_destriginmode(
2159 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2160 enum dma350_ch_destriginmode_t mode);
2161
2162 /**
2163 * \brief Sets Destination Trigger Input Default Transfer Size
2164 * in the command structure
2165 *
2166 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2167 * \ref dma350_cmdlink_gencfg_t
2168 * \param[in] blksize Size value
2169 *
2170 * \return void
2171 */
2172 __STATIC_INLINE
2173 void dma350_cmdlink_set_destriginblksize(
2174 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t blksize);
2175
2176 /**
2177 * \brief Sets Trigger Output Select in the command structure
2178 *
2179 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2180 * \ref dma350_cmdlink_gencfg_t
2181 * \param[in] trigoutsel Select value
2182 *
2183 * \return void
2184 */
2185 __STATIC_INLINE
2186 void dma350_cmdlink_set_trigoutsel(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2187 uint8_t trigoutsel);
2188
2189 /**
2190 * \brief Sets Trigger Output Type in the command structure
2191 *
2192 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2193 * \ref dma350_cmdlink_gencfg_t
2194 * \param[in] type Output type \ref dma350_ch_trigouttype_t
2195 *
2196 * \return void
2197 */
2198 __STATIC_INLINE
2199 void dma350_cmdlink_set_trigouttype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2200 enum dma350_ch_trigouttype_t type);
2201
2202 /**
2203 * \brief Sets which GPO ports 0-31 in the command structure are enabled
2204 * to change at the beginning of current DMA command
2205 *
2206 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2207 * \ref dma350_cmdlink_gencfg_t
2208 * \param[in] gpoen0 Enable mask value
2209 *
2210 * \return void
2211 */
2212 __STATIC_INLINE
2213 void dma350_cmdlink_set_gpoen0(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2214 uint32_t gpoen0);
2215
2216 /**
2217 * \brief Sets the value to be driven on the GPO ports 0-31 thar are enabled
2218 * in the command structure
2219 *
2220 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2221 * \ref dma350_cmdlink_gencfg_t
2222 * \param[in] gpoval0 General Purpose Output Value GPO[31:0]
2223 *
2224 * \return void
2225 */
2226 __STATIC_INLINE
2227 void dma350_cmdlink_set_gpoval0(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2228 uint32_t gpoval0);
2229
2230 /**
2231 * \brief Sets Stream Interface operation Type in the command structure
2232 *
2233 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2234 * \ref dma350_cmdlink_gencfg_t
2235 * \param[in] type Type \ref dma350_ch_streamtype_t
2236 *
2237 * \return void
2238 */
2239 __STATIC_INLINE
2240 void dma350_cmdlink_set_streamtype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2241 enum dma350_ch_streamtype_t type);
2242
2243 /**
2244 * \brief Sets Link Address Read Transfer Memory Attribute[3:0] field
2245 * in the command structure
2246 *
2247 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2248 * \ref dma350_cmdlink_gencfg_t
2249 * \param[in] memattrlo Attribute field
2250 *
2251 * \return void
2252 */
2253 __STATIC_INLINE
2254 void dma350_cmdlink_set_linkmemattrlo(
2255 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo);
2256
2257 /**
2258 * \brief Sets Link Address Read Transfer Memory Attribute[7:4] field
2259 * in the command structure
2260 *
2261 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2262 * \ref dma350_cmdlink_gencfg_t
2263 * \param[in] memattrlo Attribute field
2264 *
2265 * \return void
2266 */
2267 __STATIC_INLINE
2268 void dma350_cmdlink_set_linkmemattrhi(
2269 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi);
2270
2271 /**
2272 * \brief Sets Link Address Transfer Shareability Attribute
2273 * in the command structure
2274 *
2275 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2276 * \ref dma350_cmdlink_gencfg_t
2277 * \param[in] shareattr Attribute field
2278 *
2279 * \return void
2280 */
2281 __STATIC_INLINE
2282 void dma350_cmdlink_set_linkshareattr(
2283 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr);
2284
2285 /**
2286 * \brief Sets Automatic Command Restart Counter in the command structure
2287 *
2288 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2289 * \ref dma350_cmdlink_gencfg_t
2290 * \param[in] cnt Counter value
2291 *
2292 * \return void
2293 */
2294 __STATIC_INLINE
2295 void dma350_cmdlink_set_cmdrestartcnt(
2296 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint16_t cnt);
2297
2298 /**
2299 * \brief Enables Infinite Automatic Command Restart in the command structure
2300 *
2301 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2302 * \ref dma350_cmdlink_gencfg_t
2303 *
2304 * \return void
2305 */
2306 __STATIC_INLINE
2307 void dma350_cmdlink_enable_cmdrestartinfen(
2308 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
2309
2310 /**
2311 * \brief Disables Infinite Automatic Command Restart in the command structure
2312 *
2313 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2314 * \ref dma350_cmdlink_gencfg_t
2315 *
2316 * \return void
2317 */
2318 __STATIC_INLINE
2319 void dma350_cmdlink_disable_cmdrestartinfen(
2320 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
2321
2322 /**
2323 * \brief Enables Link Address in the command structure
2324 *
2325 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2326 * \ref dma350_cmdlink_gencfg_t
2327 *
2328 * \return void
2329 */
2330 __STATIC_INLINE
2331 void dma350_cmdlink_enable_linkaddr(
2332 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
2333
2334 /**
2335 * \brief Disables Link Address in the command structure
2336 *
2337 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2338 * \ref dma350_cmdlink_gencfg_t
2339 *
2340 * \return void
2341 */
2342 __STATIC_INLINE
2343 void dma350_cmdlink_disable_linkaddr(
2344 struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
2345
2346 /**
2347 * \brief Sets Link Address Pointer [31:2] in the command structure
2348 *
2349 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2350 * \ref dma350_cmdlink_gencfg_t
2351 * \param[in] linkaddr Memory location of the destination
2352 *
2353 * \return void
2354 */
2355 __STATIC_INLINE
2356 void dma350_cmdlink_set_linkaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2357 uint32_t linkaddr);
2358
2359 /**
2360 * \brief Get command from a command structure
2361 * that can be fetched by the channel
2362 *
2363 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2364 * \ref dma350_cmdlink_gencfg_t
2365 * \param[inout] buffer Pointer to the buffer to place the generated cmd to
2366 * \param[in] buffer_end Pointer to the next memory address after cmd buffer
2367 *
2368 * \return next memory address in buffer after generated cmd, or NUll on error
2369 */
2370 uint32_t *dma350_cmdlink_generate(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2371 uint32_t *buffer, uint32_t *buffer_end);
2372
2373 /**
2374 * \brief Initialize command structure for dma command linking feature
2375 *
2376 * \param[in] cmldink_cfg DMA350 command structure for command linking feature
2377 * \ref dma350_cmdlink_gencfg_t
2378 *
2379 * \return void
2380 */
2381 void dma350_cmdlink_init(struct dma350_cmdlink_gencfg_t *cmdlink_cfg);
2382
2383 __STATIC_INLINE
dma350_ch_is_init(const struct dma350_ch_dev_t * dev)2384 bool dma350_ch_is_init(const struct dma350_ch_dev_t *dev)
2385 {
2386 return dev->data.state == DMA350_CH_INITIALIZED;
2387 }
2388
2389 __STATIC_INLINE
dma350_ch_set_src(struct dma350_ch_dev_t * dev,uint32_t src_addr)2390 void dma350_ch_set_src(struct dma350_ch_dev_t *dev, uint32_t src_addr)
2391 {
2392 dev->cfg.ch_base->CH_SRCADDR = src_addr;
2393 }
2394
2395 __STATIC_INLINE
dma350_ch_set_des(struct dma350_ch_dev_t * dev,uint32_t des_addr)2396 void dma350_ch_set_des(struct dma350_ch_dev_t *dev, uint32_t des_addr)
2397 {
2398 dev->cfg.ch_base->CH_DESADDR = des_addr;
2399 }
2400
2401 __STATIC_INLINE
dma350_ch_set_xsize16(struct dma350_ch_dev_t * dev,uint16_t src_xsize,uint16_t des_xsize)2402 void dma350_ch_set_xsize16(struct dma350_ch_dev_t *dev, uint16_t src_xsize,
2403 uint16_t des_xsize)
2404 {
2405 dev->cfg.ch_base->CH_XSIZE =
2406 ((des_xsize & 0x0000FFFFUL) << 16U) | (src_xsize & 0x0000FFFFUL);
2407 dev->cfg.ch_base->CH_XSIZEHI = 0;
2408 }
2409
2410 __STATIC_INLINE
dma350_ch_set_xsize32(struct dma350_ch_dev_t * dev,uint32_t src_xsize,uint32_t des_xsize)2411 void dma350_ch_set_xsize32(struct dma350_ch_dev_t *dev, uint32_t src_xsize,
2412 uint32_t des_xsize)
2413 {
2414 dev->cfg.ch_base->CH_XSIZE =
2415 ((des_xsize & 0x0000FFFFUL) << 16U) | (src_xsize & 0x0000FFFFUL);
2416 dev->cfg.ch_base->CH_XSIZEHI =
2417 (des_xsize & 0xFFFF0000UL) | ((src_xsize & 0xFFFF0000UL) >> 16U);
2418 }
2419
2420 __STATIC_INLINE
dma350_ch_set_ysize16(struct dma350_ch_dev_t * dev,uint16_t src_ysize,uint16_t des_ysize)2421 void dma350_ch_set_ysize16(struct dma350_ch_dev_t *dev, uint16_t src_ysize,
2422 uint16_t des_ysize)
2423 {
2424 dev->cfg.ch_base->CH_YSIZE =
2425 ((des_ysize & 0x0000FFFFUL) << 16U) | (src_ysize & 0x0000FFFFUL);
2426 }
2427
2428 __STATIC_INLINE
dma350_ch_set_yaddrstride(struct dma350_ch_dev_t * dev,uint16_t src_yaddrstride,uint16_t des_yaddrstride)2429 void dma350_ch_set_yaddrstride(struct dma350_ch_dev_t *dev,
2430 uint16_t src_yaddrstride,
2431 uint16_t des_yaddrstride)
2432 {
2433 dev->cfg.ch_base->CH_YADDRSTRIDE =
2434 ((des_yaddrstride & 0x0000FFFFUL) << 16U) |
2435 (src_yaddrstride & 0x0000FFFFUL);
2436 }
2437
2438 __STATIC_INLINE
dma350_ch_set_transize(struct dma350_ch_dev_t * dev,enum dma350_ch_transize_t transize)2439 void dma350_ch_set_transize(struct dma350_ch_dev_t *dev,
2440 enum dma350_ch_transize_t transize)
2441 {
2442 dev->cfg.ch_base->CH_CTRL =
2443 (dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_TRANSIZE_Msk)) |
2444 (transize & DMA_CH_CTRL_TRANSIZE_Msk);
2445 }
2446
2447 __STATIC_INLINE
dma350_ch_set_chprio(struct dma350_ch_dev_t * dev,uint8_t chprio)2448 void dma350_ch_set_chprio(struct dma350_ch_dev_t *dev, uint8_t chprio)
2449 {
2450 SET_FIELD(dev->cfg.ch_base->CH_CTRL, chprio, DMA_CH_CTRL_CHPRIO_Pos,
2451 DMA_CH_CTRL_CHPRIO_Msk);
2452 }
2453
2454 __STATIC_INLINE
dma350_ch_set_xtype(struct dma350_ch_dev_t * dev,enum dma350_ch_xtype_t xtype)2455 void dma350_ch_set_xtype(struct dma350_ch_dev_t *dev,
2456 enum dma350_ch_xtype_t xtype)
2457 {
2458 dev->cfg.ch_base->CH_CTRL =
2459 (dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_XTYPE_Msk)) |
2460 (xtype & DMA_CH_CTRL_XTYPE_Msk);
2461 }
2462
2463 __STATIC_INLINE
dma350_ch_set_ytype(struct dma350_ch_dev_t * dev,enum dma350_ch_ytype_t ytype)2464 void dma350_ch_set_ytype(struct dma350_ch_dev_t *dev,
2465 enum dma350_ch_ytype_t ytype)
2466 {
2467 dev->cfg.ch_base->CH_CTRL =
2468 (dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_YTYPE_Msk)) |
2469 (ytype & DMA_CH_CTRL_YTYPE_Msk);
2470 }
2471
2472 __STATIC_INLINE
dma350_ch_set_regreloadtype(struct dma350_ch_dev_t * dev,enum dma350_ch_regreloadtype_t regreloadtype)2473 void dma350_ch_set_regreloadtype(struct dma350_ch_dev_t *dev,
2474 enum dma350_ch_regreloadtype_t regreloadtype)
2475 {
2476 dev->cfg.ch_base->CH_CTRL =
2477 (dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_REGRELOADTYPE_Msk)) |
2478 (regreloadtype & DMA_CH_CTRL_REGRELOADTYPE_Msk);
2479 }
2480
2481 __STATIC_INLINE
dma350_ch_set_donetype(struct dma350_ch_dev_t * dev,enum dma350_ch_donetype_t donetype)2482 void dma350_ch_set_donetype(struct dma350_ch_dev_t *dev,
2483 enum dma350_ch_donetype_t donetype)
2484 {
2485 dev->cfg.ch_base->CH_CTRL =
2486 (dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_DONETYPE_Msk)) |
2487 (donetype & DMA_CH_CTRL_DONETYPE_Msk);
2488 }
2489
2490 __STATIC_INLINE
dma350_ch_enable_donepause(struct dma350_ch_dev_t * dev)2491 void dma350_ch_enable_donepause(struct dma350_ch_dev_t *dev)
2492 {
2493 dev->cfg.ch_base->CH_CTRL =
2494 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_DONEPAUSEEN_Msk;
2495 }
2496
2497 __STATIC_INLINE
dma350_ch_disable_donepause(struct dma350_ch_dev_t * dev)2498 void dma350_ch_disable_donepause(struct dma350_ch_dev_t *dev)
2499 {
2500 dev->cfg.ch_base->CH_CTRL =
2501 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_DONEPAUSEEN_Msk);
2502 }
2503
2504 __STATIC_INLINE
dma350_ch_enable_srctrigin(struct dma350_ch_dev_t * dev)2505 void dma350_ch_enable_srctrigin(struct dma350_ch_dev_t *dev)
2506 {
2507 dev->cfg.ch_base->CH_CTRL =
2508 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_USESRCTRIGIN_Msk;
2509 }
2510
2511 __STATIC_INLINE
dma350_ch_disable_srctrigin(struct dma350_ch_dev_t * dev)2512 void dma350_ch_disable_srctrigin(struct dma350_ch_dev_t *dev)
2513 {
2514 dev->cfg.ch_base->CH_CTRL =
2515 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_USESRCTRIGIN_Msk);
2516 }
2517
2518 __STATIC_INLINE
dma350_ch_enable_destrigin(struct dma350_ch_dev_t * dev)2519 void dma350_ch_enable_destrigin(struct dma350_ch_dev_t *dev)
2520 {
2521 dev->cfg.ch_base->CH_CTRL =
2522 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_USEDESTRIGIN_Msk;
2523 }
2524
2525 __STATIC_INLINE
dma350_ch_disable_destrigin(struct dma350_ch_dev_t * dev)2526 void dma350_ch_disable_destrigin(struct dma350_ch_dev_t *dev)
2527 {
2528 dev->cfg.ch_base->CH_CTRL =
2529 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_USEDESTRIGIN_Msk);
2530 }
2531
2532 __STATIC_INLINE
dma350_ch_enable_trigout(struct dma350_ch_dev_t * dev)2533 void dma350_ch_enable_trigout(struct dma350_ch_dev_t *dev)
2534 {
2535 dev->cfg.ch_base->CH_CTRL =
2536 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_USETRIGOUT_Msk;
2537 }
2538
2539 __STATIC_INLINE
dma350_ch_disable_trigout(struct dma350_ch_dev_t * dev)2540 void dma350_ch_disable_trigout(struct dma350_ch_dev_t *dev)
2541 {
2542 dev->cfg.ch_base->CH_CTRL =
2543 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_USETRIGOUT_Msk);
2544 }
2545
2546 __STATIC_INLINE
dma350_ch_enable_gpo(struct dma350_ch_dev_t * dev)2547 void dma350_ch_enable_gpo(struct dma350_ch_dev_t *dev)
2548 {
2549 dev->cfg.ch_base->CH_CTRL =
2550 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_USEGPO_Msk;
2551 }
2552
2553 __STATIC_INLINE
dma350_ch_disable_gpo(struct dma350_ch_dev_t * dev)2554 void dma350_ch_disable_gpo(struct dma350_ch_dev_t *dev)
2555 {
2556 dev->cfg.ch_base->CH_CTRL =
2557 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_USEGPO_Msk);
2558 }
2559
2560 __STATIC_INLINE
dma350_ch_enable_stream(struct dma350_ch_dev_t * dev)2561 void dma350_ch_enable_stream(struct dma350_ch_dev_t *dev)
2562 {
2563 dev->cfg.ch_base->CH_CTRL =
2564 dev->cfg.ch_base->CH_CTRL | DMA_CH_CTRL_USESTREAM_Msk;
2565 }
2566
2567 __STATIC_INLINE
dma350_ch_disable_stream(struct dma350_ch_dev_t * dev)2568 void dma350_ch_disable_stream(struct dma350_ch_dev_t *dev)
2569 {
2570 dev->cfg.ch_base->CH_CTRL =
2571 dev->cfg.ch_base->CH_CTRL & (~DMA_CH_CTRL_USESTREAM_Msk);
2572 }
2573
2574 __STATIC_INLINE
dma350_ch_set_srcmemattr(struct dma350_ch_dev_t * dev,uint8_t memattr,uint8_t shareattr)2575 void dma350_ch_set_srcmemattr(struct dma350_ch_dev_t *dev, uint8_t memattr,
2576 uint8_t shareattr)
2577 {
2578 dev->cfg.ch_base->CH_SRCTRANSCFG =
2579 /* Only set Lo, Hi, and Share attributes */
2580 (dev->cfg.ch_base->CH_SRCTRANSCFG &
2581 ((~DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk) |
2582 (~DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk) |
2583 (~DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk))
2584 /* memattr already has Lo and Hi values in correct order */
2585 ) |
2586 ((memattr & 0x000000FFUL) << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos)
2587 /* Add shareability attribute */
2588 | ((shareattr & 0x00000003UL) << DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos);
2589 }
2590
2591 __STATIC_INLINE
dma350_ch_set_srcmemattrlo(struct dma350_ch_dev_t * dev,uint8_t memattrlo)2592 void dma350_ch_set_srcmemattrlo(struct dma350_ch_dev_t *dev, uint8_t memattrlo)
2593 {
2594 SET_FIELD(dev->cfg.ch_base->CH_SRCTRANSCFG, memattrlo,
2595 DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos,
2596 DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk);
2597 }
2598
2599 __STATIC_INLINE
dma350_ch_set_srcmemattrhi(struct dma350_ch_dev_t * dev,uint8_t memattrhi)2600 void dma350_ch_set_srcmemattrhi(struct dma350_ch_dev_t *dev, uint8_t memattrhi)
2601 {
2602 SET_FIELD(dev->cfg.ch_base->CH_SRCTRANSCFG, memattrhi,
2603 DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos,
2604 DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk);
2605 }
2606
2607 __STATIC_INLINE
dma350_ch_set_srcshareattr(struct dma350_ch_dev_t * dev,uint8_t shareattr)2608 void dma350_ch_set_srcshareattr(struct dma350_ch_dev_t *dev, uint8_t shareattr)
2609 {
2610 SET_FIELD(dev->cfg.ch_base->CH_SRCTRANSCFG, shareattr,
2611 DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos,
2612 DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk);
2613 }
2614
2615 __STATIC_INLINE
dma350_ch_set_desmemattr(struct dma350_ch_dev_t * dev,uint8_t memattr,uint8_t shareattr)2616 void dma350_ch_set_desmemattr(struct dma350_ch_dev_t *dev, uint8_t memattr,
2617 uint8_t shareattr)
2618 {
2619 dev->cfg.ch_base->CH_DESTRANSCFG =
2620 /* Only set Lo, Hi, and Share attributes */
2621 (dev->cfg.ch_base->CH_DESTRANSCFG &
2622 ((~DMA_CH_DESTRANSCFG_DESMEMATTRLO_Msk) |
2623 (~DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk) |
2624 (~DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk))
2625 /* memattr already has Lo and Hi values in correct order */
2626 ) |
2627 ((memattr & 0x000000FFUL) << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos)
2628 /* Add shareability attribute */
2629 | ((shareattr & 0x00000003UL) << DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos);
2630 }
2631
2632 __STATIC_INLINE
dma350_ch_set_desmemattrlo(struct dma350_ch_dev_t * dev,uint8_t memattrlo)2633 void dma350_ch_set_desmemattrlo(struct dma350_ch_dev_t *dev, uint8_t memattrlo)
2634 {
2635 SET_FIELD(dev->cfg.ch_base->CH_DESTRANSCFG, memattrlo,
2636 DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos,
2637 DMA_CH_DESTRANSCFG_DESMEMATTRLO_Msk);
2638 }
2639
2640 __STATIC_INLINE
dma350_ch_set_desmemattrhi(struct dma350_ch_dev_t * dev,uint8_t memattrhi)2641 void dma350_ch_set_desmemattrhi(struct dma350_ch_dev_t *dev, uint8_t memattrhi)
2642 {
2643 SET_FIELD(dev->cfg.ch_base->CH_DESTRANSCFG, memattrhi,
2644 DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos,
2645 DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk);
2646 }
2647
2648 __STATIC_INLINE
dma350_ch_set_desshareattr(struct dma350_ch_dev_t * dev,uint8_t shareattr)2649 void dma350_ch_set_desshareattr(struct dma350_ch_dev_t *dev, uint8_t shareattr)
2650 {
2651 SET_FIELD(dev->cfg.ch_base->CH_DESTRANSCFG, shareattr,
2652 DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos,
2653 DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk);
2654 }
2655
2656 __STATIC_INLINE
dma350_ch_set_src_trans_secure(struct dma350_ch_dev_t * dev)2657 void dma350_ch_set_src_trans_secure(struct dma350_ch_dev_t *dev)
2658 {
2659 dev->cfg.ch_base->CH_SRCTRANSCFG = dev->cfg.ch_base->CH_SRCTRANSCFG &
2660 (~DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk);
2661 }
2662
2663 __STATIC_INLINE
dma350_ch_set_src_trans_nonsecure(struct dma350_ch_dev_t * dev)2664 void dma350_ch_set_src_trans_nonsecure(struct dma350_ch_dev_t *dev)
2665 {
2666 dev->cfg.ch_base->CH_SRCTRANSCFG =
2667 dev->cfg.ch_base->CH_SRCTRANSCFG | DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk;
2668 }
2669
2670 __STATIC_INLINE
dma350_ch_set_des_trans_secure(struct dma350_ch_dev_t * dev)2671 void dma350_ch_set_des_trans_secure(struct dma350_ch_dev_t *dev)
2672 {
2673 dev->cfg.ch_base->CH_DESTRANSCFG = dev->cfg.ch_base->CH_DESTRANSCFG &
2674 (~DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk);
2675 }
2676
2677 __STATIC_INLINE
dma350_ch_set_des_trans_nonsecure(struct dma350_ch_dev_t * dev)2678 void dma350_ch_set_des_trans_nonsecure(struct dma350_ch_dev_t *dev)
2679 {
2680 dev->cfg.ch_base->CH_DESTRANSCFG =
2681 dev->cfg.ch_base->CH_DESTRANSCFG | DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk;
2682 }
2683
2684 __STATIC_INLINE
dma350_ch_set_src_trans_privileged(struct dma350_ch_dev_t * dev)2685 void dma350_ch_set_src_trans_privileged(struct dma350_ch_dev_t *dev)
2686 {
2687 dev->cfg.ch_base->CH_SRCTRANSCFG =
2688 dev->cfg.ch_base->CH_SRCTRANSCFG | DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk;
2689 }
2690
2691 __STATIC_INLINE
dma350_ch_set_src_trans_unprivileged(struct dma350_ch_dev_t * dev)2692 void dma350_ch_set_src_trans_unprivileged(struct dma350_ch_dev_t *dev)
2693 {
2694 dev->cfg.ch_base->CH_SRCTRANSCFG = dev->cfg.ch_base->CH_SRCTRANSCFG &
2695 (~DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk);
2696 }
2697
2698 __STATIC_INLINE
dma350_ch_set_des_trans_privileged(struct dma350_ch_dev_t * dev)2699 void dma350_ch_set_des_trans_privileged(struct dma350_ch_dev_t *dev)
2700 {
2701 dev->cfg.ch_base->CH_DESTRANSCFG =
2702 dev->cfg.ch_base->CH_DESTRANSCFG | DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk;
2703 }
2704
2705 __STATIC_INLINE
dma350_ch_set_des_trans_unprivileged(struct dma350_ch_dev_t * dev)2706 void dma350_ch_set_des_trans_unprivileged(struct dma350_ch_dev_t *dev)
2707 {
2708 dev->cfg.ch_base->CH_DESTRANSCFG = dev->cfg.ch_base->CH_DESTRANSCFG &
2709 (~DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk);
2710 }
2711
2712 __STATIC_INLINE
dma350_ch_set_srcmaxburstlen(struct dma350_ch_dev_t * dev,uint8_t length)2713 void dma350_ch_set_srcmaxburstlen(struct dma350_ch_dev_t *dev, uint8_t length)
2714 {
2715 SET_FIELD(dev->cfg.ch_base->CH_SRCTRANSCFG, length,
2716 DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos,
2717 DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Msk);
2718 }
2719
2720 __STATIC_INLINE
dma350_ch_set_desmaxburstlen(struct dma350_ch_dev_t * dev,uint8_t length)2721 void dma350_ch_set_desmaxburstlen(struct dma350_ch_dev_t *dev, uint8_t length)
2722 {
2723 SET_FIELD(dev->cfg.ch_base->CH_DESTRANSCFG, length,
2724 DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos,
2725 DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Msk);
2726 }
2727
2728 __STATIC_INLINE
dma350_ch_set_src_xaddr_inc(struct dma350_ch_dev_t * dev,int16_t src_xaddr_inc)2729 void dma350_ch_set_src_xaddr_inc(struct dma350_ch_dev_t *dev,
2730 int16_t src_xaddr_inc)
2731 {
2732 dev->cfg.ch_base->CH_XADDRINC =
2733 (dev->cfg.ch_base->CH_XADDRINC & (~DMA_CH_XADDRINC_SRCXADDRINC_Msk)) |
2734 ((uint32_t)src_xaddr_inc & 0x0000FFFFUL);
2735 }
2736
2737 __STATIC_INLINE
dma350_ch_set_des_xaddr_inc(struct dma350_ch_dev_t * dev,int16_t des_xaddr_inc)2738 void dma350_ch_set_des_xaddr_inc(struct dma350_ch_dev_t *dev,
2739 int16_t des_xaddr_inc)
2740 {
2741 dev->cfg.ch_base->CH_XADDRINC =
2742 (dev->cfg.ch_base->CH_XADDRINC & (~DMA_CH_XADDRINC_DESXADDRINC_Msk)) |
2743 (((uint32_t)des_xaddr_inc & 0x0000FFFFUL) << DMA_CH_XADDRINC_DESXADDRINC_Pos);
2744 }
2745
2746 __STATIC_INLINE
dma350_ch_set_xaddr_inc(struct dma350_ch_dev_t * dev,int16_t src_xaddr_inc,int16_t des_xaddr_inc)2747 void dma350_ch_set_xaddr_inc(struct dma350_ch_dev_t *dev, int16_t src_xaddr_inc,
2748 int16_t des_xaddr_inc)
2749 {
2750 dev->cfg.ch_base->CH_XADDRINC =
2751 (((uint32_t)des_xaddr_inc & 0x0000FFFFUL) << DMA_CH_XADDRINC_DESXADDRINC_Pos) |
2752 ((uint32_t)src_xaddr_inc & 0x0000FFFFUL);
2753 }
2754
2755 __STATIC_INLINE
dma350_ch_set_fill_value(struct dma350_ch_dev_t * dev,uint32_t fill_value)2756 void dma350_ch_set_fill_value(struct dma350_ch_dev_t *dev, uint32_t fill_value)
2757 {
2758 dev->cfg.ch_base->CH_FILLVAL = fill_value;
2759 }
2760
2761 __STATIC_INLINE
dma350_ch_set_srctriginsel(struct dma350_ch_dev_t * dev,uint8_t srctriginsel)2762 void dma350_ch_set_srctriginsel(struct dma350_ch_dev_t *dev,
2763 uint8_t srctriginsel)
2764 {
2765 SET_FIELD(dev->cfg.ch_base->CH_SRCTRIGINCFG, srctriginsel,
2766 DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos,
2767 DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Msk);
2768 }
2769
2770 __STATIC_INLINE
dma350_ch_set_srctrigintype(struct dma350_ch_dev_t * dev,enum dma350_ch_srctrigintype_t type)2771 void dma350_ch_set_srctrigintype(struct dma350_ch_dev_t *dev,
2772 enum dma350_ch_srctrigintype_t type)
2773 {
2774 dev->cfg.ch_base->CH_SRCTRIGINCFG =
2775 (dev->cfg.ch_base->CH_SRCTRIGINCFG &
2776 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk)) |
2777 (type & DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk);
2778 }
2779
2780 __STATIC_INLINE
dma350_ch_set_srctriginmode(struct dma350_ch_dev_t * dev,enum dma350_ch_srctriginmode_t mode)2781 void dma350_ch_set_srctriginmode(struct dma350_ch_dev_t *dev,
2782 enum dma350_ch_srctriginmode_t mode)
2783 {
2784 dev->cfg.ch_base->CH_SRCTRIGINCFG =
2785 (dev->cfg.ch_base->CH_SRCTRIGINCFG &
2786 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk)) |
2787 (mode & DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk);
2788 }
2789
2790 __STATIC_INLINE
dma350_ch_set_srctriginblksize(struct dma350_ch_dev_t * dev,uint8_t blksize)2791 void dma350_ch_set_srctriginblksize(struct dma350_ch_dev_t *dev,
2792 uint8_t blksize)
2793 {
2794 SET_FIELD(dev->cfg.ch_base->CH_SRCTRIGINCFG, blksize,
2795 DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos,
2796 DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Msk);
2797 }
2798
2799 __STATIC_INLINE
dma350_ch_set_destriginsel(struct dma350_ch_dev_t * dev,uint8_t destriginsel)2800 void dma350_ch_set_destriginsel(struct dma350_ch_dev_t *dev,
2801 uint8_t destriginsel)
2802 {
2803 SET_FIELD(dev->cfg.ch_base->CH_DESTRIGINCFG, destriginsel,
2804 DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos,
2805 DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Msk);
2806 }
2807
2808 __STATIC_INLINE
dma350_ch_set_destrigintype(struct dma350_ch_dev_t * dev,enum dma350_ch_destrigintype_t type)2809 void dma350_ch_set_destrigintype(struct dma350_ch_dev_t *dev,
2810 enum dma350_ch_destrigintype_t type)
2811 {
2812 dev->cfg.ch_base->CH_DESTRIGINCFG =
2813 (dev->cfg.ch_base->CH_DESTRIGINCFG &
2814 (~DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk)) |
2815 (type & DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk);
2816 }
2817
2818 __STATIC_INLINE
dma350_ch_set_destriginmode(struct dma350_ch_dev_t * dev,enum dma350_ch_destriginmode_t mode)2819 void dma350_ch_set_destriginmode(struct dma350_ch_dev_t *dev,
2820 enum dma350_ch_destriginmode_t mode)
2821 {
2822 dev->cfg.ch_base->CH_DESTRIGINCFG =
2823 (dev->cfg.ch_base->CH_DESTRIGINCFG &
2824 (~DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk)) |
2825 (mode & DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk);
2826 }
2827
2828 __STATIC_INLINE
dma350_ch_set_destriginblksize(struct dma350_ch_dev_t * dev,uint8_t blksize)2829 void dma350_ch_set_destriginblksize(struct dma350_ch_dev_t *dev,
2830 uint8_t blksize)
2831 {
2832 SET_FIELD(dev->cfg.ch_base->CH_DESTRIGINCFG, blksize,
2833 DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos,
2834 DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Msk);
2835 }
2836
2837 __STATIC_INLINE
dma350_ch_set_trigoutsel(struct dma350_ch_dev_t * dev,uint8_t trigoutsel)2838 void dma350_ch_set_trigoutsel(struct dma350_ch_dev_t *dev, uint8_t trigoutsel)
2839 {
2840 SET_FIELD(dev->cfg.ch_base->CH_TRIGOUTCFG, trigoutsel,
2841 DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos,
2842 DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Msk);
2843 }
2844
2845 __STATIC_INLINE
dma350_ch_set_trigouttype(struct dma350_ch_dev_t * dev,enum dma350_ch_trigouttype_t type)2846 void dma350_ch_set_trigouttype(struct dma350_ch_dev_t *dev,
2847 enum dma350_ch_trigouttype_t type)
2848 {
2849 dev->cfg.ch_base->CH_TRIGOUTCFG =
2850 (dev->cfg.ch_base->CH_TRIGOUTCFG &
2851 (~DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk)) |
2852 (type & DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk);
2853 }
2854
2855 __STATIC_INLINE
dma350_ch_set_gpoen0(struct dma350_ch_dev_t * dev,uint32_t gpoen0)2856 void dma350_ch_set_gpoen0(struct dma350_ch_dev_t *dev, uint32_t gpoen0)
2857 {
2858 dev->cfg.ch_base->CH_GPOEN0 = gpoen0;
2859 }
2860
2861 __STATIC_INLINE
dma350_ch_set_gpoval0(struct dma350_ch_dev_t * dev,uint32_t gpoval0)2862 void dma350_ch_set_gpoval0(struct dma350_ch_dev_t *dev, uint32_t gpoval0)
2863 {
2864 dev->cfg.ch_base->CH_GPOVAL0 = gpoval0;
2865 }
2866
2867 __STATIC_INLINE
dma350_ch_get_gpoval0(struct dma350_ch_dev_t * dev)2868 uint32_t dma350_ch_get_gpoval0(struct dma350_ch_dev_t *dev)
2869 {
2870 return dev->cfg.ch_base->CH_GPOREAD0;
2871 }
2872
2873 __STATIC_INLINE
dma350_ch_set_streamtype(struct dma350_ch_dev_t * dev,enum dma350_ch_streamtype_t type)2874 void dma350_ch_set_streamtype(struct dma350_ch_dev_t *dev,
2875 enum dma350_ch_streamtype_t type)
2876 {
2877 dev->cfg.ch_base->CH_STREAMINTCFG =
2878 (dev->cfg.ch_base->CH_STREAMINTCFG &
2879 (~DMA_CH_STREAMINTCFG_STREAMTYPE_Msk)) |
2880 (type & DMA_CH_STREAMINTCFG_STREAMTYPE_Msk);
2881 }
2882
2883 __STATIC_INLINE
dma350_ch_set_linkmemattrlo(struct dma350_ch_dev_t * dev,uint8_t memattrlo)2884 void dma350_ch_set_linkmemattrlo(struct dma350_ch_dev_t *dev, uint8_t memattrlo)
2885 {
2886 SET_FIELD(dev->cfg.ch_base->CH_LINKATTR, memattrlo,
2887 DMA_CH_LINKATTR_LINKMEMATTRLO_Pos,
2888 DMA_CH_LINKATTR_LINKMEMATTRLO_Msk);
2889 }
2890
2891 __STATIC_INLINE
dma350_ch_set_linkmemattrhi(struct dma350_ch_dev_t * dev,uint8_t memattrhi)2892 void dma350_ch_set_linkmemattrhi(struct dma350_ch_dev_t *dev, uint8_t memattrhi)
2893 {
2894 SET_FIELD(dev->cfg.ch_base->CH_LINKATTR, memattrhi,
2895 DMA_CH_LINKATTR_LINKMEMATTRHI_Pos,
2896 DMA_CH_LINKATTR_LINKMEMATTRHI_Msk);
2897 }
2898
2899 __STATIC_INLINE
dma350_ch_set_linkshareattr(struct dma350_ch_dev_t * dev,uint8_t shareattr)2900 void dma350_ch_set_linkshareattr(struct dma350_ch_dev_t *dev, uint8_t shareattr)
2901 {
2902 SET_FIELD(dev->cfg.ch_base->CH_LINKATTR, shareattr,
2903 DMA_CH_LINKATTR_LINKSHAREATTR_Pos,
2904 DMA_CH_LINKATTR_LINKSHAREATTR_Msk);
2905 }
2906
2907 __STATIC_INLINE
dma350_ch_enable_linkaddr(struct dma350_ch_dev_t * dev)2908 void dma350_ch_enable_linkaddr(struct dma350_ch_dev_t *dev)
2909 {
2910 dev->cfg.ch_base->CH_LINKADDR |= DMA_CH_LINKADDR_LINKADDREN_Msk;
2911 }
2912
2913 __STATIC_INLINE
dma350_ch_disable_linkaddr(struct dma350_ch_dev_t * dev)2914 void dma350_ch_disable_linkaddr(struct dma350_ch_dev_t *dev)
2915 {
2916 dev->cfg.ch_base->CH_LINKADDR &= ~(DMA_CH_LINKADDR_LINKADDREN_Msk);
2917 }
2918
2919 __STATIC_INLINE
dma350_ch_set_linkaddr32(struct dma350_ch_dev_t * dev,uint32_t linkaddr)2920 void dma350_ch_set_linkaddr32(struct dma350_ch_dev_t *dev, uint32_t linkaddr)
2921 {
2922 dev->cfg.ch_base->CH_LINKADDR =
2923 (dev->cfg.ch_base->CH_LINKADDR & (~DMA_CH_LINKADDR_LINKADDR_Msk)) |
2924 ((uint32_t)linkaddr & DMA_CH_LINKADDR_LINKADDR_Msk);
2925 }
2926
2927 __STATIC_INLINE
dma350_cmdlink_set_regclear(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)2928 void dma350_cmdlink_set_regclear(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
2929 {
2930 cmdlink_cfg->header |= DMA350_CMDLINK_REGCLEAR_SET;
2931 }
2932
2933 __STATIC_INLINE
dma350_cmdlink_enable_intr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_intr_t intr)2934 void dma350_cmdlink_enable_intr(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2935 enum dma350_ch_intr_t intr)
2936 {
2937 cmdlink_cfg->header |= DMA350_CMDLINK_INTREN_SET;
2938 cmdlink_cfg->cfg.intren |= intr;
2939 }
2940
2941 __STATIC_INLINE
dma350_cmdlink_disable_intr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_intr_t intr)2942 void dma350_cmdlink_disable_intr(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2943 enum dma350_ch_intr_t intr)
2944 {
2945 cmdlink_cfg->header |= DMA350_CMDLINK_INTREN_SET;
2946 cmdlink_cfg->cfg.intren &= (~intr);
2947 }
2948
2949 __STATIC_INLINE
dma350_cmdlink_set_transize(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_transize_t transize)2950 void dma350_cmdlink_set_transize(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2951 enum dma350_ch_transize_t transize)
2952 {
2953 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
2954 cmdlink_cfg->cfg.ctrl =
2955 (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_TRANSIZE_Msk)) |
2956 (transize & DMA_CH_CTRL_TRANSIZE_Msk);
2957 }
2958
2959 __STATIC_INLINE
dma350_cmdlink_set_chprio(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t chprio)2960 void dma350_cmdlink_set_chprio(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2961 uint8_t chprio)
2962 {
2963 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
2964 cmdlink_cfg->cfg.ctrl =
2965 (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_CHPRIO_Msk)) |
2966 (((chprio & 0x000000FFUL) << DMA_CH_CTRL_CHPRIO_Pos) &
2967 DMA_CH_CTRL_CHPRIO_Msk);
2968 }
2969
2970 __STATIC_INLINE
dma350_cmdlink_set_xtype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_xtype_t xtype)2971 void dma350_cmdlink_set_xtype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2972 enum dma350_ch_xtype_t xtype)
2973 {
2974 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
2975 cmdlink_cfg->cfg.ctrl = (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_XTYPE_Msk)) |
2976 (xtype & DMA_CH_CTRL_XTYPE_Msk);
2977 }
2978
2979 __STATIC_INLINE
dma350_cmdlink_set_ytype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_ytype_t ytype)2980 void dma350_cmdlink_set_ytype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2981 enum dma350_ch_ytype_t ytype)
2982 {
2983 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
2984 cmdlink_cfg->cfg.ctrl = (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_YTYPE_Msk)) |
2985 (ytype & DMA_CH_CTRL_YTYPE_Msk);
2986 }
2987
2988 __STATIC_INLINE
dma350_cmdlink_set_regreloadtype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_regreloadtype_t regreloadtype)2989 void dma350_cmdlink_set_regreloadtype(
2990 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
2991 enum dma350_ch_regreloadtype_t regreloadtype)
2992 {
2993 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
2994 cmdlink_cfg->cfg.ctrl =
2995 (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_REGRELOADTYPE_Msk)) |
2996 (regreloadtype & DMA_CH_CTRL_REGRELOADTYPE_Msk);
2997 }
2998
2999 __STATIC_INLINE
dma350_cmdlink_set_donetype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_donetype_t donetype)3000 void dma350_cmdlink_set_donetype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3001 enum dma350_ch_donetype_t donetype)
3002 {
3003 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3004 cmdlink_cfg->cfg.ctrl =
3005 (cmdlink_cfg->cfg.ctrl & (~DMA_CH_CTRL_DONETYPE_Msk)) |
3006 (donetype & DMA_CH_CTRL_DONETYPE_Msk);
3007 }
3008
3009 __STATIC_INLINE
dma350_cmdlink_enable_donepause(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3010 void dma350_cmdlink_enable_donepause(
3011 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3012 {
3013 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3014 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_DONEPAUSEEN_Msk;
3015 }
3016
3017 __STATIC_INLINE
dma350_cmdlink_disable_donepause(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3018 void dma350_cmdlink_disable_donepause(
3019 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3020 {
3021 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3022 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_DONEPAUSEEN_Msk);
3023 }
3024
3025 __STATIC_INLINE
dma350_cmdlink_enable_srctrigin(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3026 void dma350_cmdlink_enable_srctrigin(
3027 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3028 {
3029 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3030 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_USESRCTRIGIN_Msk;
3031 }
3032
3033 __STATIC_INLINE
dma350_cmdlink_disable_srctrigin(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3034 void dma350_cmdlink_disable_srctrigin(
3035 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3036 {
3037 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3038 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_USESRCTRIGIN_Msk);
3039 }
3040
3041 __STATIC_INLINE
dma350_cmdlink_enable_destrigin(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3042 void dma350_cmdlink_enable_destrigin(
3043 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3044 {
3045 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3046 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_USEDESTRIGIN_Msk;
3047 }
3048
3049 __STATIC_INLINE
dma350_cmdlink_disable_destrigin(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3050 void dma350_cmdlink_disable_destrigin(
3051 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3052 {
3053 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3054 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_USEDESTRIGIN_Msk);
3055 }
3056
3057 __STATIC_INLINE
dma350_cmdlink_enable_trigout(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3058 void dma350_cmdlink_enable_trigout(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3059 {
3060 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3061 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_USETRIGOUT_Msk;
3062 }
3063
3064 __STATIC_INLINE
dma350_cmdlink_disable_trigout(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3065 void dma350_cmdlink_disable_trigout(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3066 {
3067 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3068 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_USETRIGOUT_Msk);
3069 }
3070
3071 __STATIC_INLINE
dma350_cmdlink_enable_gpo(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3072 void dma350_cmdlink_enable_gpo(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3073 {
3074 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3075 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_USEGPO_Msk;
3076 }
3077
3078 __STATIC_INLINE
dma350_cmdlink_disable_gpo(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3079 void dma350_cmdlink_disable_gpo(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3080 {
3081 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3082 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_USEGPO_Msk);
3083 }
3084
3085 __STATIC_INLINE
dma350_cmdlink_enable_stream(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3086 void dma350_cmdlink_enable_stream(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3087 {
3088 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3089 cmdlink_cfg->cfg.ctrl |= DMA_CH_CTRL_USESTREAM_Msk;
3090 }
3091
3092 __STATIC_INLINE
dma350_cmdlink_disable_stream(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3093 void dma350_cmdlink_disable_stream(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3094 {
3095 cmdlink_cfg->header |= DMA350_CMDLINK_CTRL_SET;
3096 cmdlink_cfg->cfg.ctrl &= (~DMA_CH_CTRL_USESTREAM_Msk);
3097 }
3098
3099 __STATIC_INLINE
dma350_cmdlink_set_srcaddr32(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t src_addr)3100 void dma350_cmdlink_set_srcaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3101 uint32_t src_addr)
3102 {
3103 cmdlink_cfg->header |= DMA350_CMDLINK_SRC_ADDR_SET;
3104 cmdlink_cfg->header &= (~DMA350_CMDLINK_SRC_ADDRHI_SET);
3105 cmdlink_cfg->cfg.srcaddr = src_addr;
3106 }
3107
3108 __STATIC_INLINE
dma350_cmdlink_set_desaddr32(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t des_addr)3109 void dma350_cmdlink_set_desaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3110 uint32_t des_addr)
3111 {
3112 cmdlink_cfg->header |= DMA350_CMDLINK_DES_ADDR_SET;
3113 cmdlink_cfg->header &= (~DMA350_CMDLINK_DES_ADDRHI_SET);
3114 cmdlink_cfg->cfg.desaddr = des_addr;
3115 }
3116
3117 __STATIC_INLINE
dma350_cmdlink_set_xsize16(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint16_t src_xsize,uint16_t des_xsize)3118 void dma350_cmdlink_set_xsize16(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3119 uint16_t src_xsize, uint16_t des_xsize)
3120 {
3121 cmdlink_cfg->header |= DMA350_CMDLINK_XSIZE_SET;
3122 cmdlink_cfg->header &= (~DMA350_CMDLINK_XSIZEHI_SET);
3123 cmdlink_cfg->cfg.xsize = (des_xsize & 0x0000FFFFUL)
3124 << DMA_CH_XSIZE_DESXSIZE_Pos;
3125 cmdlink_cfg->cfg.xsize |= (src_xsize & 0x0000FFFFUL)
3126 << DMA_CH_XSIZE_SRCXSIZE_Pos;
3127 }
3128
3129 __STATIC_INLINE
dma350_cmdlink_set_xsize32(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t src_xsize,uint32_t des_xsize)3130 void dma350_cmdlink_set_xsize32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3131 uint32_t src_xsize, uint32_t des_xsize)
3132 {
3133 cmdlink_cfg->header |= DMA350_CMDLINK_XSIZE_SET;
3134 cmdlink_cfg->header |= DMA350_CMDLINK_XSIZEHI_SET;
3135 cmdlink_cfg->cfg.xsize = (des_xsize & 0x0000FFFFUL)
3136 << DMA_CH_XSIZE_DESXSIZE_Pos;
3137 cmdlink_cfg->cfg.xsize |= (src_xsize & 0x0000FFFFUL)
3138 << DMA_CH_XSIZE_SRCXSIZE_Pos;
3139 cmdlink_cfg->cfg.xsizehi = (des_xsize & 0xFFFF0000UL);
3140 cmdlink_cfg->cfg.xsizehi |= (src_xsize & 0xFFFF0000UL) >> 16;
3141 }
3142
3143 __STATIC_INLINE
dma350_cmdlink_set_srcmemattrlo(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrlo)3144 void dma350_cmdlink_set_srcmemattrlo(
3145 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo)
3146 {
3147 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3148 cmdlink_cfg->cfg.srctranscfg =
3149 (cmdlink_cfg->cfg.srctranscfg &
3150 (~DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk)) |
3151 (((memattrlo & 0x000000FFUL) << DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Pos) &
3152 DMA_CH_SRCTRANSCFG_SRCMEMATTRLO_Msk);
3153 }
3154
3155 __STATIC_INLINE
dma350_cmdlink_set_srcmemattrhi(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrhi)3156 void dma350_cmdlink_set_srcmemattrhi(
3157 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi)
3158 {
3159 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3160 cmdlink_cfg->cfg.srctranscfg =
3161 (cmdlink_cfg->cfg.srctranscfg &
3162 (~DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk)) |
3163 (((memattrhi & 0x000000FFUL) << DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Pos) &
3164 DMA_CH_SRCTRANSCFG_SRCMEMATTRHI_Msk);
3165 }
3166
3167 __STATIC_INLINE
dma350_cmdlink_set_srcshareattr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t shareattr)3168 void dma350_cmdlink_set_srcshareattr(
3169 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr)
3170 {
3171 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3172 cmdlink_cfg->cfg.srctranscfg =
3173 (cmdlink_cfg->cfg.srctranscfg &
3174 (~DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk)) |
3175 (((shareattr & 0x000000FFUL) << DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Pos) &
3176 DMA_CH_SRCTRANSCFG_SRCSHAREATTR_Msk);
3177 }
3178
3179 __STATIC_INLINE
dma350_cmdlink_set_desmemattrlo(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrlo)3180 void dma350_cmdlink_set_desmemattrlo(
3181 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo)
3182 {
3183 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3184 cmdlink_cfg->cfg.destranscfg =
3185 (cmdlink_cfg->cfg.destranscfg &
3186 (~DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk)) |
3187 (((memattrlo & 0x000000FFUL) << DMA_CH_DESTRANSCFG_DESMEMATTRLO_Pos) &
3188 DMA_CH_DESTRANSCFG_DESMEMATTRLO_Msk);
3189 }
3190
3191 __STATIC_INLINE
dma350_cmdlink_set_desmemattrhi(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrhi)3192 void dma350_cmdlink_set_desmemattrhi(
3193 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi)
3194 {
3195 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3196 cmdlink_cfg->cfg.destranscfg =
3197 (cmdlink_cfg->cfg.destranscfg &
3198 (~DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk)) |
3199 (((memattrhi & 0x000000FFUL) << DMA_CH_DESTRANSCFG_DESMEMATTRHI_Pos) &
3200 DMA_CH_DESTRANSCFG_DESMEMATTRHI_Msk);
3201 }
3202
3203 __STATIC_INLINE
dma350_cmdlink_set_desshareattr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t shareattr)3204 void dma350_cmdlink_set_desshareattr(
3205 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr)
3206 {
3207 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3208 cmdlink_cfg->cfg.destranscfg =
3209 (cmdlink_cfg->cfg.destranscfg &
3210 (~DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk)) |
3211 (((shareattr & 0x000000FFUL) << DMA_CH_DESTRANSCFG_DESSHAREATTR_Pos) &
3212 DMA_CH_DESTRANSCFG_DESSHAREATTR_Msk);
3213 }
3214
3215 __STATIC_INLINE
dma350_cmdlink_set_src_trans_secure(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3216 void dma350_cmdlink_set_src_trans_secure(
3217 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3218 {
3219 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3220 cmdlink_cfg->cfg.srctranscfg &= (~DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk);
3221 }
3222
3223 __STATIC_INLINE
dma350_cmdlink_set_src_trans_nonsecure(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3224 void dma350_cmdlink_set_src_trans_nonsecure(
3225 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3226 {
3227 cmdlink_cfg->cfg.srctranscfg |= DMA_CH_SRCTRANSCFG_SRCNONSECATTR_Msk;
3228 if (cmdlink_cfg->cfg.srctranscfg == DMA350_CH_SRCTRANSCFG_RESET_VALUE) {
3229 cmdlink_cfg->header &= (~DMA350_CMDLINK_SRCTRANSCFG_SET);
3230 }
3231 }
3232
3233 __STATIC_INLINE
dma350_cmdlink_set_des_trans_secure(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3234 void dma350_cmdlink_set_des_trans_secure(
3235 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3236 {
3237 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3238 cmdlink_cfg->cfg.destranscfg &= (~DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk);
3239 }
3240
3241 __STATIC_INLINE
dma350_cmdlink_set_des_trans_nonsecure(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3242 void dma350_cmdlink_set_des_trans_nonsecure(
3243 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3244 {
3245 cmdlink_cfg->cfg.destranscfg |= DMA_CH_DESTRANSCFG_DESNONSECATTR_Msk;
3246 if (cmdlink_cfg->cfg.destranscfg == DMA350_CH_DESTRANSCFG_RESET_VALUE) {
3247 cmdlink_cfg->header &= (~DMA350_CMDLINK_DESTRANSCFG_SET);
3248 }
3249 }
3250
3251 __STATIC_INLINE
dma350_cmdlink_set_src_trans_privileged(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3252 void dma350_cmdlink_set_src_trans_privileged(
3253 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3254 {
3255 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3256 cmdlink_cfg->cfg.srctranscfg |= DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk;
3257 }
3258
3259 __STATIC_INLINE
dma350_cmdlink_set_src_trans_unprivileged(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3260 void dma350_cmdlink_set_src_trans_unprivileged(
3261 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3262 {
3263 cmdlink_cfg->cfg.srctranscfg &= (~DMA_CH_SRCTRANSCFG_SRCPRIVATTR_Msk);
3264 if (cmdlink_cfg->cfg.srctranscfg == DMA350_CH_SRCTRANSCFG_RESET_VALUE) {
3265 cmdlink_cfg->header &= (~DMA350_CMDLINK_SRCTRANSCFG_SET);
3266 }
3267 }
3268
3269 __STATIC_INLINE
dma350_cmdlink_set_des_trans_privileged(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3270 void dma350_cmdlink_set_des_trans_privileged(
3271 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3272 {
3273 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3274 cmdlink_cfg->cfg.destranscfg |= DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk;
3275 }
3276
3277 __STATIC_INLINE
dma350_cmdlink_set_des_trans_unprivileged(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3278 void dma350_cmdlink_set_des_trans_unprivileged(
3279 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3280 {
3281 cmdlink_cfg->cfg.destranscfg &= (~DMA_CH_DESTRANSCFG_DESPRIVATTR_Msk);
3282 if (cmdlink_cfg->cfg.destranscfg == DMA350_CH_DESTRANSCFG_RESET_VALUE) {
3283 cmdlink_cfg->header &= (~DMA350_CMDLINK_DESTRANSCFG_SET);
3284 }
3285 }
3286
3287 __STATIC_INLINE
dma350_cmdlink_set_srcmaxburstlen(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t length)3288 void dma350_cmdlink_set_srcmaxburstlen(
3289 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t length)
3290 {
3291 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRANSCFG_SET;
3292 cmdlink_cfg->cfg.srctranscfg =
3293 (cmdlink_cfg->cfg.srctranscfg &
3294 (~DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Msk)) |
3295 (((length & 0x000000FFUL) << DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Pos) &
3296 DMA_CH_SRCTRANSCFG_SRCMAXBURSTLEN_Msk);
3297 }
3298
3299 __STATIC_INLINE
dma350_cmdlink_set_desmaxburstlen(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t length)3300 void dma350_cmdlink_set_desmaxburstlen(
3301 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t length)
3302 {
3303 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRANSCFG_SET;
3304 cmdlink_cfg->cfg.destranscfg =
3305 (cmdlink_cfg->cfg.destranscfg &
3306 (~DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Msk)) |
3307 (((length & 0x000000FFUL) << DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Pos) &
3308 DMA_CH_DESTRANSCFG_DESMAXBURSTLEN_Msk);
3309 }
3310
3311 __STATIC_INLINE
dma350_cmdlink_set_xaddrinc(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint16_t src_xaddrinc,uint16_t des_xaddrinc)3312 void dma350_cmdlink_set_xaddrinc(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3313 uint16_t src_xaddrinc, uint16_t des_xaddrinc)
3314 {
3315 cmdlink_cfg->header |= DMA350_CMDLINK_XADDRINC_SET;
3316 cmdlink_cfg->cfg.xaddrinc = (des_xaddrinc & 0x0000FFFFUL)
3317 << DMA_CH_XADDRINC_DESXADDRINC_Pos;
3318 cmdlink_cfg->cfg.xaddrinc |= (src_xaddrinc & 0x0000FFFFUL)
3319 << DMA_CH_XADDRINC_SRCXADDRINC_Pos;
3320 }
3321
3322 __STATIC_INLINE
dma350_cmdlink_set_yaddrstride(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint16_t src_yaddrstride,uint16_t des_yaddrstride)3323 void dma350_cmdlink_set_yaddrstride(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3324 uint16_t src_yaddrstride,
3325 uint16_t des_yaddrstride)
3326 {
3327 cmdlink_cfg->header |= DMA350_CMDLINK_YADDRSTRIDE_SET;
3328 cmdlink_cfg->cfg.yaddrstride = (des_yaddrstride & 0x0000FFFFUL)
3329 << DMA_CH_YADDRSTRIDE_DESYADDRSTRIDE_Pos;
3330 cmdlink_cfg->cfg.yaddrstride |= (src_yaddrstride & 0x0000FFFFUL)
3331 << DMA_CH_YADDRSTRIDE_SRCYADDRSTRIDE_Pos;
3332 }
3333
3334 __STATIC_INLINE
dma350_cmdlink_set_fillval(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t fillval)3335 void dma350_cmdlink_set_fillval(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3336 uint32_t fillval)
3337 {
3338 cmdlink_cfg->header |= DMA350_CMDLINK_FILLVAL_SET;
3339 cmdlink_cfg->cfg.fillval = fillval << DMA_CH_FILLVAL_FILLVAL_Pos;
3340 }
3341
3342 __STATIC_INLINE
dma350_cmdlink_set_ysize16(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint16_t src_ysize,uint16_t des_ysize)3343 void dma350_cmdlink_set_ysize16(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3344 uint16_t src_ysize, uint16_t des_ysize)
3345 {
3346 cmdlink_cfg->header |= DMA350_CMDLINK_YSIZE_SET;
3347 cmdlink_cfg->cfg.ysize = (des_ysize & 0x0000FFFFUL)
3348 << DMA_CH_YSIZE_DESYSIZE_Pos;
3349 cmdlink_cfg->cfg.ysize |= (src_ysize & 0x0000FFFFUL)
3350 << DMA_CH_YSIZE_SRCYSIZE_Pos;
3351 }
3352
3353 __STATIC_INLINE
dma350_cmdlink_set_tmpltsize(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t src_tmpltsize,uint8_t des_tmpltsize)3354 void dma350_cmdlink_set_tmpltsize(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3355 uint8_t src_tmpltsize, uint8_t des_tmpltsize)
3356 {
3357 if (src_tmpltsize <= DMA350_CH_TMPLTCFG_SRCTMPLTSIZE_MAX &&
3358 des_tmpltsize <= DMA350_CH_TMPLTCFG_DESTMPLTSIZE_MAX) {
3359 cmdlink_cfg->header |= DMA350_CMDLINK_TMPLTCFG_SET;
3360 cmdlink_cfg->cfg.tmpltcfg = (des_tmpltsize & 0x000000FFUL)
3361 << DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos;
3362 cmdlink_cfg->cfg.tmpltcfg |= (src_tmpltsize & 0x000000FFUL)
3363 << DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos;
3364 }
3365 }
3366
3367 __STATIC_INLINE
dma350_cmdlink_set_srctmplt(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t src_tmplt)3368 void dma350_cmdlink_set_srctmplt(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3369 uint32_t src_tmplt)
3370 {
3371 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTMPLT_SET;
3372 cmdlink_cfg->cfg.srctmplt = src_tmplt;
3373 }
3374
3375 __STATIC_INLINE
dma350_cmdlink_set_destmplt(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t des_tmplt)3376 void dma350_cmdlink_set_destmplt(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3377 uint32_t des_tmplt)
3378 {
3379 cmdlink_cfg->header |= DMA350_CMDLINK_DESTMPLT_SET;
3380 cmdlink_cfg->cfg.destmplt = des_tmplt;
3381 }
3382
3383 __STATIC_INLINE
dma350_cmdlink_set_srctriginsel(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t srctriginsel)3384 void dma350_cmdlink_set_srctriginsel(
3385 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t srctriginsel)
3386 {
3387 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRIGINCFG_SET;
3388 cmdlink_cfg->cfg.srctrigincfg = (cmdlink_cfg->cfg.srctrigincfg &
3389 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Msk)) |
3390 (((srctriginsel & 0x000000FFUL)
3391 << DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Pos) &
3392 DMA_CH_SRCTRIGINCFG_SRCTRIGINSEL_Msk);
3393 }
3394
3395 __STATIC_INLINE
dma350_cmdlink_set_srctrigintype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_srctrigintype_t type)3396 void dma350_cmdlink_set_srctrigintype(
3397 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3398 enum dma350_ch_srctrigintype_t type)
3399 {
3400 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRIGINCFG_SET;
3401 cmdlink_cfg->cfg.srctrigincfg =
3402 (cmdlink_cfg->cfg.srctrigincfg &
3403 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk)) |
3404 (type & DMA_CH_SRCTRIGINCFG_SRCTRIGINTYPE_Msk);
3405 }
3406
3407 __STATIC_INLINE
dma350_cmdlink_set_srctriginmode(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_srctriginmode_t mode)3408 void dma350_cmdlink_set_srctriginmode(
3409 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3410 enum dma350_ch_srctriginmode_t mode)
3411 {
3412 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRIGINCFG_SET;
3413 cmdlink_cfg->cfg.srctrigincfg =
3414 (cmdlink_cfg->cfg.srctrigincfg &
3415 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk)) |
3416 (mode & DMA_CH_SRCTRIGINCFG_SRCTRIGINMODE_Msk);
3417 }
3418
3419 __STATIC_INLINE
dma350_cmdlink_set_srctriginblksize(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t blksize)3420 void dma350_cmdlink_set_srctriginblksize(
3421 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t blksize)
3422 {
3423 cmdlink_cfg->header |= DMA350_CMDLINK_SRCTRIGINCFG_SET;
3424 cmdlink_cfg->cfg.srctrigincfg =
3425 (cmdlink_cfg->cfg.srctrigincfg &
3426 (~DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Msk)) |
3427 (((blksize & 0x000000FFUL)
3428 << DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Pos) &
3429 DMA_CH_SRCTRIGINCFG_SRCTRIGINBLKSIZE_Msk);
3430 }
3431
3432 __STATIC_INLINE
dma350_cmdlink_set_destriginsel(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t destriginsel)3433 void dma350_cmdlink_set_destriginsel(
3434 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t destriginsel)
3435 {
3436 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRIGINCFG_SET;
3437 cmdlink_cfg->cfg.destrigincfg = (cmdlink_cfg->cfg.destrigincfg &
3438 (~DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Msk)) |
3439 (((destriginsel & 0x000000FFUL)
3440 << DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Pos) &
3441 DMA_CH_DESTRIGINCFG_DESTRIGINSEL_Msk);
3442 }
3443
3444 __STATIC_INLINE
dma350_cmdlink_set_destrigintype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_destrigintype_t type)3445 void dma350_cmdlink_set_destrigintype(
3446 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3447 enum dma350_ch_destrigintype_t type)
3448 {
3449 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRIGINCFG_SET;
3450 cmdlink_cfg->cfg.destrigincfg =
3451 (cmdlink_cfg->cfg.destrigincfg &
3452 (~DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk)) |
3453 (type & DMA_CH_DESTRIGINCFG_DESTRIGINTYPE_Msk);
3454 }
3455
3456 __STATIC_INLINE
dma350_cmdlink_set_destriginmode(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_destriginmode_t mode)3457 void dma350_cmdlink_set_destriginmode(
3458 struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3459 enum dma350_ch_destriginmode_t mode)
3460 {
3461 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRIGINCFG_SET;
3462 cmdlink_cfg->cfg.destrigincfg =
3463 (cmdlink_cfg->cfg.destrigincfg &
3464 (~DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk)) |
3465 (mode & DMA_CH_DESTRIGINCFG_DESTRIGINMODE_Msk);
3466 }
3467
3468 __STATIC_INLINE
dma350_cmdlink_set_destriginblksize(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t blksize)3469 void dma350_cmdlink_set_destriginblksize(
3470 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t blksize)
3471 {
3472 cmdlink_cfg->header |= DMA350_CMDLINK_DESTRIGINCFG_SET;
3473 cmdlink_cfg->cfg.destrigincfg =
3474 (cmdlink_cfg->cfg.destrigincfg &
3475 (~DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Msk)) |
3476 (((blksize & 0x000000FFUL)
3477 << DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Pos) &
3478 DMA_CH_DESTRIGINCFG_DESTRIGINBLKSIZE_Msk);
3479 }
3480
3481 __STATIC_INLINE
dma350_cmdlink_set_trigoutsel(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t trigoutsel)3482 void dma350_cmdlink_set_trigoutsel(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3483 uint8_t trigoutsel)
3484 {
3485 cmdlink_cfg->header |= DMA350_CMDLINK_TRIGOUTCFG_SET;
3486 cmdlink_cfg->cfg.trigoutcfg =
3487 (cmdlink_cfg->cfg.trigoutcfg & (~DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Msk)) |
3488 (((trigoutsel & 0x000000FFUL) << DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Pos) &
3489 DMA_CH_TRIGOUTCFG_TRIGOUTSEL_Msk);
3490 }
3491
3492 __STATIC_INLINE
dma350_cmdlink_set_trigouttype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_trigouttype_t type)3493 void dma350_cmdlink_set_trigouttype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3494 enum dma350_ch_trigouttype_t type)
3495 {
3496 cmdlink_cfg->header |= DMA350_CMDLINK_TRIGOUTCFG_SET;
3497 cmdlink_cfg->cfg.trigoutcfg =
3498 (cmdlink_cfg->cfg.trigoutcfg & (~DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk)) |
3499 (type & DMA_CH_TRIGOUTCFG_TRIGOUTTYPE_Msk);
3500 }
3501
3502 __STATIC_INLINE
dma350_cmdlink_set_gpoen0(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t gpoen0)3503 void dma350_cmdlink_set_gpoen0(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3504 uint32_t gpoen0)
3505 {
3506 cmdlink_cfg->header |= DMA350_CMDLINK_GPOEN0_SET;
3507 cmdlink_cfg->cfg.gpoen0 = gpoen0;
3508 }
3509
3510 __STATIC_INLINE
dma350_cmdlink_set_gpoval0(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t gpoval0)3511 void dma350_cmdlink_set_gpoval0(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3512 uint32_t gpoval0)
3513 {
3514 cmdlink_cfg->header |= DMA350_CMDLINK_GPOVAL0_SET;
3515 cmdlink_cfg->cfg.gpoval0 = gpoval0;
3516 }
3517
3518 __STATIC_INLINE
dma350_cmdlink_set_streamtype(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,enum dma350_ch_streamtype_t type)3519 void dma350_cmdlink_set_streamtype(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3520 enum dma350_ch_streamtype_t type)
3521 {
3522 cmdlink_cfg->header |= DMA350_CMDLINK_STREAMINTCFG_SET;
3523 cmdlink_cfg->cfg.streamintcfg = (cmdlink_cfg->cfg.streamintcfg &
3524 (~DMA_CH_STREAMINTCFG_STREAMTYPE_Msk)) |
3525 (type & DMA_CH_STREAMINTCFG_STREAMTYPE_Msk);
3526 }
3527
3528 __STATIC_INLINE
dma350_cmdlink_set_linkmemattrlo(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrlo)3529 void dma350_cmdlink_set_linkmemattrlo(
3530 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrlo)
3531 {
3532 cmdlink_cfg->header |= DMA350_CMDLINK_LINKATTR_SET;
3533 cmdlink_cfg->cfg.linkattr =
3534 (cmdlink_cfg->cfg.linkattr & (~DMA_CH_LINKATTR_LINKMEMATTRLO_Msk)) |
3535 (((memattrlo & 0x000000FFUL) << DMA_CH_LINKATTR_LINKMEMATTRLO_Pos) &
3536 DMA_CH_LINKATTR_LINKMEMATTRLO_Msk);
3537 }
3538
3539 __STATIC_INLINE
dma350_cmdlink_set_linkmemattrhi(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t memattrhi)3540 void dma350_cmdlink_set_linkmemattrhi(
3541 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t memattrhi)
3542 {
3543 cmdlink_cfg->header |= DMA350_CMDLINK_LINKATTR_SET;
3544 cmdlink_cfg->cfg.linkattr =
3545 (cmdlink_cfg->cfg.linkattr & (~DMA_CH_LINKATTR_LINKMEMATTRHI_Msk)) |
3546 (((memattrhi & 0x000000FFUL) << DMA_CH_LINKATTR_LINKMEMATTRHI_Pos) &
3547 DMA_CH_LINKATTR_LINKMEMATTRHI_Msk);
3548 }
3549
3550 __STATIC_INLINE
dma350_cmdlink_set_linkshareattr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint8_t shareattr)3551 void dma350_cmdlink_set_linkshareattr(
3552 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint8_t shareattr)
3553 {
3554 cmdlink_cfg->header |= DMA350_CMDLINK_LINKATTR_SET;
3555 cmdlink_cfg->cfg.linkattr =
3556 (cmdlink_cfg->cfg.linkattr & (~DMA_CH_LINKATTR_LINKSHAREATTR_Msk)) |
3557 (((shareattr & 0x000000FFUL) << DMA_CH_LINKATTR_LINKSHAREATTR_Pos) &
3558 DMA_CH_LINKATTR_LINKSHAREATTR_Msk);
3559 }
3560
3561 __STATIC_INLINE
dma350_cmdlink_set_cmdrestartcnt(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint16_t cnt)3562 void dma350_cmdlink_set_cmdrestartcnt(
3563 struct dma350_cmdlink_gencfg_t *cmdlink_cfg, uint16_t cnt)
3564 {
3565 cmdlink_cfg->header |= DMA350_CMDLINK_AUTOCFG_SET;
3566 cmdlink_cfg->cfg.autocfg = (cnt & 0x0000FFFFUL)
3567 << DMA_CH_AUTOCFG_CMDRESTARTCNT_Pos;
3568 }
3569
3570 __STATIC_INLINE
dma350_cmdlink_enable_cmdrestartinfen(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3571 void dma350_cmdlink_enable_cmdrestartinfen(
3572 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3573 {
3574 cmdlink_cfg->header |= DMA350_CMDLINK_AUTOCFG_SET;
3575 cmdlink_cfg->cfg.autocfg |= DMA_CH_AUTOCFG_CMDRESTARTINFEN_Msk;
3576 }
3577
3578 __STATIC_INLINE
dma350_cmdlink_disable_cmdrestartinfen(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3579 void dma350_cmdlink_disable_cmdrestartinfen(
3580 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3581 {
3582 cmdlink_cfg->header |= DMA350_CMDLINK_AUTOCFG_SET;
3583 cmdlink_cfg->cfg.autocfg &= (~DMA_CH_AUTOCFG_CMDRESTARTINFEN_Msk);
3584 }
3585
3586 __STATIC_INLINE
dma350_cmdlink_enable_linkaddr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3587 void dma350_cmdlink_enable_linkaddr(struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3588 {
3589 cmdlink_cfg->header |= DMA350_CMDLINK_LINKADDR_SET;
3590 cmdlink_cfg->cfg.linkaddr |= DMA_CH_LINKADDR_LINKADDREN_Msk;
3591 }
3592
3593 __STATIC_INLINE
dma350_cmdlink_disable_linkaddr(struct dma350_cmdlink_gencfg_t * cmdlink_cfg)3594 void dma350_cmdlink_disable_linkaddr(
3595 struct dma350_cmdlink_gencfg_t *cmdlink_cfg)
3596 {
3597 cmdlink_cfg->header |= DMA350_CMDLINK_LINKADDR_SET;
3598 cmdlink_cfg->cfg.linkaddr &= ~(DMA_CH_LINKADDR_LINKADDREN_Msk);
3599 }
3600
3601 __STATIC_INLINE
dma350_cmdlink_set_linkaddr32(struct dma350_cmdlink_gencfg_t * cmdlink_cfg,uint32_t linkaddr)3602 void dma350_cmdlink_set_linkaddr32(struct dma350_cmdlink_gencfg_t *cmdlink_cfg,
3603 uint32_t linkaddr)
3604 {
3605 cmdlink_cfg->header |= DMA350_CMDLINK_LINKADDR_SET;
3606 cmdlink_cfg->header &= ~(DMA350_CMDLINK_LINKADDRHI_SET);
3607 cmdlink_cfg->cfg.linkaddr =
3608 (cmdlink_cfg->cfg.linkaddr & (~DMA_CH_LINKADDR_LINKADDR_Msk)) |
3609 (linkaddr & DMA_CH_LINKADDR_LINKADDR_Msk);
3610 }
3611
3612 __STATIC_INLINE
dma350_ch_cmd(struct dma350_ch_dev_t * dev,enum dma350_ch_cmd_t cmd)3613 void dma350_ch_cmd(struct dma350_ch_dev_t *dev, enum dma350_ch_cmd_t cmd)
3614 {
3615 /* Wait outstanding CPU writes to avoid race condition with DMA */
3616 __DMB();
3617 dev->cfg.ch_base->CH_CMD = cmd;
3618 }
3619
3620 __STATIC_INLINE
dma350_ch_get_cmd(struct dma350_ch_dev_t * dev)3621 enum dma350_ch_cmd_t dma350_ch_get_cmd(struct dma350_ch_dev_t *dev)
3622 {
3623 return (enum dma350_ch_cmd_t)dev->cfg.ch_base->CH_CMD;
3624 }
3625
3626 __STATIC_INLINE
dma350_ch_is_busy(struct dma350_ch_dev_t * dev)3627 bool dma350_ch_is_busy(struct dma350_ch_dev_t *dev)
3628 {
3629 return (dev->cfg.ch_base->CH_CMD & DMA350_CH_CMD_ENABLECMD) != 0;
3630 }
3631
3632 __STATIC_INLINE
dma350_ch_is_ready(struct dma350_ch_dev_t * dev)3633 bool dma350_ch_is_ready(struct dma350_ch_dev_t *dev)
3634 {
3635 return (dev->cfg.ch_base->CH_CMD & DMA350_CH_CMD_ENABLECMD) == 0;
3636 }
3637
3638 __STATIC_INLINE
dma350_ch_get_status(struct dma350_ch_dev_t * dev)3639 union dma350_ch_status_t dma350_ch_get_status(struct dma350_ch_dev_t *dev)
3640 {
3641 return (union dma350_ch_status_t) {
3642 .w = (dev->cfg.ch_base->CH_STATUS)
3643 };
3644 }
3645
3646 __STATIC_INLINE
dma350_ch_enable_intr(struct dma350_ch_dev_t * dev,enum dma350_ch_intr_t intr)3647 void dma350_ch_enable_intr(struct dma350_ch_dev_t *dev,
3648 enum dma350_ch_intr_t intr)
3649 {
3650 dev->cfg.ch_base->CH_INTREN = dev->cfg.ch_base->CH_INTREN | intr;
3651 }
3652
3653 __STATIC_INLINE
dma350_ch_disable_intr(struct dma350_ch_dev_t * dev,enum dma350_ch_intr_t intr)3654 void dma350_ch_disable_intr(struct dma350_ch_dev_t *dev,
3655 enum dma350_ch_intr_t intr)
3656 {
3657 dev->cfg.ch_base->CH_INTREN = dev->cfg.ch_base->CH_INTREN & (~intr);
3658 }
3659
3660 #if DMA_CH_STATUS_INTR_DONE != DMA_CH_INTREN_INTREN_DONE || \
3661 DMA_CH_STATUS_INTR_ERR != DMA_CH_INTREN_INTREN_ERR || \
3662 DMA_CH_STATUS_INTR_DISABLED != DMA_CH_INTREN_INTREN_DISABLED || \
3663 DMA_CH_STATUS_INTR_STOPPED != DMA_CH_INTREN_INTREN_STOPPED || \
3664 DMA_CH_STATUS_INTR_SRCTRIGINWAIT != DMA_CH_INTREN_INTREN_SRCTRIGINWAIT || \
3665 DMA_CH_STATUS_INTR_DESTRIGINWAIT != DMA_CH_INTREN_INTREN_DESTRIGINWAIT || \
3666 DMA_CH_STATUS_INTR_TRIGOUTACKWAIT != DMA_CH_INTREN_INTREN_TRIGOUTACKWAIT
3667 #error "STATUS_INTR INTREN_INTREN not aligned anymore!"
3668 #endif
3669 __STATIC_INLINE
dma350_ch_is_intr_set(struct dma350_ch_dev_t * dev,enum dma350_ch_intr_t intr)3670 bool dma350_ch_is_intr_set(struct dma350_ch_dev_t *dev,
3671 enum dma350_ch_intr_t intr)
3672 {
3673 return (dev->cfg.ch_base->CH_STATUS & intr) != 0;
3674 }
3675
3676 __STATIC_INLINE
dma350_ch_is_stat_set(struct dma350_ch_dev_t * dev,enum dma350_ch_stat_t stat)3677 bool dma350_ch_is_stat_set(struct dma350_ch_dev_t *dev,
3678 enum dma350_ch_stat_t stat)
3679 {
3680 return (dev->cfg.ch_base->CH_STATUS & stat) != 0;
3681 }
3682
3683 __STATIC_INLINE
dma350_ch_clear_stat(struct dma350_ch_dev_t * dev,enum dma350_ch_stat_t stat)3684 void dma350_ch_clear_stat(struct dma350_ch_dev_t *dev,
3685 enum dma350_ch_stat_t stat)
3686 {
3687 dev->cfg.ch_base->CH_STATUS = stat;
3688 }
3689
3690 __STATIC_INLINE
dma350_ch_set_autocfg_restart_cnt(struct dma350_ch_dev_t * dev,uint16_t cnt)3691 void dma350_ch_set_autocfg_restart_cnt(struct dma350_ch_dev_t *dev,
3692 uint16_t cnt)
3693 {
3694 dev->cfg.ch_base->CH_AUTOCFG = (cnt & DMA_CH_AUTOCFG_CMDRESTARTCNT_Msk);
3695 }
3696
3697 __STATIC_INLINE
dma350_ch_set_autocfg_restart_inf(struct dma350_ch_dev_t * dev)3698 void dma350_ch_set_autocfg_restart_inf(struct dma350_ch_dev_t *dev)
3699 {
3700 dev->cfg.ch_base->CH_AUTOCFG = DMA_CH_AUTOCFG_CMDRESTARTINFEN_Msk;
3701 }
3702
3703 __STATIC_INLINE
dma350_ch_set_tmplt_src_size(struct dma350_ch_dev_t * dev,uint32_t size)3704 void dma350_ch_set_tmplt_src_size(struct dma350_ch_dev_t *dev, uint32_t size)
3705 {
3706 SET_FIELD(dev->cfg.ch_base->CH_TMPLTCFG, size,
3707 DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Pos,
3708 DMA_CH_TMPLTCFG_SRCTMPLTSIZE_Msk);
3709 }
3710
3711 __STATIC_INLINE
dma350_ch_set_tmplt_des_size(struct dma350_ch_dev_t * dev,uint32_t size)3712 void dma350_ch_set_tmplt_des_size(struct dma350_ch_dev_t *dev, uint32_t size)
3713 {
3714 SET_FIELD(dev->cfg.ch_base->CH_TMPLTCFG, size,
3715 DMA_CH_TMPLTCFG_DESTMPLTSIZE_Pos,
3716 DMA_CH_TMPLTCFG_DESTMPLTSIZE_Msk);
3717 }
3718
3719 __STATIC_INLINE
dma350_ch_set_tmplt_src(struct dma350_ch_dev_t * dev,uint32_t tmplt)3720 void dma350_ch_set_tmplt_src(struct dma350_ch_dev_t *dev, uint32_t tmplt)
3721 {
3722 dev->cfg.ch_base->CH_SRCTMPLT = tmplt;
3723 }
3724
3725 __STATIC_INLINE
dma350_ch_set_tmplt_des(struct dma350_ch_dev_t * dev,uint32_t tmplt)3726 void dma350_ch_set_tmplt_des(struct dma350_ch_dev_t *dev, uint32_t tmplt)
3727 {
3728 dev->cfg.ch_base->CH_DESTMPLT = tmplt;
3729 }
3730
3731 __STATIC_INLINE
dma350_ch_get_tmplt_src(struct dma350_ch_dev_t * dev)3732 uint32_t dma350_ch_get_tmplt_src(struct dma350_ch_dev_t *dev)
3733 {
3734 return dev->cfg.ch_base->CH_SRCTMPLT;
3735 }
3736
3737 __STATIC_INLINE
dma350_ch_get_tmplt_des(struct dma350_ch_dev_t * dev)3738 uint32_t dma350_ch_get_tmplt_des(struct dma350_ch_dev_t *dev)
3739 {
3740 return dev->cfg.ch_base->CH_DESTMPLT;
3741 }
3742
3743 #ifdef __cplusplus
3744 }
3745 #endif
3746 #endif /* __DMA350_CH_DRV_H */
3747
