| /hal_infineon-latest/mtb-hal-cat1/source/ |
| D | cyhal_utils_impl.c | 140 …al_utils_allocate_peri(cyhal_clock_t *clock, uint8_t peri_group, cyhal_clock_block_t div, bool acc… in _cyhal_utils_allocate_peri()
509 …cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item, cyhal_clock_block_t div, bool acc… in _cyhal_utils_allocate_clock()
556 …cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item, cyhal_clock_block_t div, bool acc… in _cyhal_utils_allocate_clock()
585 …cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item, cyhal_clock_block_t div, bool acc… in _cyhal_utils_allocate_clock()
592 …cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item, cyhal_clock_block_t div, bool acc… in _cyhal_utils_allocate_clock()
626 bool only_below_desired, uint32_t *div) in _cyhal_utils_find_hf_clk_div()
664 uint32_t *div) in _cyhal_utils_find_hf_source_n_divider()
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| D | cyhal_clock.c | 579 …int32_t desired_hz, uint32_t divider_bits, const cyhal_clock_tolerance_t *tolerance, uint32_t *div) in _cyhal_clock_compute_div()
1488 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0); in _cyhal_clock_set_enabled_fll() local
1540 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0); in _cyhal_clock_set_frequency_fll() local
1651 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0); in _cyhal_clock_set_enabled_pll() local
1740 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0); in _cyhal_clock_set_frequency_pll() local
1859 uint32_t div; in _cyhal_clock_set_frequency_mf() local
2265 uint32_t div; in _cyhal_clock_set_frequency_fast() local
2334 uint32_t div; in _cyhal_clock_set_frequency_slow() local
2454 uint32_t div; in _cyhal_clock_set_frequency_mem() local
2505 uint32_t div; in _cyhal_clock_set_frequency_peri() local
[all …]
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| D | cyhal_pwm.c | 193 uint32_t div = (uint32_t)((source_hz + (desired_freq_hz - 1))/ desired_freq_hz); in _cyhal_pwm_update_clock_freq() local
226 uint32_t div = 0; in _cyhal_pwm_init_clock() local
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| D | cyhal_adc_sar.c | 1184 uint32_t div = source_hz / DESIRED_DIVIDER; in _cyhal_adc_config_hw() local
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| D | cyhal_sdhc.c | 796 const cyhal_clock_tolerance_t *tolerance, bool only_below_desired, uint32_t *div) in _cyhal_sdxx_find_best_div()
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| /hal_infineon-latest/XMCLib/drivers/src/ |
| D | xmc_bccu.c | 158 void XMC_BCCU_SetFastClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div) in XMC_BCCU_SetFastClockPrescaler()
170 void XMC_BCCU_SetDimClockPrescaler (XMC_BCCU_t *const bccu, uint32_t div) in XMC_BCCU_SetDimClockPrescaler()
182 void XMC_BCCU_SelectBitClock (XMC_BCCU_t *const bccu, XMC_BCCU_BCLK_MODE_t div) in XMC_BCCU_SelectBitClock()
559 void XMC_BCCU_DIM_SetDimDivider (XMC_BCCU_DIM_t *const dim_engine, uint32_t div) in XMC_BCCU_DIM_SetDimDivider()
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| D | xmc_ccu8.c | 101 #define XMC_CCU8_SLICE_CHECK_DTC_DIV(div) \ argument
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| /hal_infineon-latest/mtb-hal-cat1/include_pvt/ |
| D | cyhal_hw_resources.h | 250 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div)) argument
259 …#define _CYHAL_PERIPHERAL_GROUP_ADJUST(instance, group, div) (((group + (instance * PERI0_P… argument
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| D | cyhal_utils_impl.h | 253 …_cyhal_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, uint32_t div) in _cyhal_utils_peri_pclk_set_divider()
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| /hal_infineon-latest/mtb-pdl-cat1/drivers/source/ |
| D | cy_sysanalog.c | 47 #define IS_DIV_VALID(div) (((div) == CY_SYSANALOG_DEEPSLEEP_CLK_NO_DIV) || \ argument
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| D | cy_sysclk_v2.c | 2837 uint32_t div = (_FLD2VAL(SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV, SRSS_CLK_ECO_PRESCALE) + \ in Cy_SysClk_EcoPrescaleGetFrequency() local
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| /hal_infineon-latest/XMCLib/drivers/inc/ |
| D | xmc_ccu8.h | 895 uint32_t div : 2; /**< Dead time prescaler divider value. member
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| /hal_infineon-latest/mtb-pdl-cat1/drivers/include/ |
| D | cy_sysclk.h | 8083 #define CY_SYSCLK_FLL_IS_DIVIDER_VALID(div) (((div) == CY_SYSCLK_PUMP_NO_DIV) || \ argument
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| /hal_infineon-latest/btstack/wiced_include/ |
| D | wiced_bt_dev.h | 1104 …uint16_t div; /**< local DIV to generate local LTK=d1(ER,DIV,0) and CS… member
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