1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_ESPI_VW_H 7 #define _MEC_ESPI_VW_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 #include "mec_defs.h" 13 14 /* Interfaces to any C modules */ 15 #ifdef __cplusplus 16 extern "C" 17 { 18 #endif 19 20 /* forward declarations */ 21 struct mec_espi_io_regs; 22 struct mec_espi_mem_regs; 23 struct mec_espi_vw_regs; 24 25 /* ---- Virtual Wire channel (VW) ---- */ 26 27 /* Configuration for a Controller-to-Target(EC) eSPI Virtual Wire group 28 * host_idx is the eSPI Host Index from the eSPI specification this 29 * CTVW register represents. 30 * reset_src is the signal triggering CTVW hardware to load reset 31 * default values into the 4 VWire source bits in this group. 32 * reset_state_bm bits [3:0] are the reset state of [SRC3:SRC0] 33 * src_val_bm loads each of the 4 VWire source bits based on: 34 * A 1 bit in b[3:0] causes the config API to load the value 35 * in src_val bit n+4 into the VWire SRC[n] bit. 0 <= n <= 3. 36 * src_ien[4] is the interrupt enable and trigger for each VWire. 37 */ 38 #define MEC_ESPI_VW_SRC_VAL_WR_MSK 0xfu; 39 #define MEC_ESPI_VW_SRC_VAL_MSK 0xf0u; 40 41 enum mec_espi_vw_reset_source { 42 MEC_ESPI_VW_RESET_ESPI = 0, 43 MEC_ESPI_VW_RESET_SYS, 44 MEC_ESPI_VW_RESET_SIO, 45 MEC_ESPI_VW_RESET_PLTRST, 46 MEC_ESPI_VW_RESET_MAX, 47 }; 48 49 enum mec_espi_vw_ct_intr_en { 50 MEC_ESPI_VW_CT_IEN_DIS = 0, 51 MEC_ESPI_VW_CT_IEN_LL, 52 MEC_ESPI_VW_CT_IEN_LH, 53 MEC_ESPI_VW_CT_IEN_RE, 54 MEC_ESPI_VW_CT_IEN_FE, 55 MEC_ESPI_VW_CT_IEN_BE, 56 MEC_ESPI_VW_CT_IEN_MAX, 57 }; 58 59 enum mec_espi_vw_reg_idx { 60 MEC_ESPI_CTVW00_REG_IDX = 0, 61 MEC_ESPI_CTVW01_REG_IDX, 62 MEC_ESPI_CTVW02_REG_IDX, 63 MEC_ESPI_CTVW03_REG_IDX, 64 MEC_ESPI_CTVW04_REG_IDX, 65 MEC_ESPI_CTVW05_REG_IDX, 66 MEC_ESPI_CTVW06_REG_IDX, 67 MEC_ESPI_CTVW07_REG_IDX, 68 MEC_ESPI_CTVW08_REG_IDX, 69 MEC_ESPI_CTVW09_REG_IDX, 70 MEC_ESPI_CTVW10_REG_IDX, 71 MEC_ESPI_TCVW00_REG_IDX, 72 MEC_ESPI_TCVW01_REG_IDX, 73 MEC_ESPI_TCVW02_REG_IDX, 74 MEC_ESPI_TCVW03_REG_IDX, 75 MEC_ESPI_TCVW04_REG_IDX, 76 MEC_ESPI_TCVW05_REG_IDX, 77 MEC_ESPI_TCVW06_REG_IDX, 78 MEC_ESPI_TCVW07_REG_IDX, 79 MEC_ESPI_TCVW08_REG_IDX, 80 MEC_ESPI_TCVW09_REG_IDX, 81 MEC_ESPI_TCVW10_REG_IDX, 82 MEC_ESPI_VW_MAX_REG_IDX, 83 }; 84 85 enum mec_espi_vw_source { 86 MEC_ESPI_VW_SOURCE_0 = 0, 87 MEC_ESPI_VW_SOURCE_1, 88 MEC_ESPI_VW_SOURCE_2, 89 MEC_ESPI_VW_SOURCE_3, 90 MEC_ESPI_VW_SOURCE_MAX, 91 }; 92 93 struct mec_espi_vw_config { 94 uint8_t host_idx; 95 uint8_t reset_src; 96 uint8_t reset_val_bm; 97 uint8_t src_val_bm; 98 uint8_t src_irq_sel[4]; 99 }; 100 101 /* MEC5 CT VWires are grouped into two aggregated EC GIRQs 102 * bank 0 contains CTVW00 - CTVW06 sources 103 * bank 1 contains CTVW07 - CTVW10 sources 104 */ 105 enum espi_ctvw_irq_bank { 106 MEC_ESPI_CTVW_IRQ_BANK_0 = 0, 107 MEC_ESPI_CTVW_IRQ_BANK_1, 108 MEC_ESPI_CTVW_IRQ_BANK_MAX, 109 }; 110 111 /* mec_espi_vw_config: Update configuration of a single VWire */ 112 #define MEC_ESPI_VW_CFG_IRQSEL_POS 0 113 #define MEC_ESPI_VW_CFG_IRQSEL_MSK0 0x7u 114 #define MEC_ESPI_VW_CFG_IRQSEL_MSK 0x7u 115 #define MEC_ESPI_VW_CFG_IRQSEL_DO_POS 3 116 #define MEC_ESPI_VW_CFG_RSTSRC_POS 4 117 #define MEC_ESPI_VW_CFG_RSTSRC_MSK0 0x3u 118 #define MEC_ESPI_VW_CFG_RSTSRC_MSK 0x30u 119 #define MEC_ESPI_VW_CFG_RSTSRC_DO_POS 6 120 #define MEC_ESPI_VW_CFG_RSTVAL_POS 8 121 #define MEC_ESPI_VW_CFG_RSTVAL_MSK0 0x1u 122 #define MEC_ESPI_VW_CFG_RSTVAL_MSK 0x100u 123 #define MEC_ESPI_VW_CFG_RSTVAL_DO_POS 9 124 125 /* mec_espi_vwg_config: Update configuration of all four VWires in a group */ 126 #define MEC_ESPI_VWG_CFG_HI_POS 0 127 #define MEC_ESPI_VWG_CFG_RST_SRC_POS 1 128 #define MEC_ESPI_VWG_CFG_SRC0_RST_VAL_POS 4 129 #define MEC_ESPI_VWG_CFG_SRC1_RST_VAL_POS 5 130 #define MEC_ESPI_VWG_CFG_SRC2_RST_VAL_POS 6 131 #define MEC_ESPI_VWG_CFG_SRC3_RST_VAL_POS 7 132 #define MEC_ESPI_VWG_CFG_SRC0_VAL_POS 8 133 #define MEC_ESPI_VWG_CFG_SRC1_VAL_POS 9 134 #define MEC_ESPI_VWG_CFG_SRC2_VAL_POS 10 135 #define MEC_ESPI_VWG_CFG_SRC3_VAL_POS 11 136 #define MEC_ESPI_VWG_CFG_SRC0_IRQ_POS 12 137 #define MEC_ESPI_VWG_CFG_SRC1_IRQ_POS 13 138 #define MEC_ESPI_VWG_CFG_SRC2_IRQ_POS 14 139 #define MEC_ESPI_VWG_CFG_SRC3_IRQ_POS 15 140 141 #define MEC_ESPI_VWG_CFG_SRC_RST_VAL_ALL (MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_RST_VAL_POS) \ 142 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC1_RST_VAL_POS) \ 143 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC2_RST_VAL_POS) \ 144 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC3_RST_VAL_POS)) 145 #define MEC_ESPI_VWG_CFG_SRC_VAL_ALL (MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_VAL_POS) \ 146 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC1_VAL_POS) \ 147 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC2_VAL_POS) \ 148 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC3_VAL_POS)) 149 #define MEC_ESPI_VWG_CFG_SRC_IRQ_ALL (MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_IRQ_POS) \ 150 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC1_IRQ_POS) \ 151 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC2_IRQ_POS) \ 152 | MEC_BIT(MEC_ESPI_VWG_CFG_SRC3_IRQ_POS)) 153 #define MEC_ESPI_VWG_CFG_ALL_PROP (MEC_BIT(MEC_ESPI_VWG_CFG_HI_POS) \ 154 | MEC_BIT(MEC_ESPI_VWG_CFG_RST_SRC_POS) \ 155 | MEC_ESPI_VWG_CFG_SRC_RST_VAL_ALL \ 156 | MEC_ESPI_VWG_CFG_SRC_VAL_ALL \ 157 | MEC_ESPI_VWG_CFG_SRC_IRQ_ALL) 158 159 160 /* CT VWire ECIA GIRQ functions */ 161 int mec_hal_espi_vw_ct_girq_ctrl(uint8_t ct_idx, uint8_t src_idx, uint8_t enable); 162 void mec_hal_espi_vw_ct_girq_ctrl_all(uint8_t enable); 163 int mec_hal_espi_vw_ct_girq_clr(uint8_t ct_idx, uint8_t src_idx); 164 int mec_hal_espi_vw_ct_girq_clr_msk(uint8_t ct_idx, uint8_t clr_msk); 165 void mec_hal_espi_vw_ct_girq_clr_all(void); 166 uint32_t mec_hal_espi_vw_ct_girq_sts(uint8_t ct_idx, uint8_t src_idx); 167 uint32_t mec_hal_espi_vw_ct_girq_res(uint8_t ct_idx, uint8_t src_idx); 168 uint32_t mec_hal_espi_vw_ct_group_girq_sts(uint8_t ct_idx); 169 void mec_hal_espi_vw_ct_group_girq_sts_clr(uint8_t ct_idx); 170 uint32_t mec_hal_espi_vw_ct_group_girq_res(uint8_t ct_idx); 171 int mec_hal_espi_vw_ct_group_girq_ctrl(uint8_t ct_idx, uint8_t src_msk, uint8_t enable); 172 uint32_t mec_hal_espi_vw_ct_girq_bank_result(uint8_t bank); 173 void mec_hal_espi_vw_ct_girq_bank_clr(uint8_t bank, uint32_t clrmsk); 174 175 void mec_hal_espi_vw_ct_from_girq_pos(uint8_t bank, uint8_t girq_pos, 176 uint8_t *ctidx, uint8_t *ctsrc); 177 178 int mec_hal_espi_vw_ct_irq_sel_set(struct mec_espi_vw_regs * const vwbase, uint8_t vw_idx, 179 uint8_t src_idx, uint8_t irq_sel); 180 int mec_hal_espi_vw_ct_irq_sel_set_all(struct mec_espi_vw_regs * const vwbase, uint8_t vw_idx, 181 uint32_t irq_sels); 182 183 int mec_hal_espi_vw_ct_wire_set(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 184 uint8_t widx, uint8_t val); 185 int mec_hal_espi_vw_ct_wire_get(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 186 uint8_t widx, uint8_t *val); 187 int mec_hal_espi_vw_ct_group_set(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 188 uint8_t val, uint8_t msk); 189 int mec_hal_espi_vw_ct_group_get(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 190 uint8_t *val); 191 192 int mec_hal_espi_vw_tc_wire_set(struct mec_espi_vw_regs * const vwbase, uint8_t tcidx, 193 uint8_t widx, uint8_t val, uint32_t flags); 194 int mec_hal_espi_vw_tc_wire_get(struct mec_espi_vw_regs * const vwbase, uint8_t tcidx, 195 uint8_t widx, uint8_t *val); 196 /* Sets *val bit[0]=C2T VWire state and bit[7]=C2T VWire change status */ 197 int mec_hal_espi_vw_tc_wire_cs_get(struct mec_espi_vw_regs * const vwbase, uint8_t tcidx, 198 uint8_t widx, uint8_t *val); 199 int mec_hal_espi_vw_tc_group_set(struct mec_espi_vw_regs * const vwbase, uint8_t tcidx, 200 uint8_t val, uint8_t msk, uint32_t flags); 201 int mec_hal_espi_vw_tc_group_get(struct mec_espi_vw_regs * const vwbase, uint8_t tcidx, 202 uint8_t *val); 203 204 /* Unlike the other channels where channel enable change (edge) 205 * detected, the virtual channel enable state is connected 206 * directly to the GIRQ status. This creates level detection 207 * and is always active when VWire channel is enabled. 208 */ 209 int mec_hal_espi_vw_is_enabled(struct mec_espi_io_regs * const iobase); 210 uint32_t mec_hal_espi_vw_en_status(struct mec_espi_io_regs * const iobase); 211 void mec_hal_espi_vw_en_status_clr(void); 212 void mec_hal_espi_vw_en_ien(uint8_t enable); 213 uint32_t mec_hal_espi_vw_en_result(void); 214 215 void mec_hal_espi_vw_ready_set(struct mec_espi_io_regs * const iobase); 216 int mec_hal_espi_vw_is_ready(struct mec_espi_io_regs * const iobase); 217 218 int mec_hal_espi_vwire_config(struct mec_espi_vw_regs *const vwbase, uint8_t vwidx, 219 uint8_t src_idx, uint8_t host_index, uint32_t config); 220 221 int mec_hal_espi_vwg_config(struct mec_espi_vw_regs * const vwbase, uint8_t vwidx, 222 struct mec_espi_vw_config *cfg, uint32_t flags); 223 224 int mec_hal_espi_vw_ct_host_index_set(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 225 uint8_t host_index); 226 int mec_hal_espi_vw_ct_reset_source_get(struct mec_espi_vw_regs * const vwbase, 227 uint8_t ctidx, uint8_t *reset_source); 228 int mec_hal_espi_vw_ct_reset_source_set(struct mec_espi_vw_regs * const vwbase, 229 uint8_t ctidx, uint8_t reset_source); 230 int mec_hal_espi_vw_ct_reset_state_set(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 231 uint8_t src_idx, uint8_t reset_state); 232 int mec_hal_espi_vw_ct_irqsel_set(struct mec_espi_vw_regs * const vwbase, uint8_t ctidx, 233 uint8_t src_idx, uint8_t irq_sel); 234 235 /* Access VWires using MEC5 VW register index and vwire source position 236 * idx_src: 237 * b[7:0] = tc vw index 238 * b[11:8] = VW in group [0:3] 239 * flags 240 * b[0]=1 if wire changed state wait infinite time for it to be transmitted. 241 */ 242 243 #define MEC_ESPI_VW_FLAG_WAIT_TC_TX_POS 0 244 245 struct mec_espi_vw { 246 uint8_t vwidx; /* value from enum mec_espi_vw_reg_idx */ 247 uint8_t srcidx; /* VWire's source index [0 to 3] in the group */ 248 uint8_t val; /* VWire's value (0 or 1) */ 249 uint8_t msk; /* group mask, used with group API's */ 250 }; 251 252 struct mec_espi_vw_poll { 253 void (*delayfp)(uint32_t); 254 uint32_t delay_param; 255 uint32_t nloops; 256 }; 257 258 int mec_hal_espi_vw_get_src(struct mec_espi_vw_regs *const vwbase, struct mec_espi_vw *vw, 259 uint32_t flags); 260 int mec_hal_espi_vw_set_src(struct mec_espi_vw_regs *const vwbase, struct mec_espi_vw *vw, 261 uint32_t flags); 262 int mec_hal_espi_vw_set_src_cs(struct mec_espi_vw_regs *const vwbase, struct mec_espi_vw *vw, 263 const struct mec_espi_vw_poll *vwp); 264 265 int mec_hal_espi_vw_get_src_group(struct mec_espi_vw_regs *const vwbase, struct mec_espi_vw *vw, 266 uint32_t flags); 267 int mec_hal_espi_vw_set_src_group(struct mec_espi_vw_regs *const vwbase, struct mec_espi_vw *vw, 268 uint32_t flags); 269 270 /* Get/Set value of a eSPI Virtual Wire given 271 * the VW's Host Index and source position (0-3) 272 */ 273 int mec_hal_espi_vw_set(struct mec_espi_vw_regs *const vwbase, uint8_t host_index, 274 uint8_t src_id, uint8_t val, uint32_t flags); 275 276 int mec_hal_espi_vw_set_cs(struct mec_espi_vw_regs * const vwbase, uint8_t host_index, 277 uint8_t src_id, uint8_t val, const struct mec_espi_vw_poll *vwp); 278 279 int mec_hal_espi_vw_get(struct mec_espi_vw_regs *const vwbase, uint8_t host_index, 280 uint8_t src_id, uint8_t *val); 281 282 /* Get/Set the group of 4 eSPI Virtual Wires for the given Host Index */ 283 int mec_hal_espi_vw_get_group(struct mec_espi_vw_regs *const vwbase, uint8_t host_index, 284 uint8_t *groupval); 285 286 int mec_hal_espi_vw_set_group(struct mec_espi_vw_regs *const vwbase, uint8_t host_index, 287 uint8_t groupval, uint8_t groupmsk, uint32_t flags); 288 289 #ifdef __cplusplus 290 } 291 #endif 292 293 #endif /* #ifndef _MEC_ESPI_VW_H */ 294
