1 /* 2 * Copyright (c) 2017-2021 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 struct lll_adv_iso_stream { 8 /* Associated BIG Handle */ 9 uint8_t big_handle; 10 struct ll_iso_datapath *dp; 11 12 /* Transmission queue */ 13 MEMQ_DECLARE(tx); 14 memq_link_t link_tx; 15 memq_link_t *link_tx_free; 16 17 /* Downstream last packet sequence number */ 18 uint16_t pkt_seq_num; 19 }; 20 21 struct lll_adv_iso { 22 struct lll_hdr hdr; 23 struct lll_adv *adv; 24 25 uint8_t seed_access_addr[4]; 26 uint8_t base_crc_init[2]; 27 uint16_t latency_prepare; 28 uint16_t latency_event; 29 uint16_t data_chan_prn_s; 30 uint16_t data_chan_remap_idx; 31 uint8_t next_chan_use; 32 33 uint64_t payload_count:39; 34 uint64_t enc:1; 35 uint64_t framing:1; 36 uint64_t handle:8; 37 uint64_t cssn:3; 38 uint32_t iso_interval:12; 39 40 uint8_t data_chan_map[PDU_CHANNEL_MAP_SIZE]; 41 uint8_t data_chan_count:6; 42 uint8_t num_bis:5; 43 uint8_t bn:3; 44 uint8_t nse:5; 45 uint8_t phy:3; 46 47 uint32_t sub_interval:20; 48 uint32_t max_pdu:8; 49 uint32_t pto:4; 50 51 uint32_t bis_spacing:20; 52 uint32_t max_sdu:8; 53 uint32_t irc:4; 54 55 uint32_t sdu_interval:20; 56 uint32_t irc_curr:4; 57 uint32_t ptc_curr:4; 58 uint32_t ptc:4; 59 60 uint8_t bn_curr:3; 61 uint8_t bis_curr:5; 62 63 uint8_t phy_flags:1; 64 65 #define CHM_STATE_MASK BIT_MASK(2U) 66 #define CHM_STATE_REQ BIT(0U) 67 #define CHM_STATE_SEND BIT(1U) 68 uint8_t volatile chm_ack; 69 uint8_t chm_req; 70 uint8_t chm_chan_map[PDU_CHANNEL_MAP_SIZE]; 71 uint8_t chm_chan_count:6; 72 73 uint8_t term_req:1; 74 uint8_t term_ack:1; 75 uint8_t term_reason; 76 77 uint8_t ctrl_chan_use; 78 uint8_t ctrl_expire; 79 uint16_t ctrl_instant; 80 81 /* Encryption */ 82 uint8_t giv[8]; 83 struct ccm ccm_tx; 84 85 #if defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO) 86 /* contains the offset in ticks from the adv_sync pointing to this ISO */ 87 uint32_t ticks_sync_pdu_offset; 88 uint16_t iso_lazy; 89 #endif /* CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ 90 91 uint16_t stream_handle[BT_CTLR_ADV_ISO_STREAM_MAX]; 92 }; 93 94 struct lll_adv_sync { 95 struct lll_hdr hdr; 96 struct lll_adv *adv; 97 98 uint8_t access_addr[4]; 99 uint8_t crc_init[3]; 100 101 uint16_t latency_prepare; 102 uint16_t latency_event; 103 uint16_t event_counter; 104 105 uint16_t data_chan_id; 106 struct { 107 uint8_t data_chan_map[PDU_CHANNEL_MAP_SIZE]; 108 uint8_t data_chan_count:6; 109 } chm[DOUBLE_BUFFER_SIZE]; 110 uint8_t chm_first; 111 uint8_t chm_last; 112 uint16_t chm_instant; 113 114 struct lll_adv_pdu data; 115 116 #if defined(CONFIG_BT_CTLR_ADV_PDU_LINK) 117 struct pdu_adv *last_pdu; 118 #endif /* CONFIG_BT_CTLR_ADV_PDU_LINK */ 119 120 #if defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO) 121 /* contains the offset in us from adv_aux pointing to this sync */ 122 uint32_t us_adv_sync_pdu_offset; 123 uint16_t sync_lazy; 124 #endif /* CONFIG_BT_TICKER_EXT_EXPIRE_INFO */ 125 126 #if defined(CONFIG_BT_CTLR_ADV_ISO) 127 struct lll_adv_iso *iso; 128 uint8_t volatile iso_chm_done_req; 129 uint8_t iso_chm_done_ack; 130 #endif /* CONFIG_BT_CTLR_ADV_ISO */ 131 132 #if defined(CONFIG_BT_CTLR_DF_ADV_CTE_TX) 133 /* This flag is used only by LLL. It holds information if CTE 134 * transmission was started by LLL. 135 */ 136 uint8_t cte_started:1; 137 #endif /* CONFIG_BT_CTLR_DF_ADV_CTE_TX */ 138 }; 139 140 struct lll_adv_aux { 141 struct lll_hdr hdr; 142 struct lll_adv *adv; 143 144 /* Implementation defined radio event counter to calculate auxiliary 145 * PDU channel index. 146 */ 147 uint16_t data_chan_counter; 148 149 /* Store used by primary channel PDU event to fill the 150 * auxiliary offset to this auxiliary PDU event. 151 */ 152 uint32_t ticks_pri_pdu_offset; 153 uint32_t us_pri_pdu_offset; 154 155 struct lll_adv_pdu data; 156 #if defined(CONFIG_BT_CTLR_ADV_PDU_LINK) 157 struct pdu_adv *last_pdu; 158 #endif /* CONFIG_BT_CTLR_ADV_PDU_LINK */ 159 }; 160 161 struct lll_adv { 162 struct lll_hdr hdr; 163 164 #if defined(CONFIG_BT_PERIPHERAL) 165 /* NOTE: conn context SHALL be after lll_hdr, 166 * check ull_conn_setup how it access the connection LLL 167 * context. 168 */ 169 struct lll_conn *conn; 170 uint8_t is_hdcd:1; 171 #endif /* CONFIG_BT_PERIPHERAL */ 172 173 uint8_t chan_map:3; 174 uint8_t chan_map_curr:3; 175 uint8_t filter_policy:2; 176 177 #if defined(CONFIG_BT_CTLR_ADV_EXT) 178 uint8_t phy_p:3; 179 uint8_t phy_s:3; 180 uint8_t phy_flags:1; 181 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 182 183 #if defined(CONFIG_BT_CTLR_SCAN_REQ_NOTIFY) 184 uint8_t scan_req_notify:1; 185 #endif 186 187 #if defined(CONFIG_BT_HCI_MESH_EXT) 188 uint8_t is_mesh:1; 189 #endif /* CONFIG_BT_HCI_MESH_EXT */ 190 191 #if defined(CONFIG_BT_CTLR_PRIVACY) 192 uint8_t rl_idx; 193 #endif /* CONFIG_BT_CTLR_PRIVACY */ 194 195 struct lll_adv_pdu adv_data; 196 struct lll_adv_pdu scan_rsp; 197 198 #if defined(CONFIG_BT_CTLR_ADV_EXT) 199 struct node_rx_hdr *node_rx_adv_term; 200 struct lll_adv_aux *aux; 201 202 #if defined(CONFIG_BT_CTLR_ADV_PERIODIC) 203 struct lll_adv_sync *sync; 204 #endif /* CONFIG_BT_CTLR_ADV_PERIODIC */ 205 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 206 207 #if defined(CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL) 208 int8_t tx_pwr_lvl; 209 #endif /* CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL */ 210 }; 211 212 int lll_adv_init(void); 213 int lll_adv_reset(void); 214 void lll_adv_prepare(void *param); 215 216 extern uint16_t ull_adv_lll_handle_get(struct lll_adv *lll); 217
