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/hal_altera-latest/drivers/altera_msgdma/inc/
Daltera_msgdma_descriptor_regs.h128 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS(base, data) \ argument
130 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_ADDRESS(base, data) \ argument
132 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_LENGTH(base, data) \ argument
136 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_CONTROL_STANDARD(base, data) \ argument
138 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_SEQUENCE_NUMBER(base, data) \ argument
140 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_BURST(base, data) \ argument
142 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_BURST(base, data) \ argument
144 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_STRIDE(base, data) \ argument
146 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_WRITE_STRIDE(base, data) \ argument
148 #define IOWR_ALTERA_MSGDMA_DESCRIPTOR_READ_ADDRESS_HIGH(base, data) \ argument
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Daltera_msgdma_prefetcher_regs.h265 #define IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(base, data) \ argument
270 #define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_LOW(base, data) \ argument
275 #define IOWR_ALT_MSGDMA_PREFETCHER_NEXT_DESCRIPTOR_PTR_HIGH(base, data) \ argument
280 #define IOWR_ALT_MSGDMA_PREFETCHER_DESCRIPTOR_POLLING_FREQ(base, data) \ argument
285 #define IOWR_ALT_MSGDMA_PREFETCHER_STATUS(base, data) \ argument
Daltera_msgdma_csr_regs.h154 #define IOWR_ALTERA_MSGDMA_CSR_STATUS(base, data) \ argument
156 #define IOWR_ALTERA_MSGDMA_CSR_CONTROL(base, data) \ argument
/hal_altera-latest/drivers/altera_avalon_pio/inc/
Daltera_avalon_pio_regs.h36 #define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) argument
40 #define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) argument
44 #define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) argument
48 #define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) argument
53 #define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) argument
57 #define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) argument
/hal_altera-latest/drivers/altera_avalon_i2c/inc/
Daltera_avalon_i2c_regs.h34 #define IORMW(base, reg, data, mask) IOWR(base,reg,(IORD(base,reg) & (~ma… argument
39 #define IOWR_ALT_AVALON_I2C_TFR_CMD(base, data) IOWR(base, ALT_AVALON_I2C_TFR_CMD_REG, … argument
53 #define IOWR_ALT_AVALON_I2C_RX_DATA(base, data) IOWR(base, ALT_AVALON_I2C_RX_DATA_REG, … argument
60 #define IOWR_ALT_AVALON_I2C_CTRL(base, data) IOWR(base, ALT_AVALON_I2C_CTRL_REG, dat… argument
61 #define IORMW_ALT_AVALON_I2C_CTRL(base, data, mask) IORMW(base,ALT_AVALON_I2C_CTRL_REG,data… argument
74 #define IOWR_ALT_AVALON_I2C_ISER(base, data) IOWR(base, ALT_AVALON_I2C_ISER_REG, dat… argument
75 #define IORMW_ALT_AVALON_I2C_ISER(base, data, mask) IORMW(base,ALT_AVALON_I2C_ISER_REG,data… argument
90 #define IOWR_ALT_AVALON_I2C_ISR(base, data) IOWR(base, ALT_AVALON_I2C_ISR_REG, data) argument
91 #define IORMW_ALT_AVALON_I2C_ISR(base, data, mask) IORMW(base,ALT_AVALON_I2C_ISR_REG,data,… argument
111 #define IOWR_ALT_AVALON_I2C_STATUS(base, data) IOWR(base, ALT_AVALON_I2C_STATUS_REG, d… argument
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/hal_altera-latest/drivers/altera_avalon_timer/inc/
Daltera_avalon_timer_regs.h40 #define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \ argument
53 #define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \ argument
72 #define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \ argument
83 #define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \ argument
94 #define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \ argument
105 #define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \ argument
118 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \ argument
129 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \ argument
140 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \ argument
151 #define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \ argument
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/hal_altera-latest/drivers/altera_epcq_controller/inc/
Daltera_epcq_controller_regs.h53 #define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \ argument
89 #define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \ argument
124 #define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \ argument
160 #define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \ argument
192 #define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \ argument
223 #define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \ argument
248 #define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \ argument
/hal_altera-latest/drivers/altera_generic_qspi_controller2/inc/
Daltera_generic_quad_spi_controller2_regs.h53 #define IOWR_ALTERA_QSPI_CONTROLLER2_STATUS(base, data) \ argument
89 #define IOWR_ALTERA_QSPI_CONTROLLER2_SID(base, data) \ argument
124 #define IOWR_ALTERA_QSPI_CONTROLLER2_RDID(base, data) \ argument
160 #define IOWR_ALTERA_QSPI_CONTROLLER2_MEM_OP(base, data) \ argument
192 #define IOWR_ALTERA_QSPI_CONTROLLER2_ISR(base, data) \ argument
223 #define IOWR_ALTERA_QSPI_CONTROLLER2_IMR(base, data) \ argument
248 #define IOWR_ALTERA_QSPI_CHIP_SELECT(base, data) \ argument
/hal_altera-latest/drivers/altera_avalon_spi/inc/
Daltera_avalon_spi_regs.h37 #define IOWR_ALTERA_AVALON_SPI_RXDATA(base, data) IOWR(base, ALTERA_AVALON_SPI_RXDATA_REG, data) argument
42 #define IOWR_ALTERA_AVALON_SPI_TXDATA(base, data) IOWR(base, ALTERA_AVALON_SPI_TXDATA_REG, data) argument
47 #define IOWR_ALTERA_AVALON_SPI_STATUS(base, data) IOWR(base, ALTERA_AVALON_SPI_STATUS_REG, data) argument
65 #define IOWR_ALTERA_AVALON_SPI_CONTROL(base, data) IOWR(base, ALTERA_AVALON_SPI_CONTROL_REG, dat… argument
83 #define IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, data) IOWR(base, ALTERA_AVALON_SPI_SLAVE_SEL_REG, d… argument
/hal_altera-latest/drivers/altera_avalon_uart/inc/
Daltera_avalon_uart_regs.h39 #define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) \ argument
47 #define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) \ argument
55 #define IOWR_ALTERA_AVALON_UART_STATUS(base, data) \ argument
88 #define IOWR_ALTERA_AVALON_UART_CONTROL(base, data) \ argument
121 #define IOWR_ALTERA_AVALON_UART_DIVISOR(base, data) \ argument
129 #define IOWR_ALTERA_AVALON_UART_EOP(base, data) \ argument
/hal_altera-latest/drivers/altera_avalon_sgdma/inc/
Daltera_avalon_sgdma_regs.h36 #define IOWR_ALTERA_AVALON_SGDMA_STATUS(base, data) IOWR(base, 0, data) argument
51 #define IOWR_ALTERA_AVALON_SGDMA_VERSION(base, data) IOWR(base, 1, data) argument
58 #define IOWR_ALTERA_AVALON_SGDMA_CONTROL(base, data) IOWR(base, 4, data) argument
90 #define IOWR_ALTERA_AVALON_SGDMA_NEXT_DESC_POINTER(base, data) IOWR(base, 8, data) argument
/hal_altera-latest/drivers/altera_avalon_jtag_uart/inc/
Daltera_avalon_jtag_uart_regs.h39 #define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ argument
55 #define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ argument
/hal_altera-latest/drivers/altera_avalon_jtag_uart/HAL/src/
Daltera_avalon_jtag_uart_init.c128 unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; in altera_avalon_jtag_uart_irq() local
Daltera_avalon_jtag_uart_read.c73 unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); in altera_avalon_jtag_uart_read() local
/hal_altera-latest/altera_hal/HAL/inc/sys/
Dalt_dma.h181 void* data, in alt_dma_rxchan_prepare()
Dalt_flash.h162 const void *data, int length) in alt_write_flash_block()
/hal_altera-latest/drivers/altera_generic_qspi_controller2/HAL/src/
Daltera_generic_quad_spi_controller2.c448 const void *data, /** data to be written */ in alt_qspi_controller2_write_block()
/hal_altera-latest/drivers/altera_epcq_controller/HAL/src/
Daltera_epcq_controller.c259 const void *data, /** data to be written */ in alt_epcq_controller_write_block()