1 /*!
2 \file gd32f4xx_dac.c
3 \brief DAC driver
4
5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
9 */
10
11 /*
12 Copyright (c) 2022, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32f4xx_dac.h"
39
40 /* DAC register bit offset */
41 #define DAC1_REG_OFFSET ((uint32_t)16U)
42 #define DH_12BIT_OFFSET ((uint32_t)16U)
43 #define DH_8BIT_OFFSET ((uint32_t)8U)
44
45 /*!
46 \brief deinitialize DAC
47 \param[in] none
48 \param[out] none
49 \retval none
50 */
dac_deinit(void)51 void dac_deinit(void)
52 {
53 rcu_periph_reset_enable(RCU_DACRST);
54 rcu_periph_reset_disable(RCU_DACRST);
55 }
56
57 /*!
58 \brief enable DAC
59 \param[in] dac_periph: DACx(x = 0,1)
60 \param[out] none
61 \retval none
62 */
dac_enable(uint32_t dac_periph)63 void dac_enable(uint32_t dac_periph)
64 {
65 if(DAC0 == dac_periph) {
66 DAC_CTL |= DAC_CTL_DEN0;
67 } else {
68 DAC_CTL |= DAC_CTL_DEN1;
69 }
70 }
71
72 /*!
73 \brief disable DAC
74 \param[in] dac_periph: DACx(x = 0,1)
75 \param[out] none
76 \retval none
77 */
dac_disable(uint32_t dac_periph)78 void dac_disable(uint32_t dac_periph)
79 {
80 if(DAC0 == dac_periph) {
81 DAC_CTL &= ~DAC_CTL_DEN0;
82 } else {
83 DAC_CTL &= ~DAC_CTL_DEN1;
84 }
85 }
86
87 /*!
88 \brief enable DAC DMA function
89 \param[in] dac_periph: DACx(x = 0,1)
90 \param[out] none
91 \retval none
92 */
dac_dma_enable(uint32_t dac_periph)93 void dac_dma_enable(uint32_t dac_periph)
94 {
95 if(DAC0 == dac_periph) {
96 DAC_CTL |= DAC_CTL_DDMAEN0;
97 } else {
98 DAC_CTL |= DAC_CTL_DDMAEN1;
99 }
100 }
101
102 /*!
103 \brief disable DAC DMA function
104 \param[in] dac_periph: DACx(x = 0,1)
105 \param[out] none
106 \retval none
107 */
dac_dma_disable(uint32_t dac_periph)108 void dac_dma_disable(uint32_t dac_periph)
109 {
110 if(DAC0 == dac_periph) {
111 DAC_CTL &= ~DAC_CTL_DDMAEN0;
112 } else {
113 DAC_CTL &= ~DAC_CTL_DDMAEN1;
114 }
115 }
116
117 /*!
118 \brief enable DAC output buffer
119 \param[in] dac_periph: DACx(x = 0,1)
120 \param[out] none
121 \retval none
122 */
dac_output_buffer_enable(uint32_t dac_periph)123 void dac_output_buffer_enable(uint32_t dac_periph)
124 {
125 if(DAC0 == dac_periph) {
126 DAC_CTL &= ~DAC_CTL_DBOFF0;
127 } else {
128 DAC_CTL &= ~DAC_CTL_DBOFF1;
129 }
130 }
131
132 /*!
133 \brief disable DAC output buffer
134 \param[in] dac_periph: DACx(x = 0,1)
135 \param[out] none
136 \retval none
137 */
dac_output_buffer_disable(uint32_t dac_periph)138 void dac_output_buffer_disable(uint32_t dac_periph)
139 {
140 if(DAC0 == dac_periph) {
141 DAC_CTL |= DAC_CTL_DBOFF0;
142 } else {
143 DAC_CTL |= DAC_CTL_DBOFF1;
144 }
145 }
146
147 /*!
148 \brief get DAC output value
149 \param[in] dac_periph: DACx(x = 0,1)
150 \param[out] none
151 \retval DAC output data
152 */
dac_output_value_get(uint32_t dac_periph)153 uint16_t dac_output_value_get(uint32_t dac_periph)
154 {
155 uint16_t data = 0U;
156 if(DAC0 == dac_periph) {
157 /* store the DAC0 output value */
158 data = (uint16_t)DAC0_DO;
159 } else {
160 /* store the DAC1 output value */
161 data = (uint16_t)DAC1_DO;
162 }
163 return data;
164 }
165
166 /*!
167 \brief set the DAC specified data holding register value
168 \param[in] dac_periph: DACx(x = 0,1)
169 \param[in] dac_align: data alignment
170 only one parameter can be selected which is shown as below:
171 \arg DAC_ALIGN_8B_R: data right 8 bit alignment
172 \arg DAC_ALIGN_12B_R: data right 12 bit alignment
173 \arg DAC_ALIGN_12B_L: data left 12 bit alignment
174 \param[in] data: data to be loaded
175 \param[out] none
176 \retval none
177 */
dac_data_set(uint32_t dac_periph,uint32_t dac_align,uint16_t data)178 void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data)
179 {
180 if(DAC0 == dac_periph) {
181 switch(dac_align) {
182 /* data right 12 bit alignment */
183 case DAC_ALIGN_12B_R:
184 DAC0_R12DH = data;
185 break;
186 /* data left 12 bit alignment */
187 case DAC_ALIGN_12B_L:
188 DAC0_L12DH = data;
189 break;
190 /* data right 8 bit alignment */
191 case DAC_ALIGN_8B_R:
192 DAC0_R8DH = data;
193 break;
194 default:
195 break;
196 }
197 } else {
198 switch(dac_align) {
199 /* data right 12 bit alignment */
200 case DAC_ALIGN_12B_R:
201 DAC1_R12DH = data;
202 break;
203 /* data left 12 bit alignment */
204 case DAC_ALIGN_12B_L:
205 DAC1_L12DH = data;
206 break;
207 /* data right 8 bit alignment */
208 case DAC_ALIGN_8B_R:
209 DAC1_R8DH = data;
210 break;
211 default:
212 break;
213 }
214 }
215 }
216
217 /*!
218 \brief enable DAC trigger
219 \param[in] dac_periph: DACx(x = 0,1)
220 \param[out] none
221 \retval none
222 */
dac_trigger_enable(uint32_t dac_periph)223 void dac_trigger_enable(uint32_t dac_periph)
224 {
225 if(DAC0 == dac_periph) {
226 DAC_CTL |= DAC_CTL_DTEN0;
227 } else {
228 DAC_CTL |= DAC_CTL_DTEN1;
229 }
230 }
231
232 /*!
233 \brief disable DAC trigger
234 \param[in] dac_periph: DACx(x = 0,1)
235 \param[out] none
236 \retval none
237 */
dac_trigger_disable(uint32_t dac_periph)238 void dac_trigger_disable(uint32_t dac_periph)
239 {
240 if(DAC0 == dac_periph) {
241 DAC_CTL &= ~DAC_CTL_DTEN0;
242 } else {
243 DAC_CTL &= ~DAC_CTL_DTEN1;
244 }
245 }
246
247 /*!
248 \brief set DAC trigger source
249 \param[in] dac_periph: DACx(x = 0,1)
250 \param[in] triggersource: external triggers of DAC
251 only one parameter can be selected which is shown as below:
252 \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
253 \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
254 \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
255 \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
256 \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
257 \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO
258 \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
259 \arg DAC_TRIGGER_SOFTWARE: software trigger
260 \param[out] none
261 \retval none
262 */
dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource)263 void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource)
264 {
265 if(DAC0 == dac_periph) {
266 /* configure DAC0 trigger source */
267 DAC_CTL &= ~DAC_CTL_DTSEL0;
268 DAC_CTL |= triggersource;
269 } else {
270 /* configure DAC1 trigger source */
271 DAC_CTL &= ~DAC_CTL_DTSEL1;
272 DAC_CTL |= (triggersource << DAC1_REG_OFFSET);
273 }
274 }
275
276 /*!
277 \brief enable DAC software trigger
278 \param[in] dac_periph: DACx(x = 0,1)
279 \retval none
280 */
dac_software_trigger_enable(uint32_t dac_periph)281 void dac_software_trigger_enable(uint32_t dac_periph)
282 {
283 if(DAC0 == dac_periph) {
284 DAC_SWT |= DAC_SWT_SWTR0;
285 } else {
286 DAC_SWT |= DAC_SWT_SWTR1;
287 }
288 }
289
290 /*!
291 \brief disable DAC software trigger
292 \param[in] dac_periph: DACx(x = 0,1)
293 \param[out] none
294 \retval none
295 */
dac_software_trigger_disable(uint32_t dac_periph)296 void dac_software_trigger_disable(uint32_t dac_periph)
297 {
298 if(DAC0 == dac_periph) {
299 DAC_SWT &= ~DAC_SWT_SWTR0;
300 } else {
301 DAC_SWT &= ~DAC_SWT_SWTR1;
302 }
303 }
304
305 /*!
306 \brief configure DAC wave mode
307 \param[in] dac_periph: DACx(x = 0,1)
308 \param[in] wave_mode: noise wave mode
309 only one parameter can be selected which is shown as below:
310 \arg DAC_WAVE_DISABLE: wave disable
311 \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
312 \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
313 \param[out] none
314 \retval none
315 */
dac_wave_mode_config(uint32_t dac_periph,uint32_t wave_mode)316 void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode)
317 {
318 if(DAC0 == dac_periph) {
319 /* configure DAC0 wave mode */
320 DAC_CTL &= ~DAC_CTL_DWM0;
321 DAC_CTL |= wave_mode;
322 } else {
323 /* configure DAC1 wave mode */
324 DAC_CTL &= ~DAC_CTL_DWM1;
325 DAC_CTL |= (wave_mode << DAC1_REG_OFFSET);
326 }
327 }
328
329 /*!
330 \brief configure DAC wave bit width
331 \param[in] dac_periph: DACx(x = 0,1)
332 \param[in] bit_width: noise wave bit width
333 only one parameter can be selected which is shown as below:
334 \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
335 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
336 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
337 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
338 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
339 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
340 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
341 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
342 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
343 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
344 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
345 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
346 \param[out] none
347 \retval none
348 */
dac_wave_bit_width_config(uint32_t dac_periph,uint32_t bit_width)349 void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width)
350 {
351 if(DAC0 == dac_periph) {
352 /* configure DAC0 wave bit width */
353 DAC_CTL &= ~DAC_CTL_DWBW0;
354 DAC_CTL |= bit_width;
355 } else {
356 /* configure DAC1 wave bit width */
357 DAC_CTL &= ~DAC_CTL_DWBW1;
358 DAC_CTL |= (bit_width << DAC1_REG_OFFSET);
359 }
360 }
361
362 /*!
363 \brief configure DAC LFSR noise mode
364 \param[in] dac_periph: DACx(x = 0,1)
365 \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode
366 only one parameter can be selected which is shown as below:
367 \arg DAC_LFSR_BIT0: unmask the LFSR bit0
368 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
369 \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
370 \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
371 \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
372 \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
373 \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
374 \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
375 \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
376 \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
377 \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
378 \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
379 \param[out] none
380 \retval none
381 */
dac_lfsr_noise_config(uint32_t dac_periph,uint32_t unmask_bits)382 void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits)
383 {
384 if(DAC0 == dac_periph) {
385 /* configure DAC0 LFSR noise mode */
386 DAC_CTL &= ~DAC_CTL_DWBW0;
387 DAC_CTL |= unmask_bits;
388 } else {
389 /* configure DAC1 LFSR noise mode */
390 DAC_CTL &= ~DAC_CTL_DWBW1;
391 DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET);
392 }
393 }
394
395 /*!
396 \brief configure DAC triangle noise mode
397 \param[in] dac_periph: DACx(x = 0,1)
398 \param[in] amplitude: triangle amplitude in DAC triangle noise mode
399 only one parameter can be selected which is shown as below:
400 \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
401 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
402 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
403 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
404 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
405 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
406 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
407 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
408 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
409 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
410 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
411 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
412 \param[out] none
413 \retval none
414 */
dac_triangle_noise_config(uint32_t dac_periph,uint32_t amplitude)415 void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude)
416 {
417 if(DAC0 == dac_periph) {
418 /* configure DAC0 triangle noise mode */
419 DAC_CTL &= ~DAC_CTL_DWBW0;
420 DAC_CTL |= amplitude;
421 } else {
422 /* configure DAC1 triangle noise mode */
423 DAC_CTL &= ~DAC_CTL_DWBW1;
424 DAC_CTL |= (amplitude << DAC1_REG_OFFSET);
425 }
426 }
427
428 /*!
429 \brief enable DAC concurrent mode
430 \param[in] none
431 \param[out] none
432 \retval none
433 */
dac_concurrent_enable(void)434 void dac_concurrent_enable(void)
435 {
436 uint32_t ctl = 0U;
437 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
438 DAC_CTL |= (ctl);
439 }
440
441 /*!
442 \brief disable DAC concurrent mode
443 \param[in] none
444 \param[out] none
445 \retval none
446 */
dac_concurrent_disable(void)447 void dac_concurrent_disable(void)
448 {
449 uint32_t ctl = 0U;
450 ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1;
451 DAC_CTL &= (~ctl);
452 }
453
454 /*!
455 \brief enable DAC concurrent software trigger function
456 \param[in] none
457 \param[out] none
458 \retval none
459 */
dac_concurrent_software_trigger_enable(void)460 void dac_concurrent_software_trigger_enable(void)
461 {
462 uint32_t swt = 0U;
463 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
464 DAC_SWT |= (swt);
465 }
466
467 /*!
468 \brief disable DAC concurrent software trigger function
469 \param[in] none
470 \param[out] none
471 \retval none
472 */
dac_concurrent_software_trigger_disable(void)473 void dac_concurrent_software_trigger_disable(void)
474 {
475 uint32_t swt = 0U;
476 swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1;
477 DAC_SWT &= (~swt);
478 }
479
480 /*!
481 \brief enable DAC concurrent buffer function
482 \param[in] none
483 \param[out] none
484 \retval none
485 */
dac_concurrent_output_buffer_enable(void)486 void dac_concurrent_output_buffer_enable(void)
487 {
488 uint32_t ctl = 0U;
489 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
490 DAC_CTL &= (~ctl);
491 }
492
493 /*!
494 \brief disable DAC concurrent buffer function
495 \param[in] none
496 \param[out] none
497 \retval none
498 */
dac_concurrent_output_buffer_disable(void)499 void dac_concurrent_output_buffer_disable(void)
500 {
501 uint32_t ctl = 0U;
502 ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1;
503 DAC_CTL |= (ctl);
504 }
505
506 /*!
507 \brief set DAC concurrent mode data holding register value
508 \param[in] dac_align: data alignment
509 only one parameter can be selected which is shown as below:
510 \arg DAC_ALIGN_8B_R: data right 8b alignment
511 \arg DAC_ALIGN_12B_R: data right 12b alignment
512 \arg DAC_ALIGN_12B_L: data left 12b alignment
513 \param[in] data0: data to be loaded
514 \param[in] data1: data to be loaded
515 \param[out] none
516 \retval none
517 */
dac_concurrent_data_set(uint32_t dac_align,uint16_t data0,uint16_t data1)518 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
519 {
520 uint32_t data = 0U;
521 switch(dac_align) {
522 /* data right 12b alignment */
523 case DAC_ALIGN_12B_R:
524 data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
525 DACC_R12DH = data;
526 break;
527 /* data left 12b alignment */
528 case DAC_ALIGN_12B_L:
529 data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0;
530 DACC_L12DH = data;
531 break;
532 /* data right 8b alignment */
533 case DAC_ALIGN_8B_R:
534 data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0;
535 DACC_R8DH = data;
536 break;
537 default:
538 break;
539 }
540 }
541
542 /*!
543 \brief enable DAC concurrent interrupt funcution
544 \param[in] none
545 \param[out] none
546 \retval none
547 */
dac_concurrent_interrupt_enable(void)548 void dac_concurrent_interrupt_enable(void)
549 {
550 uint32_t ctl = 0U;
551 ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1;
552 DAC_CTL |= (ctl);
553 }
554
555 /*!
556 \brief disable DAC concurrent interrupt funcution
557 \param[in] none
558 \param[out] none
559 \retval none
560 */
dac_concurrent_interrupt_disable(void)561 void dac_concurrent_interrupt_disable(void)
562 {
563 uint32_t ctl = 0U;
564 ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1;
565 DAC_CTL &= (~ctl);
566 }
567
568 /*!
569 \brief get the specified DAC flag (DAC DMA underrun flag)
570 \param[in] dac_periph: DACx(x = 0,1)
571 \param[out] none
572 \retval FlagStatus: SET or RESET
573 */
dac_flag_get(uint32_t dac_periph)574 FlagStatus dac_flag_get(uint32_t dac_periph)
575 {
576 FlagStatus temp_flag = RESET;
577 if(DAC0 == dac_periph) {
578 /* check the DMA underrun flag */
579 if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)) {
580 temp_flag = SET;
581 }
582 } else {
583 /* check the DMA underrun flag */
584 if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)) {
585 temp_flag = SET;
586 }
587 }
588 return temp_flag;
589 }
590
591 /*!
592 \brief clear the specified DAC flag (DAC DMA underrun flag)
593 \param[in] dac_periph: DACx(x = 0,1)
594 \param[out] none
595 \retval none
596 */
dac_flag_clear(uint32_t dac_periph)597 void dac_flag_clear(uint32_t dac_periph)
598 {
599 if(DAC0 == dac_periph) {
600 DAC_STAT |= DAC_STAT_DDUDR0;
601 } else {
602 DAC_STAT |= DAC_STAT_DDUDR1;
603 }
604 }
605
606 /*!
607 \brief enable DAC interrupt(DAC DMA underrun interrupt)
608 \param[in] dac_periph: DACx(x = 0,1)
609 \param[out] none
610 \retval none
611 */
dac_interrupt_enable(uint32_t dac_periph)612 void dac_interrupt_enable(uint32_t dac_periph)
613 {
614 if(DAC0 == dac_periph) {
615 DAC_CTL |= DAC_CTL_DDUDRIE0;
616 } else {
617 DAC_CTL |= DAC_CTL_DDUDRIE1;
618 }
619 }
620
621 /*!
622 \brief disable DAC interrupt(DAC DMA underrun interrupt)
623 \param[in] dac_periph: DACx(x = 0,1)
624 \param[out] none
625 \retval none
626 */
dac_interrupt_disable(uint32_t dac_periph)627 void dac_interrupt_disable(uint32_t dac_periph)
628 {
629 if(DAC0 == dac_periph) {
630 DAC_CTL &= ~DAC_CTL_DDUDRIE0;
631 } else {
632 DAC_CTL &= ~DAC_CTL_DDUDRIE1;
633 }
634 }
635
636 /*!
637 \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag)
638 \param[in] dac_periph: DACx(x = 0,1)
639 \param[out] none
640 \retval FlagStatus: SET or RESET
641 */
dac_interrupt_flag_get(uint32_t dac_periph)642 FlagStatus dac_interrupt_flag_get(uint32_t dac_periph)
643 {
644 FlagStatus temp_flag = RESET;
645 uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
646
647 if(DAC0 == dac_periph) {
648 /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
649 ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0;
650 ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0;
651 if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) {
652 temp_flag = SET;
653 }
654 } else {
655 /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
656 ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1;
657 ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1;
658 if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) {
659 temp_flag = SET;
660 }
661 }
662 return temp_flag;
663 }
664
665 /*!
666 \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag)
667 \param[in] dac_periph: DACx(x = 0,1)
668 \param[out] none
669 \retval none
670 */
dac_interrupt_flag_clear(uint32_t dac_periph)671 void dac_interrupt_flag_clear(uint32_t dac_periph)
672 {
673 if(DAC0 == dac_periph) {
674 DAC_STAT |= DAC_STAT_DDUDR0;
675 } else {
676 DAC_STAT |= DAC_STAT_DDUDR1;
677 }
678 }
679
