1 /* 2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 typedef volatile struct sens_dev_s { 15 union { 16 struct { 17 uint32_t sar1_clk_div: 8; /*clock divider*/ 18 uint32_t reserved8: 10; 19 uint32_t sar1_clk_gated: 1; 20 uint32_t sar1_sample_num: 8; 21 uint32_t reserved27: 1; 22 uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ 23 uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/ 24 uint32_t reserved30: 2; 25 }; 26 uint32_t val; 27 } sar_reader1_ctrl; 28 uint32_t sar_reader1_status; /**/ 29 union { 30 struct { 31 uint32_t reserved0: 22; 32 uint32_t rtc_saradc_reset: 1; 33 uint32_t rtc_saradc_clkgate_en: 1; 34 uint32_t force_xpd_amp: 2; 35 uint32_t amp_rst_fb_force: 2; 36 uint32_t amp_short_ref_force: 2; 37 uint32_t amp_short_ref_gnd_force: 2; 38 }; 39 uint32_t val; 40 } sar_meas1_ctrl1; 41 union { 42 struct { 43 uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ 44 uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ 45 uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/ 46 uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/ 47 uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/ 48 uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/ 49 }; 50 uint32_t val; 51 } sar_meas1_ctrl2; 52 union { 53 struct { 54 uint32_t reserved0: 31; 55 uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ 56 }; 57 uint32_t val; 58 } sar_meas1_mux; 59 uint32_t sar_atten1; /*2-bit attenuation for each pad*/ 60 union { 61 struct { 62 uint32_t sar_amp_wait1:16; 63 uint32_t sar_amp_wait2:16; 64 }; 65 uint32_t val; 66 } sar_amp_ctrl1; 67 union { 68 struct { 69 uint32_t sar1_dac_xpd_fsm_idle: 1; 70 uint32_t xpd_sar_amp_fsm_idle: 1; 71 uint32_t amp_rst_fb_fsm_idle: 1; 72 uint32_t amp_short_ref_fsm_idle: 1; 73 uint32_t amp_short_ref_gnd_fsm_idle: 1; 74 uint32_t xpd_sar_fsm_idle: 1; 75 uint32_t sar_rstb_fsm_idle: 1; 76 uint32_t reserved7: 9; 77 uint32_t sar_amp_wait3: 16; 78 }; 79 uint32_t val; 80 } sar_amp_ctrl2; 81 union { 82 struct { 83 uint32_t sar1_dac_xpd_fsm: 4; 84 uint32_t xpd_sar_amp_fsm: 4; 85 uint32_t amp_rst_fb_fsm: 4; 86 uint32_t amp_short_ref_fsm: 4; 87 uint32_t amp_short_ref_gnd_fsm: 4; 88 uint32_t xpd_sar_fsm: 4; 89 uint32_t sar_rstb_fsm: 4; 90 uint32_t reserved28: 4; 91 }; 92 uint32_t val; 93 } sar_amp_ctrl3; 94 union { 95 struct { 96 uint32_t sar2_clk_div: 8; /*clock divider*/ 97 uint32_t reserved8: 8; 98 uint32_t sar2_wait_arb_cycle: 2; /*wait arbit stable after sar_done*/ 99 uint32_t sar2_clk_gated: 1; 100 uint32_t sar2_sample_num: 8; 101 uint32_t reserved27: 2; 102 uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ 103 uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/ 104 uint32_t reserved31: 1; 105 }; 106 uint32_t val; 107 } sar_reader2_ctrl; 108 uint32_t sar_reader2_status; /**/ 109 union { 110 struct { 111 uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/ 112 uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ 113 uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/ 114 uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/ 115 uint32_t sar2_rstb_force: 2; 116 uint32_t sar2_standby_wait: 8; 117 uint32_t sar2_rstb_wait: 8; 118 uint32_t sar2_xpd_wait: 8; 119 }; 120 uint32_t val; 121 } sar_meas2_ctrl1; 122 union { 123 struct { 124 uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ 125 uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ 126 uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/ 127 uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/ 128 uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/ 129 uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/ 130 }; 131 uint32_t val; 132 } sar_meas2_ctrl2; 133 union { 134 struct { 135 uint32_t reserved0: 28; 136 uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ 137 uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/ 138 }; 139 uint32_t val; 140 } sar_meas2_mux; 141 uint32_t sar_atten2; /*2-bit attenuation for each pad*/ 142 union { 143 struct { 144 uint32_t reserved0: 29; 145 uint32_t force_xpd_sar: 2; 146 uint32_t sarclk_en: 1; 147 }; 148 uint32_t val; 149 } sar_power_xpd_sar; 150 union { 151 struct { 152 uint32_t i2c_slave_addr1: 11; 153 uint32_t i2c_slave_addr0: 11; 154 uint32_t meas_status: 8; 155 uint32_t reserved30: 2; 156 }; 157 uint32_t val; 158 } sar_slave_addr1; 159 union { 160 struct { 161 uint32_t i2c_slave_addr3:11; 162 uint32_t i2c_slave_addr2:11; 163 uint32_t reserved22: 10; 164 }; 165 uint32_t val; 166 } sar_slave_addr2; 167 union { 168 struct { 169 uint32_t i2c_slave_addr5:11; 170 uint32_t i2c_slave_addr4:11; 171 uint32_t reserved22: 10; 172 }; 173 uint32_t val; 174 } sar_slave_addr3; 175 union { 176 struct { 177 uint32_t i2c_slave_addr7:11; 178 uint32_t i2c_slave_addr6:11; 179 uint32_t reserved22: 10; 180 }; 181 uint32_t val; 182 } sar_slave_addr4; 183 union { 184 struct { 185 uint32_t tsens_out: 8; /*temperature sensor data out*/ 186 uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ 187 uint32_t reserved9: 3; 188 uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/ 189 uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ 190 uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ 191 uint32_t tsens_power_up: 1; /*temperature sensor power up*/ 192 uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/ 193 uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/ 194 uint32_t reserved25: 7; 195 }; 196 uint32_t val; 197 } sar_tctrl; 198 union { 199 struct { 200 uint32_t tsens_xpd_wait: 12; 201 uint32_t tsens_xpd_force: 2; 202 uint32_t tsens_clk_inv: 1; 203 uint32_t tsens_clkgate_en: 1; /*temperature sensor clock enable*/ 204 uint32_t tsens_reset: 1; /*temperature sensor reset*/ 205 uint32_t reserved17: 15; 206 }; 207 uint32_t val; 208 } sar_tctrl2; 209 union { 210 struct { 211 uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ 212 uint32_t sar_i2c_start: 1; /*start I2C*/ 213 uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/ 214 uint32_t reserved30: 2; 215 }; 216 uint32_t val; 217 } sar_i2c_ctrl; 218 union { 219 struct { 220 uint32_t touch_outen: 15; /*touch controller output enable*/ 221 uint32_t touch_status_clr: 1; /*clear all touch active status*/ 222 uint32_t touch_data_sel: 2; /*3: smooth data 2: benchmark 1 0: raw_data*/ 223 uint32_t touch_denoise_end: 1; /*touch_denoise_done*/ 224 uint32_t touch_unit_end: 1; /*touch_unit_done*/ 225 uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ 226 uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/ 227 uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/ 228 }; 229 uint32_t val; 230 } sar_touch_conf; 231 union { 232 struct { 233 uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ 234 uint32_t reserved22: 10; 235 }; 236 uint32_t val; 237 } touch_thresh[14]; 238 uint32_t reserved_98; 239 uint32_t reserved_9c; 240 uint32_t reserved_a0; 241 uint32_t reserved_a4; 242 uint32_t reserved_a8; 243 uint32_t reserved_ac; 244 uint32_t reserved_b0; 245 uint32_t reserved_b4; 246 uint32_t reserved_b8; 247 uint32_t reserved_bc; 248 uint32_t reserved_c0; 249 uint32_t reserved_c4; 250 uint32_t reserved_c8; 251 uint32_t reserved_cc; 252 uint32_t reserved_d0; 253 union { 254 struct { 255 uint32_t touch_pad_active: 15; /*touch active status*/ 256 uint32_t touch_channel_clr:15; /*Clear touch channel*/ 257 uint32_t reserved30: 1; 258 uint32_t touch_meas_done: 1; 259 }; 260 uint32_t val; 261 } sar_touch_chn_st; 262 union { 263 struct { 264 uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/ 265 uint32_t touch_scan_curr: 4; 266 uint32_t reserved26: 6; 267 }; 268 uint32_t val; 269 } sar_touch_status0; 270 union { 271 struct { 272 uint32_t touch_pad_data: 22; 273 uint32_t reserved22: 7; 274 uint32_t touch_pad_debounce: 3; 275 }; 276 uint32_t val; 277 } sar_touch_status[14]; 278 union { 279 struct { 280 uint32_t touch_slp_data: 22; 281 uint32_t reserved22: 7; 282 uint32_t touch_slp_debounce: 3; 283 }; 284 uint32_t val; 285 } sar_touch_slp_status; 286 union { 287 struct { 288 uint32_t touch_approach_pad2_cnt: 8; 289 uint32_t touch_approach_pad1_cnt: 8; 290 uint32_t touch_approach_pad0_cnt: 8; 291 uint32_t touch_slp_approach_cnt: 8; 292 }; 293 uint32_t val; 294 } sar_touch_appr_status; 295 union { 296 struct { 297 uint32_t sw_fstep: 16; /*frequency step for CW generator*/ 298 uint32_t sw_tone_en: 1; /*1: enable CW generator*/ 299 uint32_t debug_bit_sel: 5; 300 uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/ 301 uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ 302 uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ 303 uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ 304 uint32_t dac_reset: 1; 305 uint32_t dac_clkgate_en: 1; 306 uint32_t reserved28: 4; 307 }; 308 uint32_t val; 309 } sar_dac_ctrl1; 310 union { 311 struct { 312 uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ 313 uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ 314 uint32_t dac_scale1: 2; /*00: no scale*/ 315 uint32_t dac_scale2: 2; /*00: no scale*/ 316 uint32_t dac_inv1: 2; /*00: do not invert any bits*/ 317 uint32_t dac_inv2: 2; /*00: do not invert any bits*/ 318 uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/ 319 uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/ 320 uint32_t reserved26: 6; 321 }; 322 uint32_t val; 323 } sar_dac_ctrl2; 324 union { 325 struct { 326 uint32_t reserved0: 25; 327 uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ 328 uint32_t clk_en: 1; /*check cocpu whether clk on*/ 329 uint32_t reset_n: 1; /*check cocpu whether in reset state*/ 330 uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ 331 uint32_t trap: 1; /*check cocpu whether in trap state*/ 332 uint32_t ebreak: 1; /*check cocpu whether in ebreak*/ 333 uint32_t reserved31: 1; 334 }; 335 uint32_t val; 336 } sar_cocpu_state; 337 union { 338 struct { 339 uint32_t touch_done: 1; /*int from touch done*/ 340 uint32_t touch_inactive: 1; /*int from touch inactive*/ 341 uint32_t touch_active: 1; /*int from touch active*/ 342 uint32_t saradc1: 1; /*int from saradc1*/ 343 uint32_t saradc2: 1; /*int from saradc2*/ 344 uint32_t tsens: 1; /*int from tsens*/ 345 uint32_t start: 1; /*int from start*/ 346 uint32_t sw: 1; /*int from software*/ 347 uint32_t swd: 1; /*int from super watch dog*/ 348 uint32_t reserved9: 23; 349 }; 350 uint32_t val; 351 } sar_cocpu_int_raw; 352 union { 353 struct { 354 uint32_t touch_done: 1; 355 uint32_t touch_inactive: 1; 356 uint32_t touch_active: 1; 357 uint32_t saradc1: 1; 358 uint32_t saradc2: 1; 359 uint32_t tsens: 1; 360 uint32_t start: 1; 361 uint32_t sw: 1; /*cocpu int enable*/ 362 uint32_t swd: 1; 363 uint32_t reserved9: 23; 364 }; 365 uint32_t val; 366 } sar_cocpu_int_ena; 367 union { 368 struct { 369 uint32_t touch_done: 1; 370 uint32_t touch_inactive: 1; 371 uint32_t touch_active: 1; 372 uint32_t saradc1: 1; 373 uint32_t saradc2: 1; 374 uint32_t tsens: 1; 375 uint32_t start: 1; 376 uint32_t sw: 1; /*cocpu int status*/ 377 uint32_t swd: 1; 378 uint32_t reserved9: 23; 379 }; 380 uint32_t val; 381 } sar_cocpu_int_st; 382 union { 383 struct { 384 uint32_t touch_done: 1; 385 uint32_t touch_inactive: 1; 386 uint32_t touch_active: 1; 387 uint32_t saradc1: 1; 388 uint32_t saradc2: 1; 389 uint32_t tsens: 1; 390 uint32_t start: 1; 391 uint32_t sw: 1; /*cocpu int clear*/ 392 uint32_t swd: 1; 393 uint32_t reserved9: 23; 394 }; 395 uint32_t val; 396 } sar_cocpu_int_clr; 397 union { 398 struct { 399 uint32_t pc: 13; /*cocpu Program counter*/ 400 uint32_t mem_vld: 1; /*cocpu mem valid output*/ 401 uint32_t mem_rdy: 1; /*cocpu mem ready input*/ 402 uint32_t mem_wen: 4; /*cocpu mem write enable output*/ 403 uint32_t mem_addr: 13; /*cocpu mem address output*/ 404 }; 405 uint32_t val; 406 } sar_cocpu_debug; 407 union { 408 struct { 409 uint32_t reserved0: 28; 410 uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ 411 uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ 412 uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ 413 uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ 414 }; 415 uint32_t val; 416 } sar_hall_ctrl; 417 uint32_t sar_nouse; /**/ 418 union { 419 struct { 420 uint32_t reserved0: 30; 421 uint32_t iomux_reset: 1; 422 uint32_t iomux_clk_gate_en: 1; 423 }; 424 uint32_t val; 425 } sar_io_mux_conf; 426 union { 427 struct { 428 uint32_t sar_date: 28; 429 uint32_t reserved28: 4; 430 }; 431 uint32_t val; 432 } sardate; 433 } sens_dev_t; 434 extern sens_dev_t SENS; 435 #ifdef __cplusplus 436 } 437 #endif 438
