1 /***************************************************************************//**
2 * \file cyhal_system.c
3 *
4 * \brief
5 * Provides a high level interface for interacting with the Infineon power
6 * management and system clock configuration. This interface abstracts out the
7 * chip specific details. If any chip specific functionality is necessary, or
8 * performance is critical the low level functions can be used directly.
9 *
10 ********************************************************************************
11 * \copyright
12 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
13 * an affiliate of Cypress Semiconductor Corporation
14 *
15 * SPDX-License-Identifier: Apache-2.0
16 *
17 * Licensed under the Apache License, Version 2.0 (the "License");
18 * you may not use this file except in compliance with the License.
19 * You may obtain a copy of the License at
20 *
21 * http://www.apache.org/licenses/LICENSE-2.0
22 *
23 * Unless required by applicable law or agreed to in writing, software
24 * distributed under the License is distributed on an "AS IS" BASIS,
25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26 * See the License for the specific language governing permissions and
27 * limitations under the License.
28 *******************************************************************************/
29
30 #include "cyhal_system.h"
31
32 #if (defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D))
33 #include "cy_syslib.h"
34 #endif
35
36 #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)
37 #include "cyabs_rtos.h"
38 #endif
39
40 #if (CYHAL_DRIVER_AVAILABLE_SYSTEM)
41
42 #if defined(__cplusplus)
43 extern "C"
44 {
45 #endif
46
47 #define _CYHAL_SYSTEM_HZ_PER_MHZ 1000000
48
49 #if (defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)) &&\
50 !defined(CYHAL_DISABLE_WEAK_FUNC_IMPL)
51 /* Overrides weak implemenation for Cy_SysLib_Rtos_Delay to provide a way
52 * to call into a RTOS if so configured. This function is only available
53 * in mtb-pdl-cat1 version 2.2.0 or later.
54 */
Cy_SysLib_Rtos_Delay(uint32_t milliseconds)55 void Cy_SysLib_Rtos_Delay(uint32_t milliseconds)
56 {
57 cy_rslt_t result = cyhal_system_delay_ms(milliseconds);
58 CY_ASSERT(CY_RSLT_SUCCESS == result);
59 CY_UNUSED_PARAMETER(result);
60 }
61 #endif
62
cyhal_system_delay_ms(uint32_t milliseconds)63 cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds)
64 {
65 #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)
66 // The RTOS is configured to round down, while this API is intended to wait at least the
67 // requested time. Add 1 to the requested time to make it behave the same.
68 return cy_rtos_delay_milliseconds(milliseconds + 1);
69 #else
70 Cy_SysLib_Delay(milliseconds);
71 return CY_RSLT_SUCCESS;
72 #endif
73 }
74
cyhal_system_get_reset_reason(void)75 cyhal_reset_reason_t cyhal_system_get_reset_reason(void)
76 {
77 uint32_t pdl_reason = Cy_SysLib_GetResetReason();
78 cyhal_reset_reason_t reason = CYHAL_SYSTEM_RESET_NONE;
79
80 if (CY_SYSLIB_RESET_SOFT & pdl_reason)
81 reason |= CYHAL_SYSTEM_RESET_SOFT;
82 if (CY_SYSLIB_RESET_HWWDT & pdl_reason)
83 reason |= CYHAL_SYSTEM_RESET_WDT;
84 #if defined(CY_IP_S8SRSSLT)
85 if (CY_SYSLIB_PROT_FAULT & pdl_reason)
86 reason |= CYHAL_SYSTEM_RESET_PROTECTION;
87 #endif
88 #if defined(CY_IP_MXS40SRSS) || defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS22SSRSS)
89 if (CY_SYSLIB_RESET_ACT_FAULT & pdl_reason)
90 reason |= CYHAL_SYSTEM_RESET_ACTIVE_FAULT;
91 if (CY_SYSLIB_RESET_DPSLP_FAULT & pdl_reason)
92 reason |= CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT;
93 if (CY_SYSLIB_RESET_HIB_WAKEUP & pdl_reason)
94 reason |= CYHAL_SYSTEM_RESET_HIB_WAKEUP;
95 if (CY_SYSLIB_RESET_CSV_LOSS_WAKEUP & pdl_reason)
96 reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR;
97 if (CY_SYSLIB_RESET_CSV_ERROR_WAKEUP & pdl_reason)
98 reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR;
99 if ((CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT3) & pdl_reason)
100 reason |= CYHAL_SYSTEM_RESET_WDT;
101 #endif
102 #if (SRSS_WCOCSV_PRESENT != 0U)
103 if (CY_SYSLIB_RESET_CSV_WCO_LOSS & pdl_reason)
104 reason |= CYHAL_SYSTEM_RESET_WCO_ERR;
105 #endif
106 #if (SRSS_MASK_HFCSV != 0U)
107 if ((CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_HFCLK_ERR) & pdl_reason)
108 reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR;
109 #endif
110
111 #if defined(CY_IP_MXS40SSRSS)
112 if ((reason == CYHAL_SYSTEM_RESET_NONE) && Cy_SysLib_IsDSRAMWarmBootEntry())
113 reason |= CYHAL_SYSTEM_RESET_WARMBOOT;
114 #endif
115
116 return reason;
117 }
118
cyhal_system_set_isr(int32_t irq_num,int32_t irq_src,uint8_t priority,cyhal_irq_handler handler)119 cy_rslt_t cyhal_system_set_isr(int32_t irq_num, int32_t irq_src, uint8_t priority, cyhal_irq_handler handler)
120 {
121 CY_UNUSED_PARAMETER(irq_src); // Not used by most configurations as there is a 1:1 mapping from irq_src to irq_num
122 cy_stc_sysint_t cfg =
123 {
124 #if defined (CY_IP_M7CPUSS)
125 .intrSrc = (uint32_t)irq_src | ((uint32_t)irq_num << 16),
126 #else
127 .intrSrc = (IRQn_Type)irq_num,
128 #endif
129 .intrPriority = priority,
130 #if (CY_CPU_CORTEX_M0P) && defined (CY_IP_M4CPUSS)
131 .cm0pSrc = (cy_en_intr_t)irq_src,
132 #endif
133 };
134 return Cy_SysInt_Init(&cfg, (cy_israddress)handler);
135 }
136
137 #if defined(__cplusplus)
138 }
139 #endif
140
141 #endif /* CYHAL_DRIVER_AVAILABLE_SYSTEM */
142
