1 /***************************************************************************//** 2 * \file cyhal_system_impl.h 3 * 4 * \brief 5 * Provides a PSoC™ Specific interface for interacting with the Infineon power 6 * management and system clock configuration. This interface abstracts out the 7 * chip specific details. If any chip specific functionality is necessary, or 8 * performance is critical the low level functions can be used directly. 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation 14 * 15 * SPDX-License-Identifier: Apache-2.0 16 * 17 * Licensed under the Apache License, Version 2.0 (the "License"); 18 * you may not use this file except in compliance with the License. 19 * You may obtain a copy of the License at 20 * 21 * http://www.apache.org/licenses/LICENSE-2.0 22 * 23 * Unless required by applicable law or agreed to in writing, software 24 * distributed under the License is distributed on an "AS IS" BASIS, 25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 * See the License for the specific language governing permissions and 27 * limitations under the License. 28 *******************************************************************************/ 29 30 #pragma once 31 32 #include "cyhal_system.h" 33 34 #if defined(CY_IP_MXS40SRSS) || defined(CY_IP_S8SRSSLT) || defined(CY_IP_MXS28SRSS) || defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS22SRSS) 35 36 #define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection() 37 38 #define cyhal_system_critical_section_exit(x) Cy_SysLib_ExitCriticalSection(x) 39 40 #define cyhal_system_delay_us(microseconds) Cy_SysLib_DelayUs(microseconds) 41 42 #define cyhal_system_clear_reset_reason() Cy_SysLib_ClearResetReason() 43 44 #endif /* defined(CY_IP_MXS40SRSS) || defined(CY_IP_S8SRSSLT) || defined(CY_IP_MXS28SRSS) || defined(CY_IP_MXS40SSRSS) */ 45
