1 /***************************************************************************//** 2 * \file cyhal_hw_types.h 3 * 4 * \brief 5 * Provides a struct definitions for configuration resources in the PDL. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_hal_impl CAT1 Implementation Specific 29 * \{ 30 * This section provides details about the CAT1 implementation of the Cypress HAL. 31 * All information within this section is platform specific and is provided for reference. 32 * Portable application code should depend only on the APIs and types which are documented 33 * in the @ref group_hal section. 34 * 35 * \section group_hal_impl_mapping HAL Resource Hardware Mapping 36 * The following table shows a mapping of each HAL driver to the lower level firmware driver 37 * and the corresponding hardware resource. This is intended to help understand how the HAL 38 * is implemented for CAT1 and what features the underlying hardware supports. 39 * 40 * | HAL Resource | PDL Driver(s) | CAT1 Hardware | 41 * | ------------------ | ------------------- | -------------------------------- | 42 * | ADC | cy_adc | SAR ADC | 43 * | Clock | cy_sysclk | All clocks (system & peripheral) | 44 * | Comparator | cy_ctb or cy_lpcomp | CTBm or LPComp | 45 * | CRC | cy_crypto_core_crc | Crypto | 46 * | DAC | cy_ctdac | DAC | 47 * | DMA | cy_dma, cy_dmac | DMA Controller | 48 * | EZ-I2C | cy_scb_ezi2c | SCB | 49 * | Flash | cy_flash | Flash | 50 * | GPIO | cy_gpio | GPIO | 51 * | Hardware Manager | NA | NA | 52 * | I2C | cy_scb_i2c | SCB | 53 * | I2S | cy_i2s | I2S | 54 * | LPTimer | cy_mcwdt | MCWDT | 55 * | Opamp | cy_ctb | CTBm | 56 * | PDM/PCM | cy_pdm_pcm | PDM-PCM | 57 * | PWM | cy_pwm | TCPWM | 58 * | QSPI | cy_smif | QSPI (SMIF) | 59 * | Quadrature Decoder | cy_tcpwm_quaddec | TCPWM | 60 * | RTC | cy_rtc | RTC | 61 * | SDHC | cy_sd_host | SD Host | 62 * | SDIO | cy_sd_host, or NA | SD Host, or UDB | 63 * | SPI | cy_scb_spi | SCB | 64 * | SysPM | cy_syspm | System Power Resources | 65 * | System | cy_syslib | System Resources | 66 * | TDM | cy_i2s | I2S | 67 * | Timer | cy_tcpwm_counter | TCPWM | 68 * | TRNG | cy_crypto_core_trng | Crypto | 69 * | UART | cy_scb_uart | SCB | 70 * | USB Device | cy_usbfs_dev_drv | USB-FS | 71 * | WDT | cy_wdt | WDT | 72 * 73 * \section group_hal_impl_errors Device Specific Errors 74 * Error codes generated by the low level level PDL driver all use module IDs starting 75 * with \ref CY_RSLT_MODULE_DRIVERS_PDL_BASE. The exact errors are documented for each 76 * driver in the 77 * <a href="https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html"> 78 * mtb-pdl-cat1 documentation</a>. 79 */ 80 81 /** 82 * \addtogroup group_hal_impl_hw_types CAT1 Specific Hardware Types 83 * \{ 84 * Aliases for types which are part of the public HAL interface but whose representations 85 * need to vary per HAL implementation 86 */ 87 88 #pragma once 89 90 #include "cy_pdl.h" 91 #include "cyhal_general_types.h" 92 #include "cyhal_hw_resources.h" 93 #include "cyhal_pin_package.h" 94 #include "cyhal_triggers.h" 95 #include <stdbool.h> 96 97 #if defined(CYHAL_UDB_SDIO) 98 #include "SDIO_HOST.h" 99 #endif 100 101 #ifdef __cplusplus 102 extern "C" { 103 #endif 104 105 #if defined(COMPONENT_CAT1D) 106 #define CYHAL_TRIGGER_CPUSS_ZERO CYHAL_TRIGGER_M33SYSCPUSS_ZERO 107 #endif 108 109 #ifndef CYHAL_ISR_PRIORITY_DEFAULT 110 /** Priority that is applied by default to all drivers when initialized. Priorities can be 111 * overridden on each driver as part of enabling events. 112 */ 113 #if (CORE == CM0P) 114 #define CYHAL_ISR_PRIORITY_DEFAULT (3) 115 #else // (CORE == CM0P) 116 #define CYHAL_ISR_PRIORITY_DEFAULT (7) 117 #endif // (CORE == CM0P) 118 #endif 119 120 /** 121 * \cond INTERNAL 122 */ 123 124 #define CYHAL_ADC_IMPL_HEADER "cyhal_adc_impl.h" //!< Implementation specific header for ADC 125 #define CYHAL_DMA_IMPL_HEADER "cyhal_dma_impl.h" //!< Implementation specific header for DMA 126 #define CYHAL_CLOCK_IMPL_HEADER "cyhal_clock_impl.h" //!< Implementation specific header for Clocks 127 #define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO 128 #define CYHAL_PDMPCM_IMPL_HEADER "cyhal_pdmpcm_impl.h" //!< Implementation specific header for PDMPCM 129 #define CYHAL_I2S_IMPL_HEADER "cyhal_i2s_impl.h" //!< Implementation specific header for I2S 130 #define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM 131 #define CYHAL_QUADDEC_IMPL_HEADER "cyhal_quaddec_impl.h" //!< Implementation specific header for QUADDEC 132 #define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System 133 #define CYHAL_SYSPM_IMPL_HEADER "cyhal_syspm_impl.h" //!< Implementation specific header for System Power Management 134 #define CYHAL_TDM_IMPL_HEADER "cyhal_tdm_impl.h" //!< Implementation specific header for TDM 135 #define CYHAL_TIMER_IMPL_HEADER "cyhal_timer_impl.h" //!< Implementation specific header for Timer 136 #define CYHAL_INTERCONNECT_IMPL_HEADER "cyhal_interconnect_impl.h" //!< Implementation specific header for Interconnect 137 138 #if defined(_CYHAL_DRIVER_AVAILABLE_CRYPTO) 139 #define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC 140 #define CYHAL_TRNG_IMPL_HEADER "cyhal_trng_impl.h" //!< Implementation specific header for TRNG 141 #endif 142 143 #if defined(CYHAL_DRIVER_AVAILABLE_IPC) 144 #define CYHAL_IPC_IMPL_HEADER "cyhal_ipc_impl.h" //!< Implementation specific header for IPC 145 #endif 146 147 //TODO REMOVE this once PDL provides the missing items 148 #if defined(COMPONENT_CAT1B) 149 #include "cyhal_missing_pdl.h" 150 #endif 151 152 /** \endcond */ 153 154 /** Callbacks for Sleep and Deepsleep APIs */ 155 #define cyhal_system_callback_t cy_stc_syspm_callback_t 156 157 /** @brief Event callback data object */ 158 typedef struct { 159 cy_israddress callback; 160 void* callback_arg; 161 } cyhal_event_callback_data_t; 162 163 /** 164 * @brief Store information about buffer 165 * 166 * Application code should not rely on the specific contents of this struct. 167 * They are considered an implementation detail which is subject to change 168 * between platforms and/or HAL releases. 169 */ 170 typedef struct { 171 union 172 { 173 void *v; 174 uint8_t *u8; 175 uint16_t *u16; 176 uint32_t *u32; 177 } addr; 178 uint32_t size; 179 } _cyhal_buffer_info_t; 180 181 /** 182 * @brief Shared data between timer/counter and PWM 183 * 184 * Application code should not rely on the specific content of this struct. 185 * They are considered an implementation detail which is subject to change 186 * between platforms and/or HAL releases. 187 */ 188 typedef struct { 189 #ifdef CY_IP_MXTCPWM 190 bool owned_by_configurator; 191 bool presleep_state; 192 TCPWM_Type* base; 193 cyhal_resource_inst_t resource; 194 cyhal_clock_t clock; 195 bool dedicated_clock; 196 uint32_t clock_hz; 197 cyhal_event_callback_data_t callback_data; 198 /* Bits to clear from the interrupt mask during the next ISR */ 199 uint32_t clear_intr_mask; 200 #if defined(CY_IP_MXPERI_TR) || defined(CY_IP_MXSPERI) 201 cyhal_source_t inputs[5]; 202 #endif 203 #else 204 void *empty; 205 #endif 206 } cyhal_tcpwm_t; 207 208 /* This is presented out of order because many other structs depend on it */ 209 /** 210 * @brief DMA object 211 * 212 * Application code should not rely on the specific contents of this struct. 213 * They are considered an implementation detail which is subject to change 214 * between platforms and/or HAL releases. 215 */ 216 typedef struct { 217 #if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXAHBDMAC) || defined(CY_IP_MXDW) || defined(CY_IP_MXSAXIDMAC) 218 cyhal_resource_inst_t resource; 219 _CYHAL_DMA_ALIGN union 220 { 221 #if defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXDW) 222 cy_stc_dma_channel_config_t dw; 223 #endif 224 #if defined(CY_IP_MXSAXIDMAC) 225 cy_stc_axidmac_channel_config_t dmac; 226 #elif defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_MXAHBDMAC) 227 cy_stc_dmac_channel_config_t dmac; 228 #endif 229 } channel_config; 230 _CYHAL_DMA_ALIGN union 231 { 232 #if defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXDW) 233 cy_stc_dma_descriptor_config_t dw; 234 #endif 235 #if defined(CY_IP_MXSAXIDMAC) 236 cy_stc_axidmac_descriptor_config_t dmac; 237 #elif defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_MXAHBDMAC) 238 cy_stc_dmac_descriptor_config_t dmac; 239 #endif 240 } descriptor_config; 241 _CYHAL_DMA_ALIGN union 242 { 243 #if defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXDW) 244 cy_stc_dma_descriptor_t dw; 245 #endif 246 #if defined(CY_IP_MXSAXIDMAC) 247 cy_stc_axidmac_descriptor_t dmac; 248 #elif defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_MXAHBDMAC) 249 cy_stc_dmac_descriptor_t dmac; 250 #endif 251 } descriptor; 252 uint16_t expected_bursts; 253 uint32_t/* cyhal_dma_direction_t */ direction; 254 uint32_t irq_cause; 255 cyhal_event_callback_data_t callback_data; 256 cyhal_source_t source; 257 bool owned_by_configurator; 258 #else 259 void *empty; 260 #endif 261 } cyhal_dma_t; 262 263 /** 264 * @brief DMA configurator struct 265 * 266 * This struct allows a configurator to provide block configuration information 267 * to the HAL. Because configurator-generated configurations are platform 268 * specific, the contents of this struct is subject to change between platforms 269 * and/or HAL releases. 270 */ 271 typedef struct 272 { 273 #if CYHAL_DRIVER_AVAILABLE_DMA 274 const cyhal_resource_inst_t* resource; 275 struct 276 { 277 union 278 { 279 #if defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXDW) 280 cy_stc_dma_channel_config_t const* dw_channel_config; 281 #endif 282 #if defined(CY_IP_MXSAXIDMAC) 283 /* AXI DMA controller has a 64-bit AXI master interface */ 284 _CYHAL_DMA_ALIGN cy_stc_axidmac_channel_config_t const* dmac_channel_config; 285 #elif defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_MXAHBDMAC) 286 cy_stc_dmac_channel_config_t const* dmac_channel_config; 287 #endif 288 }; 289 union 290 { 291 #if defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_MXDW) 292 cy_stc_dma_descriptor_config_t const* dw_descriptor_config; 293 #endif 294 #if defined(CY_IP_MXSAXIDMAC) 295 /* AXI DMA controller has a 64-bit AXI master interface */ 296 _CYHAL_DMA_ALIGN cy_stc_axidmac_descriptor_config_t const* dmac_descriptor_config; 297 #elif defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_MXAHBDMAC) 298 cy_stc_dmac_descriptor_config_t const* dmac_descriptor_config; 299 #endif 300 }; 301 }; 302 #else 303 void *empty; 304 #endif /* CYHAL_DRIVER_AVAILABLE_DMA */ 305 } cyhal_dma_configurator_t; 306 307 struct _cyhal_audioss_s; 308 309 /** 310 * @brief Interface to abstract away the driver-specific differences between TDM and I2S 311 * 312 * Application code should not rely on the specific contents of this struct. 313 * They are considered an implementation detail which is subject to change 314 * between platforms and/or HAL releases. 315 */ 316 typedef struct 317 { 318 #if defined(CY_IP_MXAUDIOSS) 319 /** Convert a PDL-level interrupt cause to a HAL-level event */ 320 uint32_t (*convert_interrupt_cause)(uint32_t pdl_event); 321 /** Convert a HAL-level event to a PDL-level interrupt cause */ 322 uint32_t (*convert_to_pdl)(uint32_t hal_event); 323 #elif defined(CY_IP_MXTDM) 324 /** Convert a PDL-level interrupt cause to a HAL-level event */ 325 uint32_t (*convert_interrupt_cause)(uint32_t pdl_event, bool is_tx); 326 /** Convert a HAL-level event to a PDL-level interrupt cause */ 327 uint32_t (*convert_to_pdl)(uint32_t hal_event, bool is_tx); 328 #endif 329 /** Invoke the user callback with the specified HAL event. 330 * Only called after the user callback has been verified to not be null. */ 331 void (*invoke_user_callback)(struct _cyhal_audioss_s* obj, uint32_t hal_event); 332 /** HAL event mask that represents the empty state */ 333 uint32_t event_mask_empty; 334 /** HAL event mask that represents the half empty state */ 335 uint32_t event_mask_half_empty; 336 /** HAL event mask that represents the full state */ 337 uint32_t event_mask_full; 338 /** HAL event mask that represents the half full state */ 339 uint32_t event_mask_half_full; 340 /** HAL event mask that represents async rx complete */ 341 uint32_t event_rx_complete; 342 /** HAL event mask that represents async tx complete */ 343 uint32_t event_tx_complete; 344 /** Error code for invalid pin */ 345 cy_rslt_t err_invalid_pin; 346 /** Error code for invalid argument */ 347 cy_rslt_t err_invalid_arg; 348 /** Error code for invalid clock frequency */ 349 cy_rslt_t err_clock; 350 /** Error code for configuration not supported */ 351 cy_rslt_t err_not_supported; 352 } _cyhal_audioss_interface_t; 353 354 /** 355 * @brief Shared data between i2s and tdm 356 * 357 * Application code should not rely on the specific contents of this struct. 358 * They are considered an implementation detail which is subject to change 359 * between platforms and/or HAL releases. 360 */ 361 typedef struct _cyhal_audioss_s { /* Explicit name to enable forward declaration */ 362 #if defined(CY_IP_MXAUDIOSS) || defined(CY_IP_MXTDM) 363 bool owned_by_configurator; 364 #if defined(CY_IP_MXAUDIOSS) 365 I2S_Type *base; 366 #elif defined(CY_IP_MXTDM) 367 /* None of the PDL APIs actually want a bare TDM_Type */ 368 TDM_STRUCT_Type *base; 369 #endif 370 cyhal_resource_inst_t resource; 371 cyhal_gpio_t pin_tx_sck; 372 cyhal_gpio_t pin_tx_ws; 373 cyhal_gpio_t pin_tx_sdo; 374 cyhal_gpio_t pin_rx_sck; 375 cyhal_gpio_t pin_rx_mclk; 376 cyhal_gpio_t pin_rx_ws; 377 cyhal_gpio_t pin_rx_sdi; 378 cyhal_gpio_t pin_tx_mclk; 379 uint8_t user_fifo_level_rx; 380 uint32_t mclk_hz_rx; 381 uint8_t channel_length_rx; 382 uint8_t word_length_rx; 383 uint32_t mclk_hz_tx; 384 uint8_t channel_length_tx; 385 uint8_t word_length_tx; 386 cyhal_clock_t clock; 387 bool is_clock_owned; 388 uint16_t user_enabled_events; 389 cyhal_event_callback_data_t callback_data; 390 cyhal_async_mode_t async_mode; 391 uint8_t async_dma_priority; 392 cyhal_dma_t tx_dma; 393 cyhal_dma_t rx_dma; 394 // Note: When the async DMA mode is in use, these variables will always reflect the state 395 // that the transfer will be in after the in-progress DMA transfer, if any, is complete 396 volatile const void *async_tx_buff; 397 volatile size_t async_tx_length; 398 volatile void *async_rx_buff; 399 volatile size_t async_rx_length; 400 volatile bool pm_transition_ready; 401 cyhal_syspm_callback_data_t pm_callback; 402 const _cyhal_audioss_interface_t *interface; 403 #else 404 void *empty; 405 #endif 406 } _cyhal_audioss_t; 407 408 /** 409 * @brief Shared I2S/TDM configurator struct 410 * 411 * This struct allows a configurator to provide block configuration information 412 * to the HAL. Because configurator-generated configurations are platform 413 * specific, the contents of this struct is subject to change between platforms 414 * and/or HAL releases. 415 */ 416 typedef struct 417 { 418 #if CYHAL_DRIVER_AVAILABLE_TDM || CYHAL_DRIVER_AVAILABLE_I2S 419 const cyhal_resource_inst_t* resource; 420 #if defined(CY_IP_MXAUDIOSS) 421 const cy_stc_i2s_config_t* config; 422 #elif defined(CY_IP_MXTDM) 423 const cy_stc_tdm_config_t* config; 424 #endif 425 const cyhal_clock_t * clock; 426 uint32_t mclk_hz_rx; /* Must be 0 is mclk is not in use for this direction */ 427 uint32_t mclk_hz_tx; /* Must be 0 is mclk is not in use for this direction */ 428 #else 429 void *empty; 430 #endif /* CYHAL_DRIVER_AVAILABLE_TDM || CYHAL_DRIVER_AVAILABLE_I2S */ 431 } _cyhal_audioss_configurator_t; 432 433 struct _cyhal_adc_channel_s; 434 435 /* Maximum number of channels across all ADC instances. For CAT1A this is provided by the PDL, for CAT1C we have to compute this */ 436 #if defined(CY_IP_MXS40EPASS_ESAR) 437 #if (((CY_IP_MXS40EPASS_ESAR_INSTANCES < 2) || (PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR > PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR)) \ 438 && ((CY_IP_MXS40EPASS_ESAR_INSTANCES < 3) || (PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR > PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR))) 439 #define CY_SAR_MAX_NUM_CHANNELS (PASS_SAR_SLICE_NR0_SAR_SAR_CHAN_NR) 440 #elif ((CY_IP_MXS40EPASS_ESAR_INSTANCES < 2) /* If we got to this point, we know neither 0 isn't the max */ \ 441 && (CY_IP_MXS40EPASS_ESAR_INSTANCES < 3 || (PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR > PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR))) 442 #define CY_SAR_MAX_NUM_CHANNELS (PASS_SAR_SLICE_NR1_SAR_SAR_CHAN_NR) 443 #elif (CY_IP_MXS40EPASS_ESAR_INSTANCES < 4) /* If we got to this point, we know neither 0 nor 1 is the max */ 444 #define CY_SAR_MAX_NUM_CHANNELS (PASS_SAR_SLICE_NR2_SAR_SAR_CHAN_NR) 445 #else 446 #error "Unhandled ADC instance count" 447 #endif 448 #endif 449 /** 450 * @brief ADC object 451 * 452 * Application code should not rely on the specific contents of this struct. 453 * They are considered an implementation detail which is subject to change 454 * between platforms and/or HAL releases. 455 */ 456 typedef struct { 457 #if defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) || defined(CY_IP_MXS40ADCMIC_INSTANCES) 458 bool owned_by_configurator; 459 #if defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) 460 #if defined(CY_IP_MXS40PASS_SAR) 461 SAR_Type* base; 462 #else 463 PASS_SAR_Type* base; 464 uint16_t average_count; /* This is set per channel on this hardware */ 465 bool average_is_accumulate; 466 #endif 467 struct _cyhal_adc_channel_s* channel_config[CY_SAR_MAX_NUM_CHANNELS]; 468 #elif defined(CY_IP_MXS40ADCMIC_INSTANCES) 469 MXS40ADCMIC_Type* base; 470 /* When doing a full scan, which channel are we on */ 471 uint8_t current_channel_index; 472 /* We implement multi-channel sequencing in firmware; there's no fixed channel count specified 473 * in hardware. So size the array based on the number of input pins that are connected */ 474 struct _cyhal_adc_channel_s* channel_config[sizeof(cyhal_pin_map_adcmic_gpio_adc_in) / sizeof(cyhal_pin_map_adcmic_gpio_adc_in[0])]; 475 cy_stc_adcmic_context_t pdl_context; 476 #endif 477 cyhal_resource_inst_t resource; 478 cyhal_clock_t clock; 479 bool dedicated_clock; 480 /* Has at least one conversion completed since the last configuration change */ 481 volatile bool conversion_complete; 482 #if defined(CY_IP_MXS40PASS_SAR) 483 bool stop_after_scan; 484 #endif 485 uint8_t user_enabled_events; 486 cyhal_event_callback_data_t callback_data; 487 /* Always updated to contain the location where the next result should be stored */ 488 int32_t *async_buff_next; 489 bool async_transfer_in_uv; /* Default is counts */ 490 /* Only decremented after all elements from a scan have been copied into async_buff */ 491 size_t async_scans_remaining; 492 #if defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) 493 /* ADCMIC is always continuously scanning and only supports SW-based async transfers */ 494 bool continuous_scanning; 495 cyhal_async_mode_t async_mode; 496 cyhal_dma_t dma; 497 cyhal_source_t source; /* SAR-only; ADCMIC has no useful triggers in DC mode */ 498 int32_t *async_buff_orig; 499 #if defined(CY_IP_MXS40EPASS_ESAR) 500 bool vbg_chan_inited; 501 uint16_t vbg_last_value; 502 #endif /* defined(CY_IP_MXS40EPASS_ESAR) */ 503 #endif 504 #else 505 void *empty; 506 #endif /* defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) || defined(CY_IP_MXS40ADCMIC_INSTANCES) */ 507 } cyhal_adc_t; 508 509 /** 510 * @brief ADC configurator struct 511 * 512 * This struct allows a configurator to provide block configuration information 513 * to the HAL. Because configurator-generated configurations are platform 514 * specific, the contents of this struct is subject to change between platforms 515 * and/or HAL releases. 516 */ 517 typedef struct 518 { 519 #if CYHAL_DRIVER_AVAILABLE_ADC 520 const cyhal_resource_inst_t* resource; 521 #if defined(CY_IP_MXS40PASS_SAR) 522 cy_stc_sar_config_t const* config; 523 #elif defined(CY_IP_MXS40EPASS_ESAR_INSTANCES) 524 cy_stc_sar2_config_t const* config; 525 #elif defined(CY_IP_MXS40ADCMIC_INSTANCES) 526 cy_stc_adcmic_config_t const* config; 527 #endif 528 const cyhal_clock_t * clock; 529 uint8_t num_channels; 530 const uint32_t* achieved_acquisition_time; /* length num_channels */ 531 /* Pins are deliberately omitted from this struct. The configurator supports routing 532 * from arbitrary sources that aren't necessarily pins. The HAL only needs to know what 533 * the pins are for the purposes of reservation, freeing, and routing - all of which the 534 * configurators take care of in this flow */ 535 #else 536 void *empty; 537 #endif 538 } cyhal_adc_configurator_t; 539 540 /** 541 * @brief ADC channel object 542 * 543 * Application code should not rely on the specific contents of this struct. 544 * They are considered an implementation detail which is subject to change 545 * between platforms and/or HAL releases. 546 */ 547 typedef struct _cyhal_adc_channel_s { /* Struct given an explicit name to make the forward declaration above work */ 548 #if defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) || defined(CY_IP_MXS40ADCMIC_INSTANCES) 549 cyhal_adc_t* adc; 550 cyhal_gpio_t vplus; 551 uint8_t channel_idx; 552 #if defined(CY_IP_MXS40ADCMIC_INSTANCES) 553 /* ADCMIC only supports single-ended channels at a fixed sample rate */ 554 cy_en_adcmic_dc_channel_t channel_sel; 555 bool enabled; 556 #elif defined(CY_IP_MXS40PASS_SAR) || defined(CY_IP_MXS40EPASS_ESAR) 557 #if defined(CY_IP_MXS40PASS_SAR) 558 cyhal_gpio_t vminus; 559 #elif defined(CY_IP_MXS40EPASS_ESAR_INSTANCES) 560 bool avg_enabled; 561 #endif 562 /* EPASS only supports single-ended channels */ 563 uint32_t minimum_acquisition_ns; 564 #endif 565 #else 566 void *empty; 567 #endif 568 } cyhal_adc_channel_t; 569 570 /** @brief Comparator object */ 571 typedef struct { 572 #if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(CY_IP_MXS40PASS_CTB_INSTANCES) 573 bool owned_by_configurator; 574 cyhal_resource_inst_t resource; 575 union 576 { 577 #if defined(CY_IP_MXS40PASS_CTB_INSTANCES) 578 CTBM_Type *base_ctb; 579 #endif 580 #if defined(CY_IP_MXLPCOMP_INSTANCES) 581 LPCOMP_Type *base_lpcomp; 582 #endif 583 }; 584 cyhal_gpio_t pin_vin_p; 585 cyhal_gpio_t pin_vin_m; 586 cyhal_gpio_t pin_out; 587 cyhal_event_callback_data_t callback_data; 588 uint32_t irq_cause; 589 #else 590 void *empty; 591 #endif 592 } cyhal_comp_t; 593 594 /** 595 * @brief Comp configurator struct 596 * 597 * This struct allows a configurator to provide block configuration information 598 * to the HAL. Because configurator-generated configurations are platform 599 * specific, the contents of this struct is subject to change between platforms 600 * and/or HAL releases. 601 */ 602 typedef struct 603 { 604 #if CYHAL_DRIVER_AVAILABLE_COMP 605 const cyhal_resource_inst_t* resource; 606 union 607 { 608 #if _CYHAL_DRIVER_AVAILABLE_COMP_LP 609 const cy_stc_lpcomp_config_t *lpcomp; 610 #endif 611 #if _CYHAL_DRIVER_AVAILABLE_COMP_CTB 612 const cy_stc_ctb_opamp_config_t *opamp; 613 #endif 614 }; 615 /* No GPIOs specified. The configurator could have routed from a non-preferred 616 * GPIO, or from another non-GPIO on-chip source. */ 617 #else 618 void *empty; 619 #endif 620 } cyhal_comp_configurator_t; 621 622 /** 623 * @brief CRC object 624 * 625 * Application code should not rely on the specific contents of this struct. 626 * They are considered an implementation detail which is subject to change 627 * between platforms and/or HAL releases. 628 */ 629 typedef struct { 630 #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) 631 CRYPTO_Type* base; 632 cyhal_resource_inst_t resource; 633 uint32_t crc_width; 634 #else 635 void *empty; 636 #endif 637 } cyhal_crc_t; 638 639 /** 640 * @brief DAC object 641 * 642 * Application code should not rely on the specific contents of this struct. 643 * They are considered an implementation detail which is subject to change 644 * between platforms and/or HAL releases. 645 */ 646 typedef struct { 647 #ifdef CY_IP_MXS40PASS_CTDAC 648 bool owned_by_configurator; 649 CTDAC_Type* base_dac; 650 CTBM_Type* base_opamp; 651 cyhal_resource_inst_t resource_dac; 652 cyhal_resource_inst_t resource_opamp; 653 cyhal_resource_inst_t resource_aref_opamp; 654 cyhal_gpio_t pin; 655 #else 656 void *empty; 657 #endif 658 } cyhal_dac_t; 659 660 /** 661 * @brief DAC configurator struct 662 * 663 * This struct allows a configurator to provide block configuration information 664 * to the HAL. Because configurator-generated configurations are platform 665 * specific, the contents of this struct is subject to change between platforms 666 * and/or HAL releases. 667 */ 668 typedef struct 669 { 670 #if CYHAL_DRIVER_AVAILABLE_DAC 671 const cyhal_resource_inst_t* resource; 672 const cy_stc_ctdac_config_t* config; 673 #else 674 void *empty; 675 #endif /* CYHAL_DRIVER_AVAILABLE_DAC */ 676 } cyhal_dac_configurator_t; 677 678 /** 679 * @brief OPAMP object 680 * 681 * Application code should not rely on the specific contents of this struct. 682 * They are considered an implementation detail which is subject to change 683 * between platforms and/or HAL releases. 684 */ 685 typedef struct { 686 #if defined(CY_IP_MXS40PASS_CTB_INSTANCES) 687 bool owned_by_configurator; 688 CTBM_Type* base; 689 cyhal_resource_inst_t resource; 690 cyhal_gpio_t pin_vin_p; 691 cyhal_gpio_t pin_vin_m; 692 cyhal_gpio_t pin_vout; 693 bool is_init_success; 694 #else 695 void *empty; 696 #endif 697 } cyhal_opamp_t; 698 699 /** 700 * @brief Opamp configurator struct 701 * 702 * This struct allows a configurator to provide block configuration information 703 * to the HAL. Because configurator-generated configurations are platform 704 * specific, the contents of this struct is subject to change between platforms 705 * and/or HAL releases. 706 */ 707 typedef struct 708 { 709 #if CYHAL_DRIVER_AVAILABLE_OPAMP 710 const cyhal_resource_inst_t* resource; 711 const cy_stc_ctb_opamp_config_t* config; 712 /* No GPIOs specified. The configurator could have routed from a non-preferred 713 * GPIO, or from another non-GPIO on-chip source. */ 714 #else 715 void *empty; 716 #endif 717 } cyhal_opamp_configurator_t; 718 719 /** 720 * @brief NVM object 721 * 722 * Application code should not rely on the specific contents of this struct. 723 * They are considered an implementation detail which is subject to change 724 * between platforms and/or HAL releases. 725 */ 726 typedef struct { 727 void *empty; 728 } cyhal_nvm_t; 729 730 /** 731 * @brief I2C object 732 * 733 * Application code should not rely on the specific contents of this staruct. 734 * They are considered an implementation detail which is subject to chnge 735 * between platforms and/or HAL releases. 736 */ 737 typedef struct { 738 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 739 CySCB_Type* base; 740 cyhal_resource_inst_t resource; 741 cyhal_gpio_t pin_sda; 742 cyhal_gpio_t pin_scl; 743 cyhal_clock_t clock; 744 bool is_clock_owned; 745 cy_stc_scb_i2c_context_t context; 746 cy_stc_scb_i2c_master_xfer_config_t rx_config; 747 cy_stc_scb_i2c_master_xfer_config_t tx_config; 748 uint32_t irq_cause; 749 uint8_t addr_irq_cause; 750 uint16_t pending; 751 bool op_in_callback; 752 _cyhal_buffer_info_t rx_slave_buff; 753 _cyhal_buffer_info_t tx_slave_buff; 754 cyhal_event_callback_data_t callback_data; 755 cyhal_event_callback_data_t addr_callback_data; 756 bool dc_configured; 757 #else 758 void *empty; 759 #endif 760 } cyhal_i2c_t; 761 762 /** 763 * @brief I2C configurator struct 764 * 765 * This struct allows a configurator to provide block configuration information 766 * to the HAL. Because configurator-generated configurations are platform 767 * specific, the contents of this struct is subject to change between platforms 768 * and/or HAL releases. 769 */ 770 typedef struct { 771 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 772 const cyhal_resource_inst_t* resource; 773 const cy_stc_scb_i2c_config_t* config; 774 const cyhal_clock_t* clock; 775 #else 776 void *empty; 777 #endif /* defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) */ 778 } cyhal_i2c_configurator_t; 779 780 /** 781 * @brief EZI2C object 782 * 783 * Application code should not rely on the specific contents of this struct. 784 * They are considered an implementation detail which is subject to change 785 * between platforms and/or HAL releases. 786 */ 787 typedef struct { 788 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 789 CySCB_Type* base; 790 cyhal_resource_inst_t resource; 791 cyhal_gpio_t pin_sda; 792 cyhal_gpio_t pin_scl; 793 cyhal_clock_t clock; 794 bool is_clock_owned; 795 cy_stc_scb_ezi2c_context_t context; 796 uint32_t irq_cause; 797 cyhal_event_callback_data_t callback_data; 798 bool two_addresses; 799 bool dc_configured; 800 #else 801 void *empty; 802 #endif 803 } cyhal_ezi2c_t; 804 805 /** 806 * @brief EZI2C configurator struct 807 * 808 * This struct allows a configurator to provide block configuration information 809 * to the HAL. Because configurator-generated configurations are platform 810 * specific, the contents of this struct is subject to change between platforms 811 * and/or HAL releases. 812 */ 813 typedef struct { 814 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 815 const cyhal_resource_inst_t* resource; 816 const cy_stc_scb_ezi2c_config_t* config; 817 const cyhal_clock_t* clock; 818 #else 819 void *empty; 820 #endif /* defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) */ 821 } cyhal_ezi2c_configurator_t; 822 823 /** 824 * @brief I2S object 825 * 826 * Application code should not rely on the specific contents of this struct. 827 * They are considered an implementation detail which is subject to change 828 * between platforms and/or HAL releases. 829 */ 830 typedef _cyhal_audioss_t cyhal_i2s_t; 831 832 /** 833 * @brief I2S configurator struct 834 * 835 * This struct allows a configurator to provide block configuration information 836 * to the HAL. Because configurator-generated configurations are platform 837 * specific, the contents of this struct is subject to change between platforms 838 * and/or HAL releases. 839 */ 840 typedef _cyhal_audioss_configurator_t cyhal_i2s_configurator_t; 841 842 /** @brief IPC object */ 843 typedef struct cyhal_ipc_s { 844 #if defined(IPC) || defined(CY_IP_MXIPC) 845 bool sema_preemptable; 846 uint32_t sema_number; 847 struct cyhal_ipc_queue_s* queue_obj; 848 uint16_t user_events; 849 /* events, that were already processed in callback */ 850 uint32_t processed_events; 851 cyhal_event_callback_data_t callback_data; 852 struct cyhal_ipc_s* prev_object; 853 #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) 854 void* rtos_sema; 855 #endif /* defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE) */ 856 #else 857 void *empty; 858 #endif 859 } cyhal_ipc_t; 860 861 /** 862 * @brief KeyScan object 863 * 864 * Application code should not rely on the specific contents of this struct. 865 * They are considered an implementation detail which is subject to change 866 * between platforms and/or HAL releases. 867 */ 868 typedef struct { 869 #if defined (CY_IP_MXKEYSCAN) 870 MXKEYSCAN_Type* base; 871 cyhal_resource_inst_t resource; 872 cyhal_gpio_t rows[MXKEYSCAN_NUM_ROWS_IN]; 873 cyhal_gpio_t columns[MXKEYSCAN_NUM_COLS_OUT]; 874 cyhal_clock_t clock; 875 bool is_clock_owned; 876 cy_stc_keyscan_context_t context; 877 uint32_t irq_cause; 878 cyhal_event_callback_data_t callback_data; 879 bool dc_configured; 880 #else 881 void *empty; 882 #endif 883 } cyhal_keyscan_t; 884 885 /** 886 * @brief KeyScan configurator struct 887 * 888 * This struct allows a configurator to provide block configuration information 889 * to the HAL. Because configurator-generated configurations are platform 890 * specific, the contents of this struct is subject to change between platforms 891 * and/or HAL releases. 892 */ 893 typedef struct { 894 #if defined (CY_IP_MXKEYSCAN) 895 const cyhal_resource_inst_t* resource; 896 /* keyscan PDL config is not const here because the config argument to Cy_Keyscan_Init is not const */ 897 cy_stc_ks_config_t* config; 898 const cyhal_clock_t* clock; 899 #else 900 void *empty; 901 #endif /* defined (CY_IP_MXKEYSCAN) */ 902 } cyhal_keyscan_configurator_t; 903 904 /** 905 * @brief LPTIMER object 906 * 907 * Application code should not rely on the specific contents of this struct. 908 * They are considered an implementation detail which is subject to change 909 * between platforms and/or HAL releases. 910 */ 911 typedef struct { 912 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) 913 MCWDT_Type *base; 914 cy_en_mcwdtctr_t counter; 915 volatile uint32_t offset; 916 volatile uint32_t final_time; 917 #else 918 MCWDT_STRUCT_Type *base; 919 #endif 920 cyhal_resource_inst_t resource; 921 cyhal_event_callback_data_t callback_data; 922 bool clear_int_mask; 923 uint8_t isr_instruction; 924 } cyhal_lptimer_t; 925 926 /** 927 * @brief PDM-PCM object 928 * 929 * Application code should not rely on the specific contents of this struct. 930 * They are considered an implementation detail which is subject to change 931 * between platforms and/or HAL releases. 932 */ 933 typedef struct { 934 #if !defined(COMPONENT_CAT1C) 935 #if defined(CY_IP_MXAUDIOSS_INSTANCES) || defined(CY_IP_MXTDM_INSTANCES) 936 bool owned_by_configurator; 937 PDM_Type *base; 938 cyhal_resource_inst_t resource; 939 cyhal_gpio_t pin_data; 940 cyhal_gpio_t pin_clk; 941 cyhal_clock_t clock; 942 bool is_clock_owned; 943 /* Number of entries in the fifo when the trigger fires - i.e. one greater than the value in the register */ 944 uint8_t user_trigger_level; 945 /** User requested irq, see cyhal_pdm_pcm_event_t */ 946 uint32_t irq_cause; 947 cyhal_event_callback_data_t callback_data; 948 uint8_t word_size; 949 cyhal_dma_t dma; 950 #if defined(CY_IP_MXPDM) 951 cyhal_dma_t dma_paired; 952 #endif 953 volatile bool stabilized; 954 volatile bool pm_transition_ready; 955 cyhal_syspm_callback_data_t pm_callback; 956 void *async_buffer; 957 size_t async_read_remaining; 958 #else 959 void *empty; 960 #endif 961 #else 962 void *empty; 963 #endif 964 } cyhal_pdm_pcm_t; 965 966 /** 967 * @brief PDM-PCM configurator struct 968 * 969 * This struct allows a configurator to provide block configuration information 970 * to the HAL. Because configurator-generated configurations are platform 971 * specific, the contents of this struct is subject to change between platforms 972 * and/or HAL releases. 973 */ 974 typedef struct { 975 #if !defined(COMPONENT_CAT1C) 976 #if defined(CY_IP_MXAUDIOSS_INSTANCES) || defined(CY_IP_MXTDM_INSTANCES) 977 const cyhal_resource_inst_t* resource; 978 #if defined(CY_IP_MXAUDIOSS_INSTANCES) 979 const cy_stc_pdm_pcm_config_t* config; 980 #elif defined(CY_IP_MXTDM_INSTANCES) 981 const cy_stc_pdm_pcm_config_v2_t* config; 982 const cy_stc_pdm_pcm_channel_config_t* chan_config; 983 #endif 984 const cyhal_clock_t* clock; 985 #else 986 void *empty; 987 #endif 988 #else 989 void *empty; 990 #endif 991 } cyhal_pdm_pcm_configurator_t; 992 993 /** 994 * @brief PWM object 995 * 996 * Application code should not rely on the specific contents of this struct. 997 * They are considered an implementation detail which is subject to change 998 * between platforms and/or HAL releases. 999 */ 1000 typedef struct { 1001 #ifdef CY_IP_MXTCPWM 1002 cyhal_tcpwm_t tcpwm; 1003 cyhal_gpio_t pin; 1004 cyhal_gpio_t pin_compl; 1005 bool dead_time_set; 1006 #else 1007 void *empty; 1008 #endif 1009 } cyhal_pwm_t; 1010 1011 /** 1012 * @brief PWM configurator struct 1013 * 1014 * This struct allows a configurator to provide block configuration information 1015 * to the HAL. Because configurator-generated configurations are platform 1016 * specific, the contents of this struct is subject to change between platforms 1017 * and/or HAL releases. 1018 */ 1019 typedef struct 1020 { 1021 #if CYHAL_DRIVER_AVAILABLE_PWM 1022 const cyhal_resource_inst_t* resource; 1023 cy_stc_tcpwm_pwm_config_t const* config; 1024 const cyhal_clock_t * clock; 1025 #else 1026 void *empty; 1027 #endif /* CYHAL_DRIVER_AVAILABLE_PWM */ 1028 } cyhal_pwm_configurator_t; 1029 1030 /** 1031 * @brief QSPI object 1032 * 1033 * Application code should not rely on the specific contents of this struct. 1034 * They are considered an implementation detail which is subject to change 1035 * between platforms and/or HAL releases. 1036 */ 1037 typedef struct { 1038 #ifdef CY_IP_MXSMIF 1039 SMIF_Type* base; 1040 cyhal_resource_inst_t resource; 1041 cyhal_gpio_t pin_sclk; 1042 en_hsiom_sel_t saved_sclk_hsiom; 1043 cyhal_gpio_t pin_io[8]; 1044 en_hsiom_sel_t saved_io_hsiom[8]; 1045 cyhal_gpio_t pin_ssel[SMIF_CHIP_TOP_SPI_SEL_NR]; 1046 en_hsiom_sel_t saved_ssel_hsiom[SMIF_CHIP_TOP_SPI_SEL_NR]; 1047 /* Active slave select */ 1048 cy_en_smif_slave_select_t slave_select; 1049 cyhal_clock_t clock; 1050 bool is_clock_owned; 1051 uint8_t mode; 1052 cy_stc_smif_context_t context; 1053 uint32_t irq_cause; 1054 cyhal_event_callback_data_t callback_data; 1055 cyhal_syspm_callback_data_t pm_callback; 1056 #if CYHAL_DRIVER_AVAILABLE_SYSPM 1057 bool pm_transition_pending; 1058 #endif // CYHAL_DRIVER_AVAILABLE_SYSPM 1059 bool dc_configured; 1060 #else 1061 void *empty; 1062 #endif /* ifdef CY_IP_MXSMIF */ 1063 } cyhal_qspi_t; 1064 1065 /** 1066 * @brief QSPI configurator struct 1067 * 1068 * This struct allows a configurator to provide block configuration information 1069 * to the HAL. Because configurator-generated configurations are platform 1070 * specific, the contents of this struct is subject to change between platforms 1071 * and/or HAL releases. 1072 */ 1073 typedef struct { 1074 #ifdef CY_IP_MXSMIF 1075 const cyhal_resource_inst_t* resource; 1076 const cy_stc_smif_config_t* config; 1077 cyhal_clock_t* clock; 1078 struct 1079 { 1080 cyhal_gpio_t sclk; 1081 cyhal_gpio_t ssel[4]; 1082 cyhal_gpio_t io[8]; 1083 } gpios; 1084 /* Bit representation of currently not supported interrupts: 1085 Bit 5 : Memory Mode Alignment Error 1086 Bit 4 : RX Data FIFO Underflow 1087 Bit 3 : TX Command FIFO Overflow 1088 Bit 2 : TX Data FIFO Overflow 1089 Bit 1 : RX FIFO Level Trigger 1090 Bit 0 : TX FIFO Level Trigger 1091 */ 1092 uint8_t irqs; 1093 /* Bit representation of DMA triggers activation indicators: 1094 Bit 1 : RX Trigger Output activated in configurator 1095 Bit 0 : TX Trigger Output activated in configurator 1096 */ 1097 uint8_t dmas; 1098 #else 1099 void *empty; 1100 #endif /* defined(CY_IP_MXSMIF) */ 1101 } cyhal_qspi_configurator_t; 1102 1103 /** 1104 * @brief Quadrature Decoder object 1105 * 1106 * Application code should not rely on the specific contents of this struct. 1107 * They are considered an implementation detail which is subject to change 1108 * between platforms and/or HAL releases. 1109 */ 1110 typedef struct { 1111 #ifdef CY_IP_MXTCPWM 1112 cyhal_tcpwm_t tcpwm; 1113 cyhal_gpio_t phi_a; 1114 cyhal_gpio_t phi_b; 1115 cyhal_gpio_t index; 1116 uint32_t last_counter_value; 1117 #else 1118 void *empty; 1119 #endif 1120 } cyhal_quaddec_t; 1121 1122 /** 1123 * @brief Quadrature Decoder configurator struct 1124 * 1125 * This struct allows a configurator to provide block configuration information 1126 * to the HAL. Because configurator-generated configurations are platform 1127 * specific, the contents of this struct is subject to change between platforms 1128 * and/or HAL releases. 1129 */ 1130 typedef struct 1131 { 1132 #if CYHAL_DRIVER_AVAILABLE_QUADDEC 1133 const cyhal_resource_inst_t* resource; 1134 const cy_stc_tcpwm_quaddec_config_t* config; 1135 const cyhal_clock_t * clock; 1136 #else 1137 void *empty; 1138 #endif /* CYHAL_DRIVER_AVAILABLE_QUADDEC */ 1139 } cyhal_quaddec_configurator_t; 1140 1141 /** 1142 * @brief RNG object 1143 * 1144 * Application code should not rely on the specific contents of this struct. 1145 * They are considered an implementation detail which is subject to change 1146 * between platforms and/or HAL releases. 1147 */ 1148 typedef struct { 1149 #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) 1150 CRYPTO_Type* base; 1151 cyhal_resource_inst_t resource; 1152 #else 1153 void *empty; 1154 #endif 1155 } cyhal_trng_t; 1156 1157 /** 1158 * @brief RTC object 1159 * 1160 * Application code should not rely on the specific contents of this struct. 1161 * They are considered an implementation detail which is subject to change 1162 * between platforms and/or HAL releases. 1163 */ 1164 typedef struct { 1165 #if defined(CY_IP_MXS40SRSS) || defined(CY_IP_MXS40SSRSS) || defined(CY_IP_MXS22SRSS) 1166 cy_stc_rtc_dst_t dst; 1167 #else 1168 void *empty; 1169 #endif 1170 } cyhal_rtc_t; 1171 1172 /** 1173 * @brief RTC configurator struct 1174 * 1175 * This struct allows a configurator to provide block configuration information 1176 * to the HAL. Because configurator-generated configurations are platform 1177 * specific, the contents of this struct is subject to change between platforms 1178 * and/or HAL releases. 1179 */ 1180 typedef struct 1181 { 1182 #if CYHAL_DRIVER_AVAILABLE_RTC 1183 const cyhal_resource_inst_t* resource; 1184 cy_stc_rtc_config_t const* config; 1185 cy_stc_rtc_dst_t const* dst_config; 1186 #else 1187 void *empty; 1188 #endif /* CYHAL_DRIVER_AVAILABLE_RTC */ 1189 } cyhal_rtc_configurator_t; 1190 1191 #if defined(CY_IP_MXSDHC) 1192 1193 /** 1194 * Data transfer status on SDHC/SDIO 1195 */ 1196 typedef enum 1197 { 1198 /** No data transfer in progress */ 1199 _CYHAL_SDXX_NOT_RUNNING = 0x0, 1200 /** Waiting for a command to complete */ 1201 _CYHAL_SDXX_WAIT_CMD_COMPLETE = 0x1, 1202 /** Waiting for a transfer to complete */ 1203 _CYHAL_SDXX_WAIT_XFER_COMPLETE = 0x2, 1204 /** Waiting for completion of both a command and a transfer */ 1205 _CYHAL_SDXX_WAIT_BOTH = _CYHAL_SDXX_WAIT_CMD_COMPLETE | _CYHAL_SDXX_WAIT_XFER_COMPLETE 1206 } _cyhal_sdxx_data_transfer_status_t; 1207 1208 /** 1209 * Contains common members between SDHC and SDIO 1210 */ 1211 typedef struct { 1212 bool is_sdio; 1213 void* obj; 1214 1215 SDHC_Type* base; 1216 cyhal_resource_inst_t resource; 1217 cy_stc_sd_host_context_t context; 1218 cyhal_clock_t clock; 1219 1220 bool emmc; 1221 cy_en_sd_host_dma_type_t dma_type; 1222 uint32_t adma_descriptor_tbl[2]; 1223 _cyhal_sdxx_data_transfer_status_t data_transfer_status; 1224 1225 cyhal_gpio_t pin_clk; 1226 cyhal_gpio_t pin_cmd; 1227 cyhal_gpio_t pin_io_vol_sel; 1228 bool low_voltage_io_set; 1229 1230 uint32_t irq_cause; 1231 cyhal_event_callback_data_t callback_data; 1232 1233 #if CYHAL_DRIVER_AVAILABLE_SYSPM 1234 bool pm_transition_pending; 1235 cyhal_syspm_callback_data_t pm_callback_data; 1236 #endif // CYHAL_DRIVER_AVAILABLE_SYSPM 1237 /* whether the block is configured by device-configurator (true) 1238 * or by user via HAL API (false) */ 1239 bool dc_configured; 1240 bool clock_owned; 1241 } _cyhal_sdxx_t; 1242 1243 #endif /* defined(CY_IP_MXSDHC) */ 1244 1245 /** 1246 * @brief SDHC object 1247 * 1248 * Application code should not rely on the specific contents of this struct. 1249 * They are considered an implementation detail which is subject to change 1250 * between platforms and/or HAL releases. 1251 */ 1252 typedef struct { 1253 #if defined(CY_IP_MXSDHC) 1254 _cyhal_sdxx_t sdxx; 1255 1256 uint8_t bus_width; 1257 bool enable_led_control; 1258 /* TOUT setting of SDHC block */ 1259 uint8_t data_timeout_tout; 1260 bool data_timeout_auto_reconfig; 1261 /* Desired by user data timeout in card clocks */ 1262 uint32_t data_timeout_card_clocks_user; 1263 cyhal_gpio_t pin_data[8]; 1264 cyhal_gpio_t pin_card_detect; 1265 cyhal_gpio_t pin_card_pwr_en; 1266 cyhal_gpio_t pin_card_mech_write_prot; 1267 cyhal_gpio_t pin_led_ctrl; 1268 cyhal_gpio_t pin_emmc_reset; 1269 bool low_voltage_io_desired; 1270 uint32_t bus_frequency_hz; 1271 /* Frequency of HF clock, that provided to SDHC block */ 1272 uint32_t block_source_freq_hz; 1273 /** This needs to mirror cyhal_gpio_callback_data_t, which can't be referenced directly. */ 1274 struct cyhal_sdhc_t_gpio_cb 1275 { 1276 void* callback; 1277 void* callback_arg; 1278 void* next; 1279 cyhal_gpio_t pin; 1280 } card_detect_cb; 1281 /* card detect GPIO callback enabled */ 1282 bool cd_gpio_cb_enabled; 1283 uint16_t emmc_generic_cmd6_time_ms; 1284 #else 1285 void *empty; 1286 #endif /* defined(CY_IP_MXSDHC) */ 1287 } cyhal_sdhc_t; 1288 1289 /** 1290 * @brief SDHC configurator struct 1291 * 1292 * This struct allows a configurator to provide block configuration information 1293 * to the HAL. Because configurator-generated configurations are platform 1294 * specific, the contents of this struct is subject to change between platforms 1295 * and/or HAL releases. 1296 */ 1297 typedef struct { 1298 #if defined(CY_IP_MXSDHC) 1299 const cyhal_resource_inst_t* resource; 1300 const cy_stc_sd_host_init_config_t* host_config; 1301 cy_stc_sd_host_sd_card_config_t* card_config; 1302 cyhal_clock_t* clock; 1303 struct 1304 { 1305 cyhal_gpio_t clk; 1306 cyhal_gpio_t cmd; 1307 cyhal_gpio_t data[8]; 1308 cyhal_gpio_t card_detect; 1309 cyhal_gpio_t io_volt_sel; 1310 cyhal_gpio_t card_pwr_en; 1311 cyhal_gpio_t card_mech_write_prot; 1312 cyhal_gpio_t led_ctrl; 1313 cyhal_gpio_t emmc_reset; 1314 } gpios; 1315 #else 1316 void *empty; 1317 #endif /* defined(CY_IP_MXSDHC) */ 1318 } cyhal_sdhc_configurator_t; 1319 1320 /** 1321 * @brief SDIO object 1322 * 1323 * Application code should not rely on the specific contents of this struct. 1324 * They are considered an implementation detail which is subject to change 1325 * between platforms and/or HAL releases. 1326 */ 1327 typedef struct { 1328 #if defined(CY_IP_MXSDHC) 1329 _cyhal_sdxx_t sdxx; 1330 /* whether the block is configured by device-configurator (true) 1331 * or by user via HAL API (false) */ 1332 bool dc_configured; 1333 bool clock_owned; 1334 #elif defined(CYHAL_UDB_SDIO) 1335 cyhal_resource_inst_t resource; 1336 cyhal_gpio_t pin_clk; 1337 cyhal_gpio_t pin_cmd; 1338 1339 uint32_t irq_cause; 1340 1341 bool pm_transition_pending; 1342 cyhal_syspm_callback_data_t pm_callback_data; 1343 #endif /* defined(CYHAL_IP_MXSDHC) */ 1344 1345 #if defined(CY_IP_MXSDHC) || defined(CYHAL_UDB_SDIO) 1346 cyhal_gpio_t pin_data0; 1347 cyhal_gpio_t pin_data1; 1348 cyhal_gpio_t pin_data2; 1349 cyhal_gpio_t pin_data3; 1350 1351 uint32_t frequencyhal_hz; 1352 uint16_t block_size; 1353 1354 uint32_t events; 1355 #else 1356 void *empty; 1357 #endif /* defined(CY_IP_MXSDHC) || defined(CYHAL_UDB_SDIO) */ 1358 } cyhal_sdio_t; 1359 1360 /** 1361 * @brief SDIO configurator struct 1362 * 1363 * This struct allows a configurator to provide block configuration information 1364 * to the HAL. Because configurator-generated configurations are platform 1365 * specific, the contents of this struct is subject to change between platforms 1366 * and/or HAL releases. 1367 */ 1368 typedef struct { 1369 #if defined(CY_IP_MXSDHC) 1370 const cyhal_resource_inst_t* resource; 1371 const cy_stc_sd_host_init_config_t* host_config; 1372 cy_stc_sd_host_sd_card_config_t* card_config; 1373 cyhal_clock_t* clock; 1374 struct 1375 { 1376 cyhal_gpio_t clk; 1377 cyhal_gpio_t cmd; 1378 cyhal_gpio_t data[4]; 1379 } gpios; 1380 #else 1381 void *empty; 1382 #endif /* defined(CY_IP_MXSDHC) */ 1383 } cyhal_sdio_configurator_t; 1384 1385 /** 1386 * @brief SPI object 1387 * 1388 * Application code should not rely on the specific contents of this struct. 1389 * They are considered an implementation detail which is subject to change 1390 * between platforms and/or HAL releases. 1391 */ 1392 typedef struct { 1393 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 1394 CySCB_Type* base; 1395 cyhal_resource_inst_t resource; 1396 cyhal_gpio_t pin_miso; 1397 cyhal_gpio_t pin_mosi; 1398 cyhal_gpio_t pin_sclk; 1399 cyhal_gpio_t pin_ssel[4]; 1400 cy_en_scb_spi_polarity_t ssel_pol[4]; 1401 uint8_t active_ssel; 1402 cyhal_clock_t clock; 1403 cy_en_scb_spi_sclk_mode_t clk_mode; 1404 uint8_t mode; 1405 uint8_t data_bits; 1406 bool is_slave; 1407 bool alloc_clock; 1408 uint8_t oversample_value; 1409 bool msb_first; 1410 cy_stc_scb_spi_context_t context; 1411 uint32_t irq_cause; 1412 uint16_t volatile pending; 1413 bool op_in_callback; 1414 uint8_t write_fill; 1415 void *rx_buffer; 1416 uint32_t rx_buffer_size; 1417 const void *tx_buffer; 1418 uint32_t tx_buffer_size; 1419 bool is_async; 1420 cyhal_event_callback_data_t callback_data; 1421 bool dc_configured; 1422 #else 1423 void *empty; 1424 #endif 1425 } cyhal_spi_t; 1426 1427 /** 1428 * @brief SPI configurator struct 1429 * 1430 * This struct allows a configurator to provide block configuration information 1431 * to the HAL. Because configurator-generated configurations are platform 1432 * specific, the contents of this struct is subject to change between platforms 1433 * and/or HAL releases. 1434 */ 1435 typedef struct { 1436 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 1437 const cyhal_resource_inst_t* resource; 1438 const cy_stc_scb_spi_config_t* config; 1439 const cyhal_clock_t* clock; 1440 struct 1441 { 1442 cyhal_gpio_t sclk; 1443 cyhal_gpio_t ssel[4]; 1444 cyhal_gpio_t mosi; 1445 cyhal_gpio_t miso; 1446 } gpios; 1447 #else 1448 void *empty; 1449 #endif /* defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) */ 1450 } cyhal_spi_configurator_t; 1451 1452 /** 1453 * @brief TDM object 1454 * 1455 * Application code should not rely on the specific contents of this struct. 1456 * They are considered an implementation detail which is subject to change 1457 * between platforms and/or HAL releases. 1458 */ 1459 typedef _cyhal_audioss_t cyhal_tdm_t; 1460 1461 /** 1462 * @brief TDM configurator struct 1463 * 1464 * This struct allows a configurator to provide block configuration information 1465 * to the HAL. Because configurator-generated configurations are platform 1466 * specific, the contents of this struct is subject to change between platforms 1467 * and/or HAL releases. 1468 */ 1469 typedef _cyhal_audioss_configurator_t cyhal_tdm_configurator_t; 1470 1471 /** 1472 * @brief Timer object 1473 * 1474 * Application code should not rely on the specific contents of this struct. 1475 * They are considered an implementation detail which is subject to change 1476 * between platforms and/or HAL releases. 1477 */ 1478 typedef struct { 1479 #ifdef CY_IP_MXTCPWM 1480 cyhal_tcpwm_t tcpwm; 1481 uint32_t default_value; 1482 #else 1483 void *empty; 1484 #endif 1485 } cyhal_timer_t; 1486 1487 /** 1488 * @brief Timer configurator struct 1489 * 1490 * This struct allows a configurator to provide block configuration information 1491 * to the HAL. Because configurator-generated configurations are platform 1492 * specific, the contents of this struct is subject to change between platforms 1493 * and/or HAL releases. 1494 */ 1495 typedef struct 1496 { 1497 #if CYHAL_DRIVER_AVAILABLE_TIMER 1498 const cyhal_resource_inst_t* resource; 1499 const cy_stc_tcpwm_counter_config_t* config; 1500 const cyhal_clock_t * clock; 1501 #else 1502 void *empty; 1503 #endif /* CYHAL_DRIVER_AVAILABLE_TIMER */ 1504 } cyhal_timer_configurator_t; 1505 1506 /** 1507 * @brief UART object 1508 * 1509 * Application code should not rely on the specific contents of this struct. 1510 * They are considered an implementation detail which is subject to change 1511 * between platforms and/or HAL releases. 1512 */ 1513 typedef struct { 1514 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 1515 CySCB_Type* base; 1516 cyhal_resource_inst_t resource; 1517 cyhal_gpio_t pin_rx; 1518 cyhal_gpio_t pin_tx; 1519 cyhal_gpio_t pin_cts; 1520 cyhal_gpio_t pin_rts; 1521 bool cts_enabled; 1522 bool rts_enabled; 1523 bool is_clock_owned; 1524 cyhal_clock_t clock; 1525 cy_stc_scb_uart_context_t context; 1526 cy_stc_scb_uart_config_t config; 1527 uint32_t irq_cause; 1528 en_hsiom_sel_t saved_tx_hsiom; 1529 en_hsiom_sel_t saved_rts_hsiom; 1530 cyhal_event_callback_data_t callback_data; 1531 bool dc_configured; 1532 uint32_t baud_rate; 1533 #if (CYHAL_DRIVER_AVAILABLE_DMA) 1534 cyhal_async_mode_t async_mode; 1535 cyhal_dma_t dma_tx; 1536 cyhal_dma_t dma_rx; 1537 volatile uint32_t async_tx_length; 1538 volatile uint32_t async_rx_length; 1539 volatile void *async_tx_buff; 1540 volatile void *async_rx_buff; 1541 uint32_t user_fifo_level; 1542 #endif 1543 #else 1544 void *empty; 1545 #endif 1546 } cyhal_uart_t; 1547 1548 /** 1549 * @brief UART configurator struct 1550 * 1551 * This struct allows a configurator to provide block configuration information 1552 * to the HAL. Because configurator-generated configurations are platform 1553 * specific, the contents of this struct is subject to change between platforms 1554 * and/or HAL releases. 1555 */ 1556 typedef struct { 1557 #if defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) 1558 const cyhal_resource_inst_t* resource; 1559 const cy_stc_scb_uart_config_t* config; 1560 const cyhal_clock_t* clock; 1561 struct 1562 { 1563 cyhal_gpio_t pin_tx; 1564 cyhal_gpio_t pin_rts; 1565 cyhal_gpio_t pin_cts; 1566 } gpios; 1567 #else 1568 void *empty; 1569 #endif /* defined(CY_IP_MXSCB) || defined(CY_IP_MXS22SCB) */ 1570 } cyhal_uart_configurator_t; 1571 1572 /** 1573 * @brief USB Device object 1574 * 1575 * Application code should not rely on the specific contents of this struct. 1576 * They are considered an implementation detail which is subject to change 1577 * between platforms and/or HAL releases. 1578 */ 1579 typedef struct { 1580 #ifdef CY_IP_MXUSBFS 1581 USBFS_Type* base; 1582 cy_stc_usbfs_dev_drv_context_t context; 1583 cyhal_resource_inst_t resource; 1584 cyhal_resource_inst_t pll_resource; 1585 cyhal_clock_t clock; 1586 bool shared_clock; 1587 cyhal_gpio_t pin_dp; 1588 cyhal_gpio_t pin_dm; 1589 cyhal_syspm_callback_data_t pm_callback; 1590 uint8_t *rd_data[CY_USBFS_DEV_DRV_NUM_EPS_MAX]; 1591 uint32_t rd_size[CY_USBFS_DEV_DRV_NUM_EPS_MAX]; 1592 #else 1593 void *empty; 1594 #endif 1595 } cyhal_usb_dev_t; 1596 1597 /** 1598 * @brief WDT object 1599 * 1600 * Application code should not rely on the specific contents of this struct. 1601 * They are considered an implementation detail which is subject to change 1602 * between platforms and/or HAL releases. 1603 */ 1604 typedef struct { 1605 uint8_t placeholder; 1606 } cyhal_wdt_t; 1607 1608 #if defined(__cplusplus) 1609 } 1610 #endif /* __cplusplus */ 1611 1612 /** \} group_hal_impl_hw_types */ 1613 /** \} group_hal_impl */ 1614
