1 /***************************************************************************//**
2 * \file cyhal_gpio_impl.h
3 *
4 * Description:
5 * Provides a high level interface for interacting with the Infineon GPIO. This is
6 * a wrapper around the lower level PDL API.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 #pragma once
29
30 #include "cy_gpio.h"
31 #include "cyhal_gpio.h"
32 #include "cyhal_utils.h"
33 #include "cy_utils.h"
34
35 #if defined(CY_IP_MXS40IOSS) || defined(CY_IP_M0S8IOSS) || defined(CY_IP_MXS40SIOSS) || defined(CY_IP_MXS22IOSS)
36
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif /* __cplusplus */
40
41 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
42 /** \addtogroup group_hal_impl_gpio GPIO
43 * \ingroup group_hal_impl
44 * \{
45 * \section group_hal_impl_gpio_interrupt Interrupt Priorities
46 * In CAT1 & CAT2 (PSoC™ 6/4), each GPIO port has a single IRQ line. Hence, there can only be a
47 * single interrupt handler and priority set at the hardware level. The HAL tracks any interrupt
48 * handler that is registered through \ref cyhal_gpio_register_callback separately so it can run
49 * the appropriate pin specific callback anyway. However, the HAL will take over the interrupt
50 * for the port. Additionally, it cannot do anything about the priority and all pins on the port
51 * will share the last priority set via \ref cyhal_gpio_enable_event. for a specific pin on a port
52 * will apply to the all the pins in that pin's port. If multiple pins on the same port are set at
53 * different priorities, the priority that the last pin is set to will be applied to all pins used
54 * on that port.
55 *
56 * \section group_hal_impl_gpio_interconnect Interconnect
57 * In CAT1 & CAT2 (PSoC™ 6/4) only a subset of pins available on a board are connected to input
58 * triggers. Another subset is connected to output triggers. Check the appropriate file for your
59 * board in pin_packages/ to determine what pins can be used. A particular pin can have 0 or 1
60 * input triggers and 0 or 1 output triggers. Input triggers to a pin are used to clear/set the
61 * GPIO pins output. An output trigger on a pin is activated when the pins GPIO input is set.
62 *
63 * \} group_hal_impl_gpio
64 */
65 #elif defined(COMPONENT_CAT2)
66 /** \addtogroup group_hal_impl_gpio GPIO
67 * \ingroup group_hal_impl
68 * \{
69 * \section group_hal_impl_gpio_interrupt Interrupt Priorities
70 * In CAT2 (PMG/PSoC™ 4), ports 0 through 3 have dedicated IRQ lines (ioss_interrupts_gpio_0_IRQn - ioss_interrupts_gpio_3_IRQn)
71 * and other ports are required to use the All-Port IRQ line (ioss_interrupt_gpio_IRQn).
72 * If multiple pins on the same port are set at different priorities, the priority that the
73 * last pin is set to will be applied to all pins used on that port. When using the pin that does
74 * not have a dedicated IRQ line (port 4 and higher) following are the implications,
75 * 1. The priority set through \ref cyhal_gpio_enable_event for the specific pin will
76 * apply to all pins on port 4 and higher.
77 * 2. The interrupts will not be proccessed in the same order as they were received
78 * because the same All-Port IRQ line will be used for all GPIOs.
79 *
80 ** \section group_hal_impl_gpio_interconnect Interconnect
81 * PSoC™ 4 does not have GPIO triggers.
82 * \} group_hal_impl_gpio
83 */
84 #endif
85
86 /*******************************************************************************
87 * Defines
88 *******************************************************************************/
89 #define CYHAL_GET_PORTADDR(pin) (Cy_GPIO_PortToAddr(CYHAL_GET_PORT(pin))) /**< Macro to get the port address from pin */
90
91 /*******************************************************************************
92 * Functions
93 *******************************************************************************/
94
cyhal_gpio_write_internal(cyhal_gpio_t pin,bool value)95 __STATIC_INLINE void cyhal_gpio_write_internal(cyhal_gpio_t pin, bool value)
96 {
97 Cy_GPIO_Write(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), value);
98 }
99
100 #define cyhal_gpio_write(pin, value) cyhal_gpio_write_internal(pin, value)
101
cyhal_gpio_read_internal(cyhal_gpio_t pin)102 __STATIC_INLINE bool cyhal_gpio_read_internal(cyhal_gpio_t pin)
103 {
104 return 0 != Cy_GPIO_Read(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
105 }
106
107 #define cyhal_gpio_read(pin) cyhal_gpio_read_internal(pin)
108
cyhal_gpio_toggle_internal(cyhal_gpio_t pin)109 __STATIC_INLINE void cyhal_gpio_toggle_internal(cyhal_gpio_t pin)
110 {
111 Cy_GPIO_Inv(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
112 }
113
114 #define cyhal_gpio_toggle(pin) cyhal_gpio_toggle_internal(pin)
115
116 #if defined(__cplusplus)
117 }
118 #endif /* __cplusplus */
119
120 #endif /* defined(CY_IP_MXS40IOSS) || defined(CY_IP_M0S8IOSS) || defined(CY_IP_MXS40SIOSS) */
121
