1 /***************************************************************************//** 2 * \file cy_sysint.h 3 * \version 1.90.1 4 * 5 * \brief 6 * Provides an API declaration of the SysInt driver 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 11 * an affiliate of Cypress Semiconductor Corporation. 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_sysint 29 * \{ 30 * The SysInt driver provides an API to configure the device peripheral interrupts. 31 * It provides a lightweight interface to complement 32 * the <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html">CMSIS core NVIC API</a>. 33 * The provided functions are applicable for all cores in a device and they can 34 * be used to configure and connect device peripheral interrupts to one or more 35 * cores. 36 * 37 * The functions and other declarations used in this driver are in cy_sysint.h. 38 * You can include cy_pdl.h to get access to all functions 39 * and declarations in the PDL. 40 * 41 * \section group_sysint_vector_table Vector Table 42 * \subsection group_sysint_CM0_CM4 CM0+/CM4 43 * The vector table defines the entry addresses of the processor exceptions and 44 * the device specific interrupts. It is located at the start address of the flash 45 * and is copied by the startup code to RAM. The symbol code __Vectors is the 46 * address of the vector table in the startup code and the register SCB->VTOR 47 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 48 * section for the implementation details. 49 * The default interrupt handler functions are defined as weak functions to a dummy handler 50 * in the startup file. The naming convention is \<interrupt_name\>_IRQHandler. 51 * 52 * Defining these in the user application allows the linker to place them in 53 * the vector table in flash/ROM. For example: 54 * \code 55 * void ioss_interrupts_gpio_0_IRQHandler(void) 56 * { 57 * ... 58 * } 59 * \endcode 60 * And can be used like this: 61 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_flashVT 62 * Using this method avoids the need for a RAM vector table. However in this scenario, 63 * interrupt handler re-location at run-time is not possible, unless the vector table is 64 * relocated to RAM. 65 * 66 * \subsection group_sysint_CM33 CM33 67 * CM33 with Security extension supports two vector tables, one for secure world and another 68 * for non-secure world. Secure interrupt vector table is placed in the secure ROM/FLASH, where as 69 * non-secure interrupt vector table is placed in the non-secure ROM/FLASH. In both scenarios, 70 * vector tables are copied by the startup code to secure and non-secure RAM respectively. 71 * The symbol code __s_vector_table is the address of the secure vector table and 72 * __ns_vector_table is for the non-secure world in the startup code. The register SCB->VTOR 73 * holds the start address of the vector table. See \ref group_system_config_device_vector_table 74 * section for the implementation details. 75 * 76 * CM33 without Security extension will support only non-secure interrupts. 77 * 78 * The default interrupt handler functions are defined to a dummy handler in the startup file. 79 * The naming convention is \<interrupt_name\>_IRQHandler. 80 * 81 * \subsection group_sysint_CM55 CM55 82 * CM55 is without Security extension and will support only non-secure interrupts. It is similar to CM33 non-secure part. 83 * Additionally CM55 core has support to block EWIC (External Wakeup Interrupt Controller). EWIC is a peripheral to the processor 84 * and it can be a source of wakeup in the system. EWIC block is disabled by default and needs to be enabled in order for the DS 85 * wakeup source to work. 86 * 87 * \subsection group_sysint_CM0_CM7 CAT1C CM0+/CM7 88 * The vector table defines the entry addresses of the processor exceptions and 89 * the device specific interrupts. Interrupt vector table is placed in the ROM/FLASH. The 90 * vector table is copied by the startup code to RAM. The symbol code __ramVectors is the address of the vector table. 91 * The register SCB->VTOR holds the start address of the vector table. See \ref group_system_config_device_vector_table 92 * section for the implementation details. 93 * Each system interrupt has to be mapped onto one out of eight external CPU interrupts. When a system interrupt is triggered, corresponding mapped 94 * CPU IRQ gets triggered which results in the execution of the default CPU IRQ handler. In this handler the system interrupt mapped to this 95 * CPU interrupt will be fetched and executed. 96 * 97 * The default CPU IRQ handler functions are defined as weak functions in the startup file. 98 * The naming convention followed is \<core\>_CpuIntr\<interrupt_number\>_Handler. 99 * Below is the code snippet. 100 * \code 101 * void Interrupt_Handler_Port0(void) 102 * { 103 * ... //User interrupt handler 104 * } 105 * \endcode 106 107 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init 108 * 109 * \section group_sysint_driver_usage Driver Usage 110 * 111 * \subsection group_sysint_initialization Initialization 112 * 113 * Interrupt numbers are defined in a device-specific header file, such as 114 * cy8c68237bz_ble.h, and are consistent with interrupt handlers defined in the 115 * vector table. 116 * 117 * To configure an interrupt, call Cy_SysInt_Init(). Populate 118 * the configuration structure (cy_stc_sysint_t) and pass it as a parameter 119 * along with the ISR address. This initializes the interrupt and 120 * instructs the CPU to jump to the specified ISR vector upon a valid trigger. 121 * For CM0+ core, the configuration structure (cy_stc_sysint_t) 122 * must specify the device interrupt source (cm0pSrc) that feeds into the CM0+ NVIC 123 * mux (intrSrc). 124 * 125 * For CM4/CM33/CM55 core, system interrupt source 'n' is connected to the 126 * corresponding IRQn. Deep-sleep capable interrupts are allocated to Deep Sleep 127 * capable IRQn channels. 128 * 129 * For CAT1C CM7/CM0+ core, the configuration structure (cy_stc_sysint_t) must specify 130 * system interrupt source, CPU IRQ and the CPU IRQ priority. The system interrupt source is mapped to bit 0-15 of intrSrc parameter 131 * and CPU IRQ is mapped to bit 16-31 of intrSrc parameter. 132 * 133 * For CM0+ core, deep Sleep wakeup-capability is determined by the CPUSS_CM0_DPSLP_IRQ_NR 134 * parameter, where the first N number of muxes (NvicMux0 ... NvicMuxN-1) have the 135 * capability to trigger Deep Sleep interrupts. A Deep Sleep capable interrupt source 136 * must be connected to one of these muxes to be able to trigger in Deep Sleep. 137 * Refer to the IRQn_Type definition in the device header. 138 * 139 * 1. For CPUSS_ver1 the CM0+ core supports up to 32 interrupt channels (IRQn 0-31). To allow all device 140 * interrupts to be routable to the NVIC of this core, there is a 240:1 multiplexer 141 * at each of the 32 NVIC channels. 142 * 143 * 2. For CPUSS_ver2 the CM0+ core supports up to 8 hardware interrupt channels (IRQn 0-7) and software-only 144 * interrupt channels (IRQn 8-15). The device has up to 1023 interrupts that can be connected to any of the 145 * hardware interrupt channels. In this structure, multiple interrupt sources can be connected 146 * simultaneously to one NVIC channel. The application must then query the interrupt source on the 147 * channel and service the active interrupt(s). The priority of these interrupts is determined by the 148 * interrupt number as defined in the cy_en_intr_t enum, where the lower number denotes higher priority 149 * over the higher number. 150 * 151 * \subsection group_sysint_enable Enable 152 * 153 * After initializing an interrupt, use the CMSIS Core 154 * <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ()</a> function 155 * to enable it. Given an initialization structure named config, 156 * the function should be called as follows: 157 * \code 158 * NVIC_EnableIRQ(config.intrSrc) 159 * \endcode 160 * 161 * \subsection group_sysint_service Writing an interrupt service routine 162 * 163 * Servicing interrupts in the Peripheral Drivers should follow a prescribed 164 * recipe to ensure all interrupts are serviced and duplicate interrupts are not 165 * received. Any peripheral-specific register that must be written to clear the 166 * source of the interrupt should be written as soon as possible in the interrupt 167 * service routine. However, note that due to buffering on the output bus to the 168 * peripherals, the write clearing of the interrupt may be delayed. After performing 169 * the normal interrupt service that should respond to the interrupting 170 * condition, the interrupt register that was initially written to clear the 171 * register should be read before returning from the interrupt service routine. 172 * This read ensures that the initial write has been flushed out to the hardware. 173 * Note, no additional processing should be performed based on the result of this 174 * read, as this read is intended only to ensure the write operation is flushed. 175 * 176 * This final read may indicate a pending interrupt. What this means is that in 177 * the interval between when the write actually happened at the peripheral and 178 * when the read actually happened at the peripheral, an interrupting condition 179 * occurred. This is ok and a return from the interrupt is still the correct 180 * action. As soon as conditions warrant, meaning interrupts are enabled and 181 * there are no higher priority interrupts pending, the interrupt will be 182 * triggered again to service the additional condition. 183 * 184 * \section group_sysint_section_configuration_considerations Configuration Considerations 185 * 186 * Certain CM0+ <a href="https://www.keil.com/pack/doc/CMSIS/Core/html/group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">NVIC IRQn</a> 187 * channels are reserved for system use: 188 * <table class="doxtable"> 189 * <tr><th>NVIC channel (\ref IRQn_Type)</th><th>Interrupt source (\ref cy_en_intr_t)</th><th>Purpose</th></tr> 190 * <tr><td>#0 (NvicMux0_IRQn)</td><td>IPC Interrupt #0 (cpuss_interrupts_ipc_0_IRQn)</td><td>System Calls to ROM</td></tr> 191 * <tr><td>#1 (NvicMux1_IRQn)</td><td>IPC Interrupt #3 (cpuss_interrupts_ipc_3_IRQn)</td><td>System IPC pipe in the default startup</td></tr> 192 * </table> 193 * 194 * \note For CPUSS_ver2, each NVIC channel can be shared between multiple interrupt sources. 195 * However it is not recommended to share the application NVIC channel with the reserved channels. 196 * 197 * \note In CAT1C, NvicMux0_IRQn and NvicMux1_IRQn are used by ROM and not meant for user. 198 * 199 * \section group_sysint_more_information More Information 200 * 201 * Refer to the technical reference manual (TRM) and the device datasheet. 202 * 203 * \section group_sysint_changelog Changelog 204 * <table class="doxtable"> 205 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 206 * <tr> 207 * <td>1.90.1</td> 208 * <td>Fixed MISRA 2012 8.5 and 8.6 violations.</td> 209 * <td>MISRA 2012 compliance..</td> 210 * </tr> 211 * <tr> 212 * <td>1.90</td> 213 * <td>Updated \ref Cy_SysInt_Init, \ref Cy_SysInt_SetVector and \ref Cy_SysInt_GetVector APIs.</td> 214 * <td>Code Clean up.</td> 215 * </tr> 216 * <tr> 217 * <td>1.80</td> 218 * <td>API's Cy_SysInt_SetInterruptSource(), Cy_SysInt_GetInterruptSource(), Cy_SysInt_DisconnectInterruptSource(), 219 * Cy_SysInt_SetNmiSource(), Cy_SysInt_GetNmiSource(), Cy_SysInt_SoftwareTrig(), Cy_SysInt_GetNvicConnection(), 220 * Cy_SysInt_GetInterruptActive(), Cy_SysInt_InitExtIRQ(), Cy_SysInt_InitIntIRQ(), Cy_SysInt_Init(), 221 * Cy_SysInt_SetVector(), Cy_SysInt_GetVector(), Cy_SysInt_SetSystemIrqVector(), Cy_SysInt_EnableSystemInt(), Cy_SysInt_DisableSystemInt() 222 * modified.</td> 223 * <td>New device support, Fix Coverity issues, Documentation enhancement.</td> 224 * </tr> 225 * <tr> 226 * <td>1.70</td> 227 * <td>Support for CAT1C, CAT1D.<br>Newly added API's Cy_SysInt_SetSystemIrqVector() to set the user ISR vector for the System Interrupt, 228 * Cy_SysInt_GetSystemIrqVector() to get the address of the current user ISR vector for the System Interrupt, 229 * Cy_SysInt_EnableSystemInt() to enable system interrupt, Cy_SysInt_DisableSystemInt() to disable system interrupt, 230 * Cy_SysInt_InitExtIRQ() to initialize the referenced external interrupt by setting the CPU IRQ priority and the interrupt vector, 231 * Cy_SysInt_InitIntIRQ() to initialize the referenced internal interrupt by setting the priority and the interrupt vector.</td> 232 * <td>New devices support.</td> 233 * </tr> 234 235 * <tr> 236 * <td>1.60</td> 237 * <td>Support for CM33.</td> 238 * <td>New devices support.</td> 239 * </tr> 240 * <tr> 241 * <td>1.50</td> 242 * <td>Fixed MISRA 2012 violations.</td> 243 * <td>MISRA 2012 compliance.</td> 244 * </tr> 245 * <tr> 246 * <td>1.40</td> 247 * <td>Updated the CY_SYSINT_IS_PC_0 macro to access the protected register 248 * for the secure CYB06xx7 devices via \ref group_pra driver. 249 * </td> 250 * <td>Added PSoC 64 devices support.</td> 251 * </tr> 252 * <tr> 253 * <td>1.30.1</td> 254 * <td>Minor documentation updates.</td> 255 * <td>Documentation enhancement.</td> 256 * </tr> 257 * <tr> 258 * <td>1.30</td> 259 * <td>The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.</td> 260 * <td>User experience enhancement.</td> 261 * </tr> 262 * <tr> 263 * <td>1.20.1</td> 264 * <td>The Vector Table section is extended with a code snippet.</td> 265 * <td>Documentation enhancement.</td> 266 * </tr> 267 * <tr> 268 * <td rowspan="3">1.20</td> 269 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td> 270 * <td>Driver library directory-structure simplification.</td> 271 * </tr> 272 * <tr> 273 * <td>Added CPUSS_ver2 support to the following API functions: 274 * - \ref Cy_SysInt_SetInterruptSource 275 * - \ref Cy_SysInt_SetNmiSource 276 * - \ref Cy_SysInt_GetNmiSource 277 * 278 * Added new API functions: 279 * - \ref Cy_SysInt_DisconnectInterruptSource 280 * - \ref Cy_SysInt_GetNvicConnection 281 * - \ref Cy_SysInt_GetInterruptActive 282 * 283 * Deprecated following functions: 284 * - Cy_SysInt_SetIntSource 285 * - Cy_SysInt_GetIntSource 286 * - Cy_SysInt_SetIntSourceNMI 287 * - Cy_SysInt_GetIntSourceNMI 288 * </td> 289 * <td>New devices support.</td> 290 * </tr> 291 * <tr> 292 * <td>Added register access layer. Use register access macros instead 293 * of direct register access using dereferenced pointers.</td> 294 * <td>Makes register access device-independent, so that the PDL does 295 * not need to be recompiled for each supported part number.</td> 296 * </tr> 297 * <tr> 298 * <td>1.10</td> 299 * <td>Cy_SysInt_GetState() function is redefined to call NVIC_GetEnableIRQ()</td> 300 * <td></td> 301 * </tr> 302 * <tr> 303 * <td>1.0</td> 304 * <td>Initial version</td> 305 * <td></td> 306 * </tr> 307 * </table> 308 * 309 * \defgroup group_sysint_macros Macros 310 * \defgroup group_sysint_globals Global variables 311 * \defgroup group_sysint_functions Functions 312 * \defgroup group_sysint_data_structures Data Structures 313 * \defgroup group_sysint_enums Enumerated Types 314 */ 315 316 317 #if !defined (CY_SYSINT_H) 318 #define CY_SYSINT_H 319 320 #include "cy_device.h" 321 322 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS) 323 324 #include <stddef.h> 325 #include "cy_syslib.h" 326 #if defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 327 #include "cy_pra.h" 328 #endif /* defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) */ 329 #include "cy_device_headers.h" 330 331 #if defined(__cplusplus) 332 extern "C" { 333 #endif 334 335 /*************************************** 336 * Global Variable 337 ***************************************/ 338 339 /** 340 * \addtogroup group_sysint_globals 341 * \{ 342 */ 343 344 #if defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) 345 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \ 346 'Coverity does not check the .S assembly files, the definition is a part of startup_psoc6_04_cm4.s file.') 347 extern const cy_israddress __Vectors[]; /**< Vector table in flash */ 348 extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ 349 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6') 350 351 #endif /* defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) */ 352 /** \} group_sysint_globals */ 353 354 355 /*************************************** 356 * Global Interrupt 357 ***************************************/ 358 359 /** 360 * \addtogroup group_sysint_macros 361 * \{ 362 */ 363 364 /** Driver major version */ 365 #define CY_SYSINT_DRV_VERSION_MAJOR 1 366 367 /** Driver minor version */ 368 #define CY_SYSINT_DRV_VERSION_MINOR 90 369 370 /** SysInt driver ID */ 371 #define CY_SYSINT_ID CY_PDL_DRV_ID (0x15U) 372 373 /** \} group_sysint_macros */ 374 375 376 /*************************************** 377 * Enumeration 378 ***************************************/ 379 380 /** 381 * \addtogroup group_sysint_enums 382 * \{ 383 */ 384 385 /** 386 * SysInt Driver error codes 387 */ 388 typedef enum 389 { 390 CY_SYSINT_SUCCESS = 0x0UL, /**< Returned successful */ 391 CY_SYSINT_BAD_PARAM = CY_SYSINT_ID | CY_PDL_STATUS_ERROR | 0x1UL, /**< Bad parameter was passed */ 392 } cy_en_sysint_status_t; 393 394 /** NMI connection input */ 395 typedef enum 396 { 397 CY_SYSINT_NMI1 = 1UL, /**< NMI source input 1 */ 398 CY_SYSINT_NMI2 = 2UL, /**< NMI source input 2 */ 399 CY_SYSINT_NMI3 = 3UL, /**< NMI source input 3 */ 400 CY_SYSINT_NMI4 = 4UL, /**< NMI source input 4 */ 401 } cy_en_sysint_nmi_t; 402 403 /** \} group_sysint_enums */ 404 405 406 /*************************************** 407 * Configuration Structure 408 ***************************************/ 409 410 /** 411 * \addtogroup group_sysint_data_structures 412 * \{ 413 */ 414 415 /** 416 * Initialization configuration structure for a single interrupt channel 417 */ 418 typedef struct { 419 #if defined (CY_IP_M7CPUSS) 420 uint32_t intrSrc; /**< Bit 0-15 indicate system interrupt and bit 16-31 will indicate the CPU IRQ */ 421 #else /* CY_IP_M7CPUSS */ 422 IRQn_Type intrSrc; /**< Interrupt source */ 423 #endif 424 #if (CY_CPU_CORTEX_M0P) && defined (CY_IP_M4CPUSS) 425 cy_en_intr_t cm0pSrc; /**< Maps cm0pSrc device interrupt to intrSrc */ 426 #endif /* CY_CPU_CORTEX_M0P */ 427 uint32_t intrPriority; /**< Interrupt priority number (Refer to __NVIC_PRIO_BITS) */ 428 } cy_stc_sysint_t; 429 430 /** \} group_sysint_data_structures */ 431 432 433 /*************************************** 434 * Constants 435 ***************************************/ 436 437 /** \cond INTERNAL */ 438 439 #define CY_INT_IRQ_BASE (16U) /**< Start location of interrupts in the vector table */ 440 #define CY_SYSINT_STATE_MASK (1UL) /**< Mask for interrupt state */ 441 #define CY_SYSINT_STIR_MASK (0xFFUL) /**< Mask for software trigger interrupt register */ 442 #define CY_SYSINT_DISABLE (0UL) /**< Disable interrupt */ 443 #define CY_SYSINT_ENABLE (1UL) /**< Enable interrupt */ 444 #define CY_SYSINT_INT_STATUS_MSK (0x7UL) 445 446 #if defined (CY_IP_M4CPUSS) 447 /*(CY_IP_M4CPUSS_VERSION == 1u) */ 448 #define CY_SYSINT_CM0P_MUX_MASK (0xFFUL) /**< CM0+ NVIC multiplexer mask */ 449 #define CY_SYSINT_CM0P_MUX_SHIFT (2U) /**< CM0+ NVIC multiplexer shift */ 450 #define CY_SYSINT_CM0P_MUX_SCALE (3U) /**< CM0+ NVIC multiplexer scaling value */ 451 #define CY_SYSINT_CM0P_MUX0 (0U) /**< CM0+ NVIC multiplexer register 0 */ 452 #define CY_SYSINT_CM0P_MUX1 (1U) /**< CM0+ NVIC multiplexer register 1 */ 453 #define CY_SYSINT_CM0P_MUX2 (2U) /**< CM0+ NVIC multiplexer register 2 */ 454 #define CY_SYSINT_CM0P_MUX3 (3U) /**< CM0+ NVIC multiplexer register 3 */ 455 #define CY_SYSINT_CM0P_MUX4 (4U) /**< CM0+ NVIC multiplexer register 4 */ 456 #define CY_SYSINT_CM0P_MUX5 (5U) /**< CM0+ NVIC multiplexer register 5 */ 457 #define CY_SYSINT_CM0P_MUX6 (6U) /**< CM0+ NVIC multiplexer register 6 */ 458 #define CY_SYSINT_CM0P_MUX7 (7U) /**< CM0+ NVIC multiplexer register 7 */ 459 #define CY_SYSINT_MUX_REG_MSK (0x7UL) 460 #endif /* CY_IP_M4CPUSS */ 461 462 /* Parameter validation macros */ 463 #define CY_SYSINT_IS_PRIORITY_VALID(intrPriority) ((uint32_t)(1UL << __NVIC_PRIO_BITS) > (intrPriority)) 464 #define CY_SYSINT_IS_VECTOR_VALID(userIsr) (NULL != (userIsr)) 465 #define CY_SYSINT_IS_NMI_NUM_VALID(nmiNum) (((nmiNum) == CY_SYSINT_NMI1) || \ 466 ((nmiNum) == CY_SYSINT_NMI2) || \ 467 ((nmiNum) == CY_SYSINT_NMI3) || \ 468 ((nmiNum) == CY_SYSINT_NMI4)) 469 #if defined (CY_IP_M4CPUSS) 470 #if CY_CPU_CORTEX_M4 && defined(CY_DEVICE_SECURE) && defined(CY_DEVICE_PSOC6ABLE2) 471 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, \ 472 CY_PRA_REG32_GET(CY_PRA_INDX_PROT_MPU_MS_CTL))) 473 #else 474 #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(0U))) 475 #endif 476 #endif /* CY_IP_M4CPUSS */ 477 /** \endcond */ 478 479 480 /*************************************** 481 * Function Prototypes 482 ***************************************/ 483 484 /** 485 * \addtogroup group_sysint_functions 486 * \{ 487 */ 488 489 490 /******************************************************************************* 491 * Function Name: Cy_SysInt_Init 492 ****************************************************************************//** 493 * 494 * \brief Initializes the referenced interrupt by setting the priority and the 495 * interrupt vector. 496 * In case of CM33 with Security Extension enabled, if this function is called 497 * from secure world then, the parameters are used to configure secure interrupt. 498 * If it is called form non-secure world then the parameters are used to configure 499 * non-secure interrupt. In case of CM33 without Security Extension, this function 500 * always configures the non-secure interrupt. 501 * In case of CM55, this function always configures the non-secure interrupt. 502 * In case of CM7/CM0+ it initializes the external system interrupt, maps it to CPU interrupt and 503 * registers the User ISR vector for the System Interrupt. 504 * 505 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 506 * 507 * \param config 508 * Interrupt configuration structure 509 * 510 * \param userIsr 511 * Address of the ISR 512 * 513 * \return 514 * Initialization status 515 * 516 * \note CM0+/CM4 <br/> 517 * The interrupt vector will be relocated only if the vector table was 518 * moved to __ramVectors in SRAM. Otherwise it is ignored. 519 * 520 * \note CM33<br/> 521 * The interrupt vector will be relocated only if the vector table was 522 * moved to __s_vector_table_rw and __ns_vector_table_rw for secure and 523 * non-secure world respectively. 524 * 525 * \note CM55<br/> 526 * The interrupt vector will be relocated only if the vector table was 527 * moved to __ns_vector_table_rw non-secure world. 528 * 529 * \funcusage 530 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_Init 531 * 532 *******************************************************************************/ 533 cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t* config, cy_israddress userIsr); 534 535 536 /******************************************************************************* 537 * Function Name: Cy_SysInt_SetVector 538 ****************************************************************************//** 539 * 540 * \brief Changes the ISR vector for the interrupt. 541 * 542 * CM0+/CM4:<br/> 543 * This function relies on the assumption that the vector table is 544 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 545 * return the address of the default ISR location in the flash vector table. 546 * 547 * CM0+/CM7:<br/> 548 * This function relies on the assumption that the vector table is 549 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 550 * return the address of the default ISR location in the flash vector table. 551 * This function is applicable only to User Interrupts (NvicMux0_IRQn - NvicMux7_IRQn) 552 * and System Interrupts (Internal0_IRQn - Internal0_IRQn). 553 * 554 * CM33:<br/> 555 * When called from secure world. this function relies on the assumption that the 556 * vector table is relocated to __s_vector_table_rw[] in secure SRAM. Otherwise it will 557 * return the address of the default ISR location in the secure flash/ROM vector table. 558 * 559 * When called from non-secure world. this function relies on the assumption that 560 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 561 * Otherwise it will return the address of the default ISR location in the non-secure 562 * flash/ROM vector table. 563 * 564 * CM55:<br/> 565 * This function relies on the assumption that 566 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 567 * Otherwise it will return the address of the default ISR location in the non-secure 568 * flash/ROM vector table. 569 * 570 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 571 * \param IRQn 572 * Interrupt source 573 * 574 * \param userIsr 575 * Address of the ISR to set in the interrupt vector table 576 * 577 * \return 578 * Previous address of the ISR in the interrupt vector table 579 * 580 * \note For CM0+, this function sets the interrupt vector for the interrupt 581 * channel on the NVIC. 582 * 583 * \note In case of CM33 with Security Extension enabled, if this function is called 584 * from secure world then, it sets the interrupt vector for the secure world. 585 * If it is called form non-secure world then it sets the interrupt vector for the 586 * non-secure world. 587 * 588 * \funcusage 589 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 590 * 591 *******************************************************************************/ 592 cy_israddress Cy_SysInt_SetVector(IRQn_Type IRQn, cy_israddress userIsr); 593 594 595 /******************************************************************************* 596 * Function Name: Cy_SysInt_GetVector 597 ****************************************************************************//** 598 * 599 * \brief Gets the address of the current ISR vector for the interrupt. 600 * 601 * CM0+/CM4:<br/> 602 * This function relies on the assumption that the vector table is 603 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 604 * return the address of the default ISR location in the flash vector table. 605 * 606 * CM0+/CM7:<br/> 607 * This function relies on the assumption that the vector table is 608 * relocated to __ramVectors[RAM_VECTORS_SIZE] in SRAM. Otherwise it will 609 * return the address of the default ISR location in the flash vector table. 610 * This function is applicable only to User Interrupts (NvicMux0_IRQn - NvicMux7_IRQn) 611 * and System Interrupts (Internal0_IRQn - Internal0_IRQn). 612 * 613 * CM33:<br/> 614 * When called from the secure world, this function relies on the assumption that 615 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 616 * Otherwise it will return the address of the default ISR location in the 617 * flash/ROM vector table. 618 * 619 * CM55:<br/> 620 * This function relies on the assumption that 621 * the vector table is relocated to __ns_vector_table_rw[] in non-secure SRAM. 622 * Otherwise it will return the address of the default ISR location in the 623 * flash/ROM vector table. 624 * 625 * \param IRQn 626 * Interrupt source 627 * 628 * \return 629 * Address of the ISR in the interrupt vector table 630 * 631 * \note CM0+:<br/> This function returns the interrupt vector for the interrupt 632 * channel on the NVIC. 633 * 634 * \note CM33:<br/>In case of CM33 with Security Extension enabled, if this function is called 635 * from secure world then, it returns the interrupt vector for the secure world. 636 * If it is called form non-secure world then it returns the interrupt vector 637 * for the non-secure world. 638 * 639 * \funcusage 640 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetVector 641 * 642 *******************************************************************************/ 643 cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); 644 645 646 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 647 /******************************************************************************* 648 * Function Name: Cy_SysInt_SetInterruptSource 649 ****************************************************************************//** 650 * 651 * \brief Configures the interrupt selection for the specified NVIC channel. 652 * 653 * To disconnect the interrupt source from the NVIC channel 654 * use the \ref Cy_SysInt_DisconnectInterruptSource. 655 * 656 * \param IRQn 657 * NVIC channel number connected to the CPU core. 658 * 659 * \param devIntrSrc 660 * Device interrupt to be routed to the NVIC channel. 661 * 662 * \note This function is available for CM0+/CM7 core only. 663 * 664 * \funcusage 665 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 666 * 667 *******************************************************************************/ 668 void Cy_SysInt_SetInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 669 670 #if defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 671 /******************************************************************************* 672 * Function Name: Cy_SysInt_GetInterruptSource 673 ****************************************************************************//** 674 * 675 * \brief Gets the interrupt source of the NVIC channel. 676 * 677 * \param IRQn 678 * NVIC channel number connected to the CPU core 679 * 680 * \return 681 * Device interrupt connected to the NVIC channel. A returned value of 682 * "disconnected_IRQn" indicates that the interrupt source is disconnected. 683 * 684 * \note This function is available for CM0+ core only. 685 * 686 * \note This function supports only devices using CPUSS_ver1. For all 687 * other devices, use the Cy_SysInt_GetNvicConnection() function. 688 * 689 * \funcusage 690 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 691 * 692 *******************************************************************************/ 693 cy_en_intr_t Cy_SysInt_GetInterruptSource(IRQn_Type IRQn); 694 #endif 695 696 /******************************************************************************* 697 * Function Name: Cy_SysInt_GetNvicConnection 698 ****************************************************************************//** 699 * 700 * \brief Gets the NVIC channel to which the interrupt source is connected. 701 * 702 * \param devIntrSrc 703 * Device interrupt that is potentially connected to the NVIC channel. 704 * 705 * \return 706 * NVIC channel number connected to the CPU core. A returned value of 707 * "unconnected_IRQn" indicates that the interrupt source is disabled. 708 * 709 * \note This function is available for CM0+/CM7 core only. 710 * 711 * \note This function supports only devices using CPUSS_ver2 or higher. 712 * 713 * \funcusage 714 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetInterruptSource 715 * 716 *******************************************************************************/ 717 IRQn_Type Cy_SysInt_GetNvicConnection(cy_en_intr_t devIntrSrc); 718 719 720 /******************************************************************************* 721 * Function Name: Cy_SysInt_GetInterruptActive 722 ****************************************************************************//** 723 * 724 * \brief Gets the highest priority active interrupt for the selected NVIC channel. 725 * 726 * The priority of the interrupt in a given channel is determined by the index 727 * value of the interrupt in the cy_en_intr_t enum. The lower the index, the 728 * higher the priority. E.g. Consider a case where an interrupt source with value 729 * 29 and an interrupt source with value 46 both source the same NVIC channel. If 730 * both are active (triggered) at the same time, calling Cy_SysInt_GetInterruptActive() 731 * will return 29 as the active interrupt. 732 * 733 * \param IRQn 734 * NVIC channel number connected to the CPU core 735 * 736 * \return 737 * Device interrupt connected to the NVIC channel. A returned value of 738 * "disconnected_IRQn" indicates that there are no active (pending) interrupts 739 * on this NVIC channel. 740 * 741 * \note This function is available for CM0+/CM7 core only. 742 * 743 * \note This function supports only devices using CPUSS_ver2 or higher. 744 * 745 * \funcusage 746 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_GetInterruptActive 747 * 748 *******************************************************************************/ 749 cy_en_intr_t Cy_SysInt_GetInterruptActive(IRQn_Type IRQn); 750 #endif 751 752 753 #if defined(CY_IP_M4CPUSS) && (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 754 /******************************************************************************* 755 * Function Name: Cy_SysInt_DisconnectInterruptSource 756 ****************************************************************************//** 757 * 758 * \brief Disconnect the interrupt source from the specified NVIC channel. 759 * 760 * \param IRQn 761 * NVIC channel number connected to the CPU core. 762 * This parameter is ignored for devices using CPUSS_ver2. 763 * 764 * \param devIntrSrc 765 * Device interrupt routed to the NVIC channel. 766 * This parameter is ignored for devices using CPUSS_ver1. 767 * 768 * \note This function is available for CM0+ core only. 769 * 770 * \funcusage 771 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_DisconnectInterruptSource 772 * 773 *******************************************************************************/ 774 void Cy_SysInt_DisconnectInterruptSource(IRQn_Type IRQn, cy_en_intr_t devIntrSrc); 775 #endif 776 777 #if defined (CY_IP_M7CPUSS) || defined (CY_DOXYGEN) 778 /******************************************************************************* 779 * Function Name: Cy_SysInt_InitExtIRQ 780 ****************************************************************************//** 781 * 782 * \brief Initializes the referenced external interrupt by setting the CPU IRQ priority and the 783 * interrupt vector. 784 * 785 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 786 * 787 * \param config 788 * Interrupt configuration structure 789 * 790 * \param userIsr 791 * Address of the ISR 792 * 793 * \note This function is available for CAT1C CM0/CM7 core. 794 * 795 * \return 796 * Initialization status 797 * 798 * \note CM0+/CM7 <br/> 799 * The interrupt vector will be relocated only if the vector table was 800 * moved to __ramVectors in SRAM. Otherwise it is ignored. 801 * 802 *******************************************************************************/ 803 cy_en_sysint_status_t Cy_SysInt_InitExtIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr); 804 805 806 /******************************************************************************* 807 * Function Name: Cy_SysInt_InitIntIRQ 808 ****************************************************************************//** 809 * 810 * \brief Initializes the referenced internal interrupt by setting the priority and the 811 * interrupt vector. 812 * 813 * Use the CMSIS core function NVIC_EnableIRQ(config.intrSrc) to enable the interrupt. 814 * 815 * \param config 816 * Interrupt configuration structure 817 * 818 * \param userIsr 819 * Address of the ISR 820 * 821 * \note This function is available for CAT1C CM0/CM7 core. 822 * 823 * \return 824 * Initialization status 825 * 826 * \note CM0+/CM7 <br/> 827 * The interrupt vector will be relocated only if the vector table was 828 * moved to __ramVectors in SRAM. Otherwise it is ignored. 829 * 830 *******************************************************************************/ 831 cy_en_sysint_status_t Cy_SysInt_InitIntIRQ(const cy_stc_sysint_t* config, cy_israddress userIsr); 832 833 834 /******************************************************************************* 835 * Function Name: Cy_SysInt_SetSystemIrqVector 836 ****************************************************************************//** 837 * 838 * \brief Sets the User ISR vector for the System Interrupt. 839 * 840 * \param sysIntSrc 841 * Interrupt source 842 * 843 * \note This function is available for CAT1C CM0/CM7 core. 844 * 845 * \param userIsr 846 * Address of the ISR to set in the interrupt vector table 847 * 848 * \return none 849 * 850 *******************************************************************************/ 851 void Cy_SysInt_SetSystemIrqVector(cy_en_intr_t sysIntSrc, cy_israddress userIsr); 852 853 854 /******************************************************************************* 855 * Function Name: Cy_SysInt_GetSystemIrqVector 856 ****************************************************************************//** 857 * 858 * \brief Gets the address of the current user ISR vector for the System Interrupt. 859 * 860 * \param sysIntSrc 861 * Interrupt source 862 * 863 * \note This function is available for CAT1C CM0/CM7 core. 864 * 865 * \return 866 * Address of the ISR in the interrupt vector table 867 * 868 *******************************************************************************/ 869 cy_israddress Cy_SysInt_GetSystemIrqVector(cy_en_intr_t sysIntSrc); 870 871 872 /******************************************************************************* 873 * Function Name: Cy_SysInt_EnableSystemInt 874 ****************************************************************************//** 875 * 876 * \brief Enable system interrupt. 877 * 878 * \param sysIntSrc 879 * System interrupt source to be enabled. 880 * 881 * \note This function is available for CAT1C CM0/CM7 core. 882 * 883 * \return none 884 * 885 *******************************************************************************/ 886 void Cy_SysInt_EnableSystemInt(cy_en_intr_t sysIntSrc); 887 888 889 /******************************************************************************* 890 * Function Name: Cy_SysInt_DisableSystemInt 891 ****************************************************************************//** 892 * 893 * \brief Disable system interrupt. 894 * 895 * \param sysIntSrc 896 * System interrupt source to be disabled. 897 * 898 * \note This function is available for CAT1C CM0/CM7 core. 899 * 900 * \return none 901 * 902 *******************************************************************************/ 903 void Cy_SysInt_DisableSystemInt(cy_en_intr_t sysIntSrc); 904 #endif 905 906 /*************************************** 907 * Functions 908 ***************************************/ 909 910 /******************************************************************************* 911 * Function Name: Cy_SysInt_SetNmiSource 912 ****************************************************************************//** 913 * 914 * \brief Sets the interrupt source of the CPU core NMI. 915 * 916 * The interrupt source must be a positive number. Setting the value to 917 * "unconnected_IRQn" or "disconnected_IRQn" disconnects the interrupt source 918 * from the NMI. Depending on the device, the number of interrupt sources that 919 * can provide the NMI trigger signal to the core can vary. 920 * 921 * \param nmiNum 922 * NMI source number. 923 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI. 924 * CPUSS_ver1 allows only one source to trigger the core NMI and 925 * the specified NMI number is ignored. 926 * 927 * \param devIntrSrc 928 * Interrupt source. This parameter can either be of type cy_en_intr_t or IRQn_Type 929 * for CM0+/CM7 and CM4/CM33/CM55 respectively. 930 * 931 * \note CM0+ may call this function only at PC=0, CM4 may set its NMI handler at any PC. 932 * \note The CM0+ NMI is used for performing system calls that execute out of ROM. 933 * 934 * \funcusage 935 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 936 * 937 *******************************************************************************/ 938 939 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.3', 2, 'Only one prototype will be picked for compilation') 940 #if (((CY_CPU_CORTEX_M0P) || defined (CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 941 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_intr_t devIntrSrc); 942 #else 943 void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, IRQn_Type intrSrc); 944 #endif 945 946 /******************************************************************************* 947 * Function Name: Cy_SysInt_GetIntSourceNMI 948 ****************************************************************************//** 949 * 950 * \brief Gets the interrupt source of the CPU core NMI for the given NMI source 951 * number. 952 * 953 * \param nmiNum 954 * NMI source number. 955 * CPUSS_ver2 allows up to 4 sources to trigger the core NMI (i.e. #1, 2, 3, 4). 956 * CPUSS_ver1 allows only 1 source to trigger the core NMI (i.e #1). 957 * 958 * \return 959 * Interrupt Source. This parameter can either be of type cy_en_intr_t or IRQn_Type 960 * for CM0+/CM7 and CM4/CM33/CM55 respectively. 961 * 962 * \funcusage 963 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource 964 * 965 *******************************************************************************/ 966 #if (((CY_CPU_CORTEX_M0P) || defined(CY_IP_M7CPUSS) || defined (CY_DOXYGEN)) && !defined(CY_IP_M0SECCPUSS)) 967 cy_en_intr_t Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 968 #else 969 IRQn_Type Cy_SysInt_GetNmiSource(cy_en_sysint_nmi_t nmiNum); 970 #endif 971 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.3') 972 973 #if !(defined(CY_CPU_CORTEX_M0P) && (CY_CPU_CORTEX_M0P)) && !(defined(CY_IP_M7CPUSS)) 974 /******************************************************************************* 975 * Function Name: Cy_SysInt_SoftwareTrig 976 ****************************************************************************//** 977 * 978 * \brief Triggers an interrupt using software (Not applicable for CM0+). 979 * 980 * \param IRQn 981 * Interrupt source 982 * 983 * \funcusage 984 * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SoftwareTrig 985 * 986 * \note Only privileged software can enable unprivileged access to the 987 * Software Trigger Interrupt Register (STIR). This function is available for CAT1A, CAT1B and CAT1D devices. 988 * 989 * 990 *******************************************************************************/ 991 void Cy_SysInt_SoftwareTrig(IRQn_Type IRQn); 992 #endif 993 994 995 /** \} group_sysint_functions */ 996 997 /** \cond INTERNAL */ 998 999 /*************************************** 1000 * Deprecated functions 1001 ***************************************/ 1002 1003 /******************************************************************************* 1004 * Function Name: Cy_SysInt_GetState 1005 ****************************************************************************//** 1006 * 1007 * This function is deprecated. It invokes the NVIC_GetEnableIRQ() function. 1008 * 1009 *******************************************************************************/ 1010 #define Cy_SysInt_GetState NVIC_GetEnableIRQ 1011 1012 1013 /******************************************************************************* 1014 * Function Name: Cy_SysInt_SetIntSource 1015 ****************************************************************************//** 1016 * 1017 * This function is deprecated. It invokes the Cy_SysInt_SetInterruptSource() function. 1018 * 1019 *******************************************************************************/ 1020 #define Cy_SysInt_SetIntSource(intrSrc, devIntrSrc) Cy_SysInt_SetInterruptSource(intrSrc, devIntrSrc) 1021 1022 1023 /******************************************************************************* 1024 * Function Name: Cy_SysInt_GetIntSource 1025 ****************************************************************************//** 1026 * 1027 * This function is deprecated. It invokes the Cy_SysInt_GetInterruptSource() function. 1028 * 1029 *******************************************************************************/ 1030 #define Cy_SysInt_GetIntSource(intrSrc) Cy_SysInt_GetInterruptSource(intrSrc) 1031 1032 1033 /******************************************************************************* 1034 * Function Name: Cy_SysInt_SetIntSourceNMI 1035 ****************************************************************************//** 1036 * 1037 * This function is deprecated. It invokes the Cy_SysInt_SetNmiSource() function. 1038 * 1039 *******************************************************************************/ 1040 #define Cy_SysInt_SetIntSourceNMI(srcParam) Cy_SysInt_SetNmiSource(CY_SYSINT_NMI1, srcParam) 1041 1042 1043 /******************************************************************************* 1044 * Function Name: Cy_SysInt_GetIntSourceNMI 1045 ****************************************************************************//** 1046 * 1047 * This function is deprecated. It invokes the Cy_SysInt_GetNmiSource() function. 1048 * 1049 *******************************************************************************/ 1050 #define Cy_SysInt_GetIntSourceNMI() Cy_SysInt_GetNmiSource(CY_SYSINT_NMI1) 1051 1052 /** \endcond */ 1053 1054 #if defined(__cplusplus) 1055 } 1056 #endif 1057 1058 #endif /* defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS) */ 1059 1060 #endif /* CY_SYSINT_H */ 1061 1062 /** \} group_sysint */ 1063 1064 /* [] END OF FILE */ 1065
