1 /***************************************************************************//**
2 * \file cy_scb_i2c.h
3 * \version 3.20
4 *
5 * Provides I2C API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb_i2c
27 * \{
28 * Driver API for I2C Bus Peripheral
29 *
30 * I2C - The Inter-Integrated Circuit (I2C) bus is an industry-standard.
31 *
32 * The functions and other declarations used in this part of the driver are in
33 * cy_scb_i2c.h. You can also include cy_pdl.h to get access
34 * to all functions and declarations in the PDL.
35 *
36 * The I2C peripheral driver provides an API to implement I2C slave, master,
37 * or master-slave devices based on the SCB hardware block.
38 * I2C devices based on SCB hardware are compatible with I2C
39 * Standard-mode, Fast-mode, and Fast-mode Plus specifications as defined in
40 * the I2C-bus specification.
41 *
42 * Features:
43 * * An industry-standard I2C bus interface
44 * * Supports slave, master, and master-slave operation
45 * * Supports standard data rates of 100/400/1000 kbps
46 * * Hardware Address Match, multiple addresses
47 * * Wake from Deep Sleep on Address Match
48 *
49 * \note
50 * I2C supports clock stretching. This occurs when a slave device is not capable
51 * of processing data, it holds the SCL line by driving a '0'. The master device monitors
52 * the SCL line and detects it when it cannot generate a positive clock pulse ('1') on the
53 * SCL line. It then reacts by delaying the generation of a positive edge on the SCL line,
54 * effectively synchronizing with the slave device that is stretching the clock.
55 * Clock stretching can occur in the case of externally clocked address matching until the
56 * internally clocked logic takes over. The largest reason for clock stretching is when the
57 * master tries to write to the slave and the slave's RX FIFO is full, the slave will then
58 * clock stretch until the FIFO is no longer full. For more information on FIFO size and clock
59 * stretching see the architecture TRM.
60 ********************************************************************************
61 * \section group_scb_i2c_configuration Configuration Considerations
62 ********************************************************************************
63 * The I2C driver configuration can be divided to number of sequential
64 * steps listed below:
65 * * \ref group_scb_i2c_config
66 * * \ref group_scb_i2c_pins
67 * * \ref group_scb_i2c_clock
68 * * \ref group_scb_i2c_data_rate
69 * * \ref group_scb_i2c_mclk_sync
70 * * \ref group_scb_i2c_intr
71 * * \ref group_scb_i2c_enable
72 *
73 * \note
74 * I2C driver is built on top of the SCB hardware block. The SCB3 instance is
75 * used as an example for all code snippets. Modify the code to match your
76 * design.
77 *
78 ********************************************************************************
79 * \subsection group_scb_i2c_config Configure I2C
80 ********************************************************************************
81 * To set up the I2C driver, provide the configuration parameters in the
82 * \ref cy_stc_scb_i2c_config_t structure. Provide i2cMode to the select
83 * operation mode slave, master or master-slave. The useRxFifo and useTxFifo
84 * parameters specify if RX and TX FIFO is used during operation. Typically, both
85 * FIFOs should be enabled to reduce possibility of clock stretching. However,
86 * using RX FIFO has side effects that needs to be taken into account
87 * (see useRxFifo field description in \ref cy_stc_scb_i2c_config_t structure).
88 * For master modes, parameters lowPhaseDutyCycle, highPhaseDutyCycle and
89 * enableDigitalFilter can be used to define output data rate (refer to section
90 * \ref group_scb_i2c_data_rate for more information).
91 * For slave mode, provide the slaveAddress and slaveAddressMask. The other
92 * parameters are optional for operation.\n
93 * To initialize the driver, call \ref Cy_SCB_I2C_Init
94 * function providing a pointer to the populated \ref cy_stc_scb_i2c_config_t
95 * structure and the allocated \ref cy_stc_scb_i2c_context_t structure.
96 *
97 * \snippet scb/i2c_snippet/main.c I2C_CFG
98 *
99 * Set up I2C slave read and write buffer before enabling its
100 * operation using \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref
101 * Cy_SCB_I2C_SlaveConfigWriteBuf appropriately. Note that the master reads
102 * data from the slave read buffer and writes data into the slave write buffer.
103 *
104 * \snippet scb/i2c_snippet/main.c I2C_CFG_BUFFER
105 *
106 ********************************************************************************
107 * \subsection group_scb_i2c_pins Assign and Configure Pins
108 ********************************************************************************
109 * Only dedicated SCB pins can be used for I2C operation. The HSIOM
110 * register must be configured to connect dedicated SCB I2C pins to the
111 * SCB block. Also the I2C pins must be configured in Open-Drain, Drives Low mode
112 * (this pins configuration implies usage of external pull-up resistors):
113 *
114 * \snippet scb/i2c_snippet/main.c I2C_CFG_PINS
115 *
116 * \note
117 * The alternative pins configuration is Resistive Pull-ups which implies usage
118 * internal pull-up resistors. This configuration is not recommended because
119 * resistor value is fixed and cannot be used for all supported data rates.
120 * Refer to the device datasheet parameter RPULLUP for resistor value specifications.
121 *
122 ********************************************************************************
123 * \subsection group_scb_i2c_clock Assign Clock Divider
124 ********************************************************************************
125 * A clock source must be connected to the SCB block to oversample input and
126 * output signals, in this document this clock will be referred as clk_scb.
127 * You must use one of the 8-bit or 16-bit dividers. Use the \ref group_sysclk
128 * driver API to do this.
129 *
130 * \snippet scb/i2c_snippet/main.c I2C_CFG_ASSIGN_CLOCK
131 *
132 ********************************************************************************
133 * \subsection group_scb_i2c_data_rate Configure Data Rate
134 ********************************************************************************
135 * To get I2C slave operation with the desired data rate, the clk_scb must be
136 * fast enough to provide sufficient oversampling. Use the
137 * \ref group_sysclk driver API to do this.
138 *
139 * \snippet scb/i2c_snippet/main.c I2C_CFG_DATA_RATE_SLAVE
140 *
141 * To get I2C master operation with the desired data rate, the source clock
142 * frequency and SCL low and high phase duration must be configured. Use the
143 * \ref group_sysclk driver API to configure source clock frequency. Then call
144 * \ref Cy_SCB_I2C_SetDataRate to set the SCL low, high phase duration and
145 * digital filter. This function sets SCL low and high phase settings based on
146 * source clock frequency.
147 *
148 * \snippet scb/i2c_snippet/main.c I2C_CFG_DATA_RATE_MASTER
149 *
150 * Alternatively, the low, high phase and digital filter can be set directly
151 * using configuration structure \ref cy_stc_scb_i2c_config_t fields
152 * lowPhaseDutyCycle, highPhaseDutyCycle and enableDigitalFilter appropriately.\n
153 * <b>Refer to the technical reference manual (TRM) section I2C sub-section
154 * Oversampling and Bit Rate to get information how to configure I2C to run with
155 * the desired data rate.</b>
156 *
157 * \note
158 * For I2C slave, the analog filter is used for all supported data rates. \n
159 * For I2C master, the analog filter is used for Standard and Fast modes and the
160 * digital filter for Fast Plus mode.
161 *
162 ********************************************************************************
163 * \subsubsection group_scb_i2c_mclk_sync I2C Master Clock Synchronization
164 ********************************************************************************
165 * \note
166 * This info is applicable only for CAT1A devices having SCB IP version 1.
167 *
168 * The highPhaseDutyCycle counter does not start counting until the SCB detects
169 * that the SCL line is high. This is not the same as when the SCB sets the SCL high.
170 * The differences are explained by three delays:
171 * -# Output wire delay from SCB to I/O pin.
172 * -# I2C bus tR delay.
173 * -# Input wire delay (filters and synchronization).
174 * .
175 * \image html i2c_scl_turnaround_path.png
176 *
177 * If the above three delays combined are greater than one clk_scb cycle, then
178 * the high phase of the SCL will be extended. This may cause the actual data rate
179 * on the I2C bus to be slower than expected.
180 * This can be avoided by:
181 * * Decreasing the pull-up resistor or decreasing the bus capacitance to reduce tR.
182 * * Reducing the highPhaseDutyCycle value in the \ref cy_stc_scb_i2c_config_t structure.
183 *
184 ********************************************************************************
185 * \subsection group_scb_i2c_intr Configure Interrupt
186 ********************************************************************************
187 * The interrupt is mandatory for I2C operation. The exception is the when only
188 * the \ref group_scb_i2c_master_low_level_functions functions are used.
189 * The driver provides three interrupt functions: \ref Cy_SCB_I2C_Interrupt,
190 * \ref Cy_SCB_I2C_SlaveInterrupt, and \ref Cy_SCB_I2C_MasterInterrupt. One of
191 * these functions must be called in the interrupt handler for the selected SCB
192 * instance. Call \ref Cy_SCB_I2C_SlaveInterrupt when I2C is configured to
193 * operate as a slave, \ref Cy_SCB_I2C_MasterInterrupt when I2C is configured
194 * to operate as a master and \ref Cy_SCB_I2C_Interrupt when I2C is configured
195 * to operate as master and slave. Using the slave- or master-specific interrupt
196 * function allows reducing the flash consumed by the I2C driver. Also this
197 * interrupt must be enabled in the NVIC otherwise it will not work.
198 * \note
199 * The I2C driver documentation refers to the \ref Cy_SCB_I2C_Interrupt function
200 * when interrupt processing is mandatory for the operation. This is done to
201 * simplify the readability of the driver's documentation. The application should
202 * call the slave- or master-specific interrupt functions \ref Cy_SCB_I2C_SlaveInterrupt
203 * or \ref Cy_SCB_I2C_MasterInterrupt, when appropriate.
204 *
205 * \snippet scb/i2c_snippet/main.c I2C_INTR_A
206 * \snippet scb/i2c_snippet/main.c I2C_INTR_B
207 *
208 ********************************************************************************
209 * \subsection group_scb_i2c_enable Enable I2C
210 ********************************************************************************
211 * Finally, enable the I2C operation by calling \ref Cy_SCB_I2C_Enable. Then I2C
212 * slave starts respond to the assigned address and I2C master ready to execute
213 * transfers.
214 *
215 * \snippet scb/i2c_snippet/main.c I2C_ENABLE
216 *
217 * \section group_scb_i2c_use_cases Common Use Cases
218 *
219 ********************************************************************************
220 * \subsection group_scb_i2c_master_mode Master Operation
221 ********************************************************************************
222 * The master API is divided into two categories:
223 * \ref group_scb_i2c_master_high_level_functions and
224 * \ref group_scb_i2c_master_low_level_functions. Therefore, there are two
225 * methods for initiating I2C master transactions using either <b>Low-Level or
226 * High-Level</b> API. These two methods are described below. Only one method
227 * should be used at a time. <b>They should not be mixed.</b>
228 *
229 ********************************************************************************
230 * \subsubsection group_scb_i2c_master_hl Use High-Level Functions
231 ********************************************************************************
232 * Call \ref Cy_SCB_I2C_MasterRead or \ref Cy_SCB_I2C_MasterWrite to
233 * communicate with the slave. These functions do not block and only start a
234 * transaction. After a transaction starts, the \ref Cy_SCB_I2C_Interrupt
235 * handles further data transaction until its completion (successfully or
236 * with error occurring). To monitor the transaction,
237 * use \ref Cy_SCB_I2C_MasterGetStatus or register callback function using
238 * \ref Cy_SCB_I2C_RegisterEventCallback to be notified about
239 * \ref group_scb_i2c_macros_callback_events.
240 *
241 * \snippet scb/i2c_snippet/main.c I2C_MASTER_WRITE_READ_INT
242 *
243 ********************************************************************************
244 * \subsubsection group_scb_i2c_master_ll Use Low-Level Functions
245 ********************************************************************************
246 * Call \ref Cy_SCB_I2C_MasterSendStart to generate a start, send an address
247 * with the Read/Write direction bit, and receive acknowledgment. After the
248 * address is ACKed by the slave, the transaction can be continued by calling
249 * \ref Cy_SCB_I2C_MasterReadByte or \ref Cy_SCB_I2C_MasterWriteByte depending
250 * on its direction. These functions handle one byte per call. Therefore,
251 * they should be called for each byte in the transaction. Note that for the
252 * Read transaction, the last byte must be NAKed. To complete the current
253 * transaction, call \ref Cy_SCB_I2C_MasterSendStop or call
254 * \ref Cy_SCB_I2C_MasterSendReStart to complete the current transaction and
255 * start a new one. Typically, do a restart to change the transaction
256 * direction without releasing the bus from the master control.
257 * The Low-Level functions are blocking and do not require calling
258 * \ref Cy_SCB_I2C_Interrupt inside the interrupt handler. Using these
259 * functions requires extensive knowledge of the I2C protocol to execute
260 * transactions correctly.
261 *
262 * <b>Master Write Operation</b>
263 * \snippet scb/i2c_snippet/main.c I2C_MASTER_WRITE_MANUAL
264 *
265 * <b>Master Read Operation</b>
266 * \snippet scb/i2c_snippet/main.c I2C_MASTER_READ_MANUAL
267 *
268 ********************************************************************************
269 * \subsection group_scb_i2c_slave Slave Operation
270 ********************************************************************************
271 * Slave operation requires the \ref Cy_SCB_I2C_Interrupt be
272 * called inside the interrupt handler. The read and write buffers must
273 * be provided for the slave to enable communication with the master. Use
274 * \ref Cy_SCB_I2C_SlaveConfigReadBuf and \ref Cy_SCB_I2C_SlaveConfigWriteBuf
275 * for this purpose. Note that after transaction completion the buffer must be
276 * configured again. Otherwise, the same buffer is used starting from the point
277 * where the master stopped a previous transaction.
278 * For example: The read buffer is configured to be 10 bytes and the master reads
279 * 8 bytes. If the read buffer is not configured again, the next master read
280 * will start from the 9th byte.
281 * To monitor the transaction status, use \ref Cy_SCB_I2C_SlaveGetStatus or
282 * use \ref Cy_SCB_I2C_RegisterEventCallback to register a callback function
283 * to be notified about \ref group_scb_i2c_macros_callback_events.
284 *
285 * <b>Get Slave Events Notification</b>
286 * \snippet scb/i2c_snippet/main.c I2C_SLAVE_REG_CALLBACK
287 * \snippet scb/i2c_snippet/main.c I2C_SLAVE_NOTIFICATION
288 *
289 * <b>Polling Slave Completion Events</b>
290 * \snippet scb/i2c_snippet/main.c I2C_SLAVE_POLLING
291 *
292 * \note
293 * All slave API (except \ref Cy_SCB_I2C_SlaveAbortRead and
294 * \ref Cy_SCB_I2C_SlaveAbortWrite) <b>are not interrupt-protected</b> and to
295 * prevent a race condition, they should be protected from the I2C interruption
296 * in the place where they are called. The code snippet Polling Slave
297 * Completion Events above shows how to prevent a race condition when detect
298 * transfer completion and update I2C slave write buffer.
299 * The simple example of race condition is: application updates slave read
300 * buffer the I2C master starts read transfer. The I2C interrupts read buffer
301 * update and I2C interrupt loads current read buffer content in the TX FIFO .
302 * After I2C interrupt returns the application updates remaining part of the read
303 * buffer. As a result the mater read partly updated buffer.
304 *
305 ********************************************************************************
306 * \section group_scb_i2c_lp Low Power Support
307 ********************************************************************************
308 * The I2C driver provides callback functions to handle power mode transition.
309 * The callback \ref Cy_SCB_I2C_DeepSleepCallback must be called
310 * during execution of \ref Cy_SysPm_CpuEnterDeepSleep \ref Cy_SCB_I2C_HibernateCallback
311 * must be called during execution of \ref Cy_SysPm_SystemEnterHibernate. To trigger the
312 * callback execution, the callback must be registered before calling the
313 * power mode transition function. Refer to \ref group_syspm driver for more
314 * information about power mode transitions and callback registration.
315 *
316 * \note
317 * Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
318 * For proper operation, when the I2C slave is configured to be a wakeup
319 * source from Deep Sleep mode, the \ref Cy_SCB_I2C_DeepSleepCallback must be
320 * copied and modified. Refer to the function description to get the details.
321 *
322 * \defgroup group_scb_i2c_macros Macros
323 * \defgroup group_scb_i2c_functions Functions
324 * \{
325 * \defgroup group_scb_i2c_general_functions General
326 * \defgroup group_scb_i2c_slave_functions Slave
327 * \defgroup group_scb_i2c_master_high_level_functions Master High-Level
328 * \defgroup group_scb_i2c_master_low_level_functions Master Low-Level
329 * \defgroup group_scb_i2c_interrupt_functions Interrupt
330 * \defgroup group_scb_i2c_low_power_functions Low Power Callbacks
331 * \}
332 * \defgroup group_scb_i2c_data_structures Data Structures
333 * \defgroup group_scb_i2c_enums Enumerated Types
334 */
335
336 #if !defined(CY_SCB_I2C_H)
337 #define CY_SCB_I2C_H
338
339 #include "cy_device.h"
340
341 #if (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB))
342
343 #include "cy_scb_common.h"
344
345 #if defined(__cplusplus)
346 extern "C" {
347 #endif
348
349 /*******************************************************************************
350 * Enumerated Types
351 *******************************************************************************/
352
353 /**
354 * \addtogroup group_scb_i2c_enums
355 * \{
356 */
357
358 /** I2C status codes */
359 typedef enum
360 {
361 /** Operation completed successfully */
362 CY_SCB_I2C_SUCCESS = 0U,
363
364 /** One or more of input parameters are invalid */
365 CY_SCB_I2C_BAD_PARAM = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 1U),
366
367 /**
368 * The master is not ready to start a new transaction.
369 * Either the master is still processing a previous transaction or in the
370 * master-slave mode, the slave operation is in progress.
371 */
372 CY_SCB_I2C_MASTER_NOT_READY = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 2U),
373
374 /**
375 * The master operation timed out before completing. Applicable only for
376 * the \ref group_scb_i2c_master_low_level_functions functions.
377 */
378 CY_SCB_I2C_MASTER_MANUAL_TIMEOUT = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 3U),
379
380 /** The slave NACKed the address. Applicable only for the
381 * \ref group_scb_i2c_master_low_level_functions functions.
382 */
383 CY_SCB_I2C_MASTER_MANUAL_ADDR_NAK = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 4U),
384
385 /** The slave NACKed the data byte. Applicable only for the
386 * \ref group_scb_i2c_master_low_level_functions.
387 */
388 CY_SCB_I2C_MASTER_MANUAL_NAK = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 5U),
389
390 /**
391 * The master lost arbitration, the transaction was aborted. Applicable only
392 * for the \ref group_scb_i2c_master_low_level_functions functions.
393 */
394 CY_SCB_I2C_MASTER_MANUAL_ARB_LOST = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 6U),
395
396 /**
397 * The master detected an erroneous start or stop, the transaction was
398 * aborted. Applicable only for the
399 * \ref group_scb_i2c_master_low_level_functions functions.
400 */
401 CY_SCB_I2C_MASTER_MANUAL_BUS_ERR = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 7U),
402
403 /**
404 * The master transaction was aborted and the slave transaction is on-going
405 * because the slave was addressed before the master generated a start.
406 * Applicable only for the \ref group_scb_i2c_master_low_level_functions
407 * functions.
408 */
409 CY_SCB_I2C_MASTER_MANUAL_ABORT_START = (CY_SCB_ID | CY_PDL_STATUS_ERROR | CY_SCB_I2C_ID | 8U)
410 } cy_en_scb_i2c_status_t;
411
412 /** I2C Operation Modes */
413 typedef enum
414 {
415 CY_SCB_I2C_SLAVE = 1U, /**< Configures SCB for I2C Slave operation */
416 CY_SCB_I2C_MASTER = 2U, /**< Configures SCB for I2C Master operation */
417 CY_SCB_I2C_MASTER_SLAVE = 3U, /**< Configures SCB for I2C Master-Slave operation */
418 } cy_en_scb_i2c_mode_t;
419
420 /** I2C Transaction Direction */
421 typedef enum
422 {
423 CY_SCB_I2C_WRITE_XFER = 0U, /**< Current transaction is Write */
424 CY_SCB_I2C_READ_XFER = 1U, /**< Current transaction is Read */
425 } cy_en_scb_i2c_direction_t;
426
427 /** I2C Command ACK / NAK */
428 typedef enum
429 {
430 CY_SCB_I2C_ACK, /**< Send ACK to current byte */
431 CY_SCB_I2C_NAK, /**< Send NAK to current byte */
432 } cy_en_scb_i2c_command_t;
433 /** \} group_scb_i2c_enums */
434
435
436 /*******************************************************************************
437 * Type Definitions
438 *******************************************************************************/
439
440 /**
441 * \addtogroup group_scb_i2c_data_structures
442 * \{
443 */
444
445 /**
446 * Provides the typedef for the callback function called in the
447 * \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of
448 * \ref group_scb_i2c_macros_callback_events.
449 */
450 typedef void (* cy_cb_scb_i2c_handle_events_t)(uint32_t event);
451
452 /**
453 * Provides the typedef for the callback function called in the
454 * \ref Cy_SCB_I2C_Interrupt to notify the user about occurrences of
455 * \ref group_scb_i2c_macros_addr_callback_events.
456 * This callback must return a decision to ACK (continue transaction) or
457 * NAK (end transaction) the received address.
458 * Note if the slave is configured to accept an address in RX FIFO, it must read
459 * from it using the \ref Cy_SCB_ReadRxFifo function.
460 */
461 typedef cy_en_scb_i2c_command_t (* cy_cb_scb_i2c_handle_addr_t)(uint32_t event);
462
463 /** I2C configuration structure */
464 typedef struct cy_stc_scb_i2c_config
465 {
466 /** Specifies the mode of operation */
467 cy_en_scb_i2c_mode_t i2cMode;
468
469 /**
470 * The SCB provides an RX FIFO in hardware (consult the selected device
471 * datasheet to get the actual FIFO size). The useRxFifo field defines
472 * how the driver firmware reads data from the RX FIFO:
473 * * If this option is enabled, the hardware is configured to automatically
474 * ACK incoming data, and interrupt is enabled to take data out of the RX
475 * FIFO when it has some number of bytes (typically, when it is half full).
476 * * If this option is disabled, the interrupt is enabled to take data out of
477 * the RX FIFO when a byte is available. Also, hardware does not
478 * automatically ACK the data. Firmware must tell the hardware to ACK
479 * the byte (so each byte requires interrupt processing).
480 * \n <b>Typically, this option should be enabled</b> to configure hardware to
481 * automatically ACK incoming data. Otherwise hardware might not get the command
482 * to ACK or NACK a byte fast enough, and clock stretching is applied
483 * (the transaction is delayed) until the command is set. When this option is
484 * enabled, the number of interrupts required to process the transaction
485 * is significantly reduced because several bytes are handled at once.
486 * \n <b>However, there is a side effect:</b>
487 * * For master mode, the drawback is that the master may receive more
488 * data than desired due to the interrupt latency. An interrupt fires
489 * when the second-to-last byte has been received. This interrupt tells
490 * the hardware to stop receiving data. If the latency of this interrupt
491 * is longer than one transaction of the byte on the I2C bus, then the
492 * hardware automatically ACKs the following bytes until the interrupt
493 * is serviced or the RX FIFO becomes full.
494 * * For slave mode, the drawback is that the slave only NACKs
495 * the master when the RX FIFO becomes full, NOT when the slave write
496 * firmware buffer becomes full.
497 * \n In either master or slave mode, all received extra bytes are dropped.
498 * \note The useRxFifo option is not available if acceptAddrInFifo is true.
499 */
500 bool useRxFifo;
501
502 /**
503 * The SCB provides a TX FIFO in hardware (consult the selected device
504 * datasheet to get the actual FIFO size). The useTxFifo option defines how the
505 * driver firmware loads data into the TX FIFO:
506 * * If this option is enabled, the TX FIFO is fully loaded with data and the
507 * interrupt is enabled to keep the TX FIFO loaded until the end of the transaction.
508 * * If this option is disabled, a single byte is loaded into the TX FIFO and
509 * the interrupt enabled to load the next byte when the TX FIFO becomes empty
510 * (so each byte requires interrupt processing).
511 * \n <b>Typically, this option should be enabled</b> to keep the TX FIFO loaded with
512 * data and reduce the probability of clock stretching. When there is no data
513 * to transfer, clock stretching is applied (the transaction is delayed) until
514 * the data is loaded. When this option is enabled, the number of interrupts required
515 * to process the transaction is significantly reduced because several
516 * bytes are handled at once.
517 * \n <b>The drawback of enabling useTxFifo</b> is that the abort operation clears
518 * the TX FIFO. The TX FIFO clear operation also clears the shift
519 * register. As a result the shifter may be cleared in the middle of a byte
520 * transaction, corrupting it. The remaining bits to transaction within the
521 * corrupted byte are complemented with 1s. If this is an issue,
522 * then do not enable this option.
523 */
524 bool useTxFifo;
525
526 /**
527 * The 7-bit right justified slave address, used only for the slave mode
528 */
529 uint8_t slaveAddress;
530
531 /**
532 * The slave address mask is used to mask bits of the slave address during
533 * the address match procedure (it is used only for the slave mode).
534 * Bit 0 of the address mask corresponds to the
535 * read/write direction bit and is always a do not care in the address match
536 * therefore must be set 0. Bit value 0 - excludes bit from address
537 * comparison. Bit value 1 - the bit needs to match with the corresponding
538 * bit of the I2C slave address.
539 */
540 uint8_t slaveAddressMask;
541
542 /**
543 * True - the slave address is accepted in the RX FIFO, false - the slave
544 * addresses are not accepted in the RX FIFO
545 */
546 bool acceptAddrInFifo;
547
548 /**
549 * True - accept the general call address; false - ignore the general
550 * call address.
551 */
552 bool ackGeneralAddr;
553
554 /**
555 * When set, the slave will wake the device from Deep Sleep on an address
556 * match (the device datasheet must be consulted to determine which SCBs
557 * support this mode)
558 */
559 bool enableWakeFromSleep;
560
561 /**
562 * Enables a digital 3-tap median filter to be applied to the inputs
563 * of filter glitches on the lines.
564 */
565 bool enableDigitalFilter;
566
567 /**
568 * The number of SCB clock cycles in the low phase of SCL. Only applicable
569 * in master modes. The valid range is 7 to 16.
570 */
571 uint32_t lowPhaseDutyCycle;
572
573 /**
574 * The number of SCB clock cycles in the high phase of SCL. Only applicable
575 * in master modes. The valid range is 5 to 16.
576 * Please refer to the section \ref group_scb_i2c_mclk_sync for more information.
577 */
578 uint32_t highPhaseDutyCycle;
579
580 } cy_stc_scb_i2c_config_t;
581
582 /** I2C context structure.
583 * All fields for the context structure are internal. Firmware never reads or
584 * writes these values. Firmware allocates the structure and provides the
585 * address of the structure to the driver in function calls. Firmware must
586 * ensure that the defined instance of this structure remains in scope
587 * while the drive is in use.
588 */
589 typedef struct cy_stc_scb_i2c_context
590 {
591 /** \cond INTERNAL */
592 bool useRxFifo; /**< Stores RX FIFO configuration */
593 bool useTxFifo; /**< Stores TX FIFO configuration */
594
595 volatile uint32_t state; /**< The driver state */
596
597 volatile uint32_t masterStatus; /**< The master status */
598 bool masterPause; /**< Stores how the master ends the transaction */
599 bool masterRdDir; /**< The direction of the master transaction */
600
601 uint8_t *masterBuffer; /**< The pointer to the master buffer (either for a transmit or a receive operation) */
602 uint32_t masterBufferSize; /**< The current master buffer size */
603 volatile uint32_t masterBufferIdx; /**< The current location in the master buffer */
604 volatile uint32_t masterNumBytes; /**< The number of bytes to send or receive */
605
606 volatile uint32_t slaveStatus; /**< The slave status */
607 volatile bool slaveRdBufEmpty; /**< Tracks slave Read buffer empty event */
608
609 uint8_t *slaveTxBuffer; /**< The pointer to the slave transmit buffer (a master reads from it) */
610 uint32_t slaveTxBufferSize; /**< The current slave transmit buffer size */
611 volatile uint32_t slaveTxBufferIdx; /**< The current location in the slave buffer */
612 volatile uint32_t slaveTxBufferCnt; /**< The number of transferred bytes */
613
614 uint8_t *slaveRxBuffer; /**< The pointer to the slave receive buffer (a master writes into it) */
615 uint32_t slaveRxBufferSize; /**< The current slave receive buffer size */
616 volatile uint32_t slaveRxBufferIdx; /**< The current location in the slave buffer */
617
618 /**
619 * The pointer to an event callback that is called when any of
620 * \ref group_scb_i2c_macros_callback_events occurs
621 */
622 cy_cb_scb_i2c_handle_events_t cbEvents;
623
624 /**
625 * The pointer to an address callback that is called when any of
626 * \ref group_scb_i2c_macros_addr_callback_events occurs (applicable only
627 * for the slave)
628 */
629 cy_cb_scb_i2c_handle_addr_t cbAddr;
630
631 /** \endcond */
632 } cy_stc_scb_i2c_context_t;
633
634 /** The I2C Master transfer structure */
635 typedef struct cy_stc_scb_i2c_master_xfer_config
636 {
637 /** The 7-bit right justified slave address to communicate with */
638 uint8_t slaveAddress;
639
640 /**
641 * The pointer to the buffer for data to read from the slave or
642 * data to write into the slave
643 */
644 uint8_t *buffer;
645
646 /** The size of the buffer */
647 uint32_t bufferSize;
648
649 /**
650 * The transfer operation is pending - the stop condition will not
651 * be generated.
652 * A new transfer starts from start condition and ends
653 * with or without stop condition. The stop condition releases I2C
654 * bus from master control. When stop is not generated master keeps
655 * bus control (transfer is pending) and can issue the next transfer
656 * using restart condition instead of start. The I2C driver
657 * automatically generates start or restart condition depends on
658 * current state.
659 * Note if master lost arbitration during transfer it stops control
660 * the bus and does not send/receive data or generate stop condition - the
661 * transfer ends.
662 */
663 bool xferPending;
664 } cy_stc_scb_i2c_master_xfer_config_t;
665 /** \} group_scb_i2c_data_structures */
666
667
668 /*******************************************************************************
669 * Function Prototypes
670 *******************************************************************************/
671
672 /**
673 * \addtogroup group_scb_i2c_general_functions
674 * \{
675 */
676 cy_en_scb_i2c_status_t Cy_SCB_I2C_Init(CySCB_Type *base, cy_stc_scb_i2c_config_t const *config,
677 cy_stc_scb_i2c_context_t *context);
678 void Cy_SCB_I2C_DeInit(CySCB_Type *base);
679 __STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base);
680 void Cy_SCB_I2C_Disable(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
681
682 uint32_t Cy_SCB_I2C_SetDataRate(CySCB_Type *base, uint32_t dataRateHz, uint32_t scbClockHz);
683 uint32_t Cy_SCB_I2C_GetDataRate(CySCB_Type const *base, uint32_t scbClockHz);
684
685 __STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress(CySCB_Type *base, uint8_t addr);
686 __STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const *base);
687 __STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask);
688 __STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base);
689
690 __STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy(CySCB_Type const *base);
691
692 __STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle (CySCB_Type *base, uint32_t clockCycles);
693 __STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles);
694 #if (((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=3)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
695 void Cy_SCB_I2C_SetStretchThreshold(CySCB_Type const *base, uint32_t value);
696 uint32_t Cy_SCB_I2C_GetStretchCount(CySCB_Type const *base);
697 bool Cy_SCB_I2C_IsStretchDetected(CySCB_Type const *base);
698 bool Cy_SCB_I2C_IsSyncDetected(CySCB_Type const *base);
699 bool Cy_SCB_I2C_IsStretching(CySCB_Type const *base);
700 #endif /* CY_IP_MXSCB_VERSION */
701
702 /** \} group_scb_i2c_general_functions */
703
704 /**
705 * \addtogroup group_scb_i2c_slave_functions
706 * \{
707 */
708 void Cy_SCB_I2C_SlaveConfigReadBuf (CySCB_Type const *base, uint8_t *buffer, uint32_t size,
709 cy_stc_scb_i2c_context_t *context);
710 void Cy_SCB_I2C_SlaveAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
711 void Cy_SCB_I2C_SlaveConfigWriteBuf(CySCB_Type const *base, uint8_t *buffer, uint32_t size,
712 cy_stc_scb_i2c_context_t *context);
713 void Cy_SCB_I2C_SlaveAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
714
715 uint32_t Cy_SCB_I2C_SlaveGetStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
716 uint32_t Cy_SCB_I2C_SlaveClearReadStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t *context);
717 uint32_t Cy_SCB_I2C_SlaveClearWriteStatus(CySCB_Type const *base, cy_stc_scb_i2c_context_t *context);
718
719 uint32_t Cy_SCB_I2C_SlaveGetReadTransferCount (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
720 uint32_t Cy_SCB_I2C_SlaveGetWriteTransferCount(CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
721 /** \} group_scb_i2c_slave_functions */
722
723 /**
724 * \addtogroup group_scb_i2c_master_high_level_functions
725 * \{
726 */
727 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t *xferConfig,
728 cy_stc_scb_i2c_context_t *context);
729 void Cy_SCB_I2C_MasterAbortWrite (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
730 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead (CySCB_Type *base, cy_stc_scb_i2c_master_xfer_config_t* xferConfig,
731 cy_stc_scb_i2c_context_t *context);
732 void Cy_SCB_I2C_MasterAbortRead (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
733 uint32_t Cy_SCB_I2C_MasterGetStatus (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
734 uint32_t Cy_SCB_I2C_MasterGetTransferCount (CySCB_Type const *base, cy_stc_scb_i2c_context_t const *context);
735 /** \} group_scb_i2c_master_low_high_functions */
736
737 /**
738 * \addtogroup group_scb_i2c_master_low_level_functions
739 * \{
740 */
741 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStart (CySCB_Type *base, uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
742 uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
743 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base, uint32_t address, cy_en_scb_i2c_direction_t bitRnW,
744 uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
745 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendStop (CySCB_Type *base,uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
746 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterReadByte (CySCB_Type *base, cy_en_scb_i2c_command_t ackNack, uint8_t *byte,
747 uint32_t timeoutMs, cy_stc_scb_i2c_context_t *context);
748 cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWriteByte (CySCB_Type *base, uint8_t byte, uint32_t timeoutMs,
749 cy_stc_scb_i2c_context_t *context);
750 /** \} group_scb_i2c_master_low_level_functions */
751
752 /**
753 * \addtogroup group_scb_i2c_interrupt_functions
754 * \{
755 */
756 void Cy_SCB_I2C_Interrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
757 void Cy_SCB_I2C_SlaveInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
758 void Cy_SCB_I2C_MasterInterrupt (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
759
760 __STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base, cy_cb_scb_i2c_handle_events_t callback,
761 cy_stc_scb_i2c_context_t *context);
762 __STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback (CySCB_Type const *base, cy_cb_scb_i2c_handle_addr_t callback,
763 cy_stc_scb_i2c_context_t *context);
764 /** \} group_scb_i2c_interrupt_functions */
765
766 /**
767 * \addtogroup group_scb_i2c_low_power_functions
768 * \{
769 */
770 cy_en_syspm_status_t Cy_SCB_I2C_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
771 cy_en_syspm_status_t Cy_SCB_I2C_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
772 /** \} group_scb_i2c_low_power_functions */
773
774
775 /*******************************************************************************
776 * API Constants
777 *******************************************************************************/
778
779 /**
780 * \addtogroup group_scb_i2c_macros
781 * \{
782 */
783
784 /**
785 * \defgroup group_scb_i2c_macros_slave_status I2C Slave Status
786 * Macros to check current I2C slave status returned by
787 * \ref Cy_SCB_I2C_SlaveGetStatus function. Each I2C slave status is encoded
788 * in a separate bit, therefore multiple bits may be set to indicate the
789 * current status.
790 * \{
791 */
792 /** There is a read transaction in progress */
793 #define CY_SCB_I2C_SLAVE_RD_BUSY (0x00000001UL)
794
795 /**
796 * All read data has been loaded into the TX FIFO, applicable only if
797 * the TX FIFO is used
798 */
799 #define CY_SCB_I2C_SLAVE_RD_IN_FIFO (0x00000002UL)
800
801 /**
802 * The master has finished reading data from the slave
803 */
804 #define CY_SCB_I2C_SLAVE_RD_CMPLT (0x00000004UL)
805
806 /**
807 * Set when the master tried to read more bytes than available in the configured
808 * read buffer. The slave is not able to finish the transaction and sends
809 * \ref CY_SCB_I2C_DEFAULT_TX.
810 */
811 #define CY_SCB_I2C_SLAVE_RD_UNDRFL (0x00000008UL)
812
813 /** There is a write transaction in progress */
814 #define CY_SCB_I2C_SLAVE_WR_BUSY (0x00000010UL)
815
816 /**
817 * The master has finished writing data into the slave
818 */
819 #define CY_SCB_I2C_SLAVE_WR_CMPLT (0x00000020UL)
820
821 /**
822 * The master attempted to write more bytes than space available in the
823 * configured Write buffer. Note that all subsequent bytes are dropped.
824 */
825 #define CY_SCB_I2C_SLAVE_WR_OVRFL (0x00000040UL)
826
827 /** The slave lost arbitration, and the transaction was aborted */
828 #define CY_SCB_I2C_SLAVE_ARB_LOST (0x00000080UL)
829
830 /**
831 * The slave captured an error on the bus during a master transaction (source
832 * of error is misplaced Start or Stop).
833 */
834 #define CY_SCB_I2C_SLAVE_BUS_ERR (0x00000100UL)
835 /** \} group_scb_i2c_macros_slave_status */
836
837 /**
838 * \defgroup group_scb_i2c_macros_master_status I2C Master Status
839 * Macros to check current I2C master status returned by
840 * \ref Cy_SCB_I2C_MasterGetStatus function. Each I2C master status is encoded
841 * in a separate bit, therefore multiple bits may be set to indicate the
842 * current status.
843 * \{
844 */
845
846 /**
847 * The master is busy executing operation started by \ref Cy_SCB_I2C_MasterRead
848 * or \ref Cy_SCB_I2C_MasterWrite
849 */
850 #define CY_SCB_I2C_MASTER_BUSY (0x00010000UL)
851
852 /**
853 * All Write data has been loaded into the TX FIFO
854 */
855 #define CY_SCB_I2C_MASTER_WR_IN_FIFO (0x00020000UL)
856
857 /** The slave NACKed the address. */
858 #define CY_SCB_I2C_MASTER_ADDR_NAK (0x00100000UL)
859
860 /** Write completed before all bytes were sent (last byte was NAKed)
861 */
862 #define CY_SCB_I2C_MASTER_DATA_NAK (0x00200000UL)
863
864 /** The master lost arbitration, the transaction was aborted */
865 #define CY_SCB_I2C_MASTER_ARB_LOST (0x00400000UL)
866
867 /**
868 * The master detected an erroneous start or stop, the transaction was aborted
869 */
870 #define CY_SCB_I2C_MASTER_BUS_ERR (0x00800000UL)
871
872 /**
873 * The master transaction was aborted and the slave transaction is on-going
874 * because the slave was addressed before the master generated a start
875 */
876 #define CY_SCB_I2C_MASTER_ABORT_START (0x01000000UL)
877 /** \} group_scb_i2c_macros_master_status */
878
879 /**
880 * \defgroup group_scb_i2c_macros_callback_events I2C Callback Events
881 * \{
882 * Macros to check I2C events passed by \ref cy_cb_scb_i2c_handle_events_t callback.
883 * Each event is encoded in a separate bit, and therefore it is possible to
884 * notify about multiple events.
885 */
886 /**
887 * Indicates that the slave was addressed and the master wants to read data.
888 * This event can be used to configure the slave Read buffer.
889 */
890 #define CY_SCB_I2C_SLAVE_READ_EVENT (0x00000001UL)
891
892 /**
893 * Indicates that the slave was addressed and the master wants to write data.
894 * This event can be used to configure the slave Write buffer.
895 */
896 #define CY_SCB_I2C_SLAVE_WRITE_EVENT (0x00000002UL)
897
898 /**
899 * All slave data from the configured Read buffer has been loaded into the
900 * TX FIFO. The content of the Read buffer can be modified. Applicable only
901 * if the TX FIFO is used.
902 */
903 #define CY_SCB_I2C_SLAVE_RD_IN_FIFO_EVENT (0x00000004UL)
904
905 /**
906 * The master has read all data out of the configured Read buffer.
907 * This event can be used to configure the next Read buffer. If the buffer
908 * remains empty, the \ref CY_SCB_I2C_DEFAULT_TX bytes are returned to the master.
909 */
910 #define CY_SCB_I2C_SLAVE_RD_BUF_EMPTY_EVENT (0x00000008UL)
911
912 /**
913 * Indicates the master completed reading from the slave (set by the master NAK
914 * or Stop)
915 */
916 #define CY_SCB_I2C_SLAVE_RD_CMPLT_EVENT (0x00000010UL)
917
918 /**
919 * Indicates the master completed writing to the slave (set by the master Stop
920 * or Restart)
921 */
922 #define CY_SCB_I2C_SLAVE_WR_CMPLT_EVENT (0x00000020UL)
923
924 /**
925 * Indicates the I2C hardware detected an error.
926 * Check \ref Cy_SCB_I2C_SlaveGetStatus to determine the source of the error.
927 */
928 #define CY_SCB_I2C_SLAVE_ERR_EVENT (0x00000040UL)
929
930 /**
931 * All data specified by \ref Cy_SCB_I2C_MasterWrite has been loaded
932 * into the TX FIFO. The content of the master write buffer can be modified.
933 * Applicable only if the TX FIFO is used.
934 */
935 #define CY_SCB_I2C_MASTER_WR_IN_FIFO_EVENT (0x00010000UL)
936
937 /** The master write started by \ref Cy_SCB_I2C_MasterWrite is complete */
938 #define CY_SCB_I2C_MASTER_WR_CMPLT_EVENT (0x00020000UL)
939
940 /** The master read started by \ref Cy_SCB_I2C_MasterRead is complete */
941 #define CY_SCB_I2C_MASTER_RD_CMPLT_EVENT (0x00040000UL)
942
943 /**
944 * Indicates the I2C hardware has detected an error. It occurs together with
945 * \ref CY_SCB_I2C_MASTER_RD_CMPLT_EVENT or \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT
946 * depends on the direction of the transfer.
947 * Check \ref Cy_SCB_I2C_MasterGetStatus to determine the source of the error.
948 */
949 #define CY_SCB_I2C_MASTER_ERR_EVENT (0x00080000UL)
950 /** \} group_scb_i2c_macros_callback_events */
951
952 /**
953 * \defgroup group_scb_i2c_macros_addr_callback_events I2C Address Callback Events
954 * Macros to check I2C address events passed by \ref cy_cb_scb_i2c_handle_addr_t callback.
955 * Each event is encoded in a separate bit and therefore it is possible to
956 * notify about multiple events.
957 * \{
958 */
959 /**
960 * Indicates the slave was addressed by the general call address
961 */
962 #define CY_SCB_I2C_GENERAL_CALL_EVENT (0x01UL)
963
964 /**
965 * The slave address is in the RX FIFO.
966 * Note that the address must be read from the RX FIFO using the
967 * \ref Cy_SCB_ReadRxFifo function.
968 */
969 #define CY_SCB_I2C_ADDR_IN_FIFO_EVENT (0x02UL)
970 /** \} group_scb_i2c_macros_addr_callback_events */
971
972 /**
973 * This value is returned by the slave when there is no data in the
974 * Read buffer
975 */
976 #define CY_SCB_I2C_DEFAULT_TX (0xFFUL)
977
978
979 /*******************************************************************************
980 * Internal Constants
981 *******************************************************************************/
982
983 /** \cond INTERNAL */
984
985 /* Slave statuses */
986 #define CY_SCB_I2C_SLAVE_RD_CLEAR (CY_SCB_I2C_SLAVE_RD_CMPLT | CY_SCB_I2C_SLAVE_RD_IN_FIFO | \
987 CY_SCB_I2C_SLAVE_RD_UNDRFL | CY_SCB_I2C_SLAVE_ARB_LOST | \
988 CY_SCB_I2C_SLAVE_BUS_ERR)
989
990 #define CY_SCB_I2C_SLAVE_WR_CLEAR (CY_SCB_I2C_SLAVE_WR_CMPLT | CY_SCB_I2C_SLAVE_WR_OVRFL | \
991 CY_SCB_I2C_SLAVE_ARB_LOST | CY_SCB_I2C_SLAVE_BUS_ERR)
992
993 /* Master error statuses */
994 #define CY_SCB_I2C_MASTER_ERR (CY_SCB_I2C_MASTER_ABORT_START | CY_SCB_I2C_MASTER_ADDR_NAK | \
995 CY_SCB_I2C_MASTER_DATA_NAK | CY_SCB_I2C_MASTER_BUS_ERR | \
996 CY_SCB_I2C_MASTER_ARB_LOST)
997
998 /* Master interrupt masks */
999 #define CY_SCB_I2C_MASTER_INTR (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_BUS_ERROR | \
1000 CY_SCB_MASTER_INTR_I2C_NACK | CY_SCB_MASTER_INTR_I2C_STOP)
1001
1002 #define CY_SCB_I2C_MASTER_INTR_ALL (CY_SCB_I2C_MASTER_INTR | CY_SCB_MASTER_INTR_I2C_ACK)
1003
1004 #define CY_SCB_I2C_MASTER_INTR_ERR (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
1005
1006 #define CY_SCB_I2C_MASTER_INTR_CMPLT (CY_SCB_I2C_MASTER_INTR_ERR | CY_SCB_MASTER_INTR_I2C_STOP)
1007
1008 /* Master statuses. */
1009 #define CY_SCB_I2C_MASTER_TX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_NACK | \
1010 CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
1011
1012 #define CY_SCB_I2C_MASTER_RX_BYTE_DONE (CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
1013
1014 #define CY_SCB_I2C_MASTER_STOP_DONE (CY_SCB_MASTER_INTR_I2C_STOP | \
1015 CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_I2C_ARB_LOST)
1016
1017 #define CY_SCB_I2C_MASTER_TIMEOUT_DONE (0x80000000UL)
1018
1019 /* The slave interrupt mask */
1020 #define CY_SCB_I2C_SLAVE_INTR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
1021 CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | \
1022 CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
1023
1024 #define CY_SCB_I2C_SLAVE_INTR_NO_STOP (CY_SCB_I2C_SLAVE_INTR & (uint32_t) ~CY_SCB_SLAVE_INTR_I2C_STOP)
1025
1026 #define CY_SCB_I2C_SLAVE_INTR_ADDR (CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR)
1027
1028 #define CY_SCB_I2C_SLAVE_ADDR_DONE (CY_SCB_I2C_SLAVE_INTR_ADDR)
1029
1030 #define CY_SCB_I2C_SLAVE_INTR_NO_ADDR (CY_SCB_I2C_SLAVE_INTR & (uint32_t) ~CY_SCB_I2C_SLAVE_INTR_ADDR)
1031
1032 #define CY_SCB_I2C_SLAVE_INTR_TX (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW)
1033
1034 #define CY_SCB_I2C_SLAVE_INTR_ERROR (CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_I2C_ARB_LOST)
1035
1036 /* I2C states */
1037 #define CY_SCB_I2C_IDLE (0x10000000UL)
1038 #define CY_SCB_I2C_IDLE_MASK (0x10000000UL)
1039
1040 /* Master states */
1041 #define CY_SCB_I2C_MASTER_ACTIVE (0x00100000UL)
1042 #define CY_SCB_I2C_MASTER_WAIT (0x10100000UL)
1043 #define CY_SCB_I2C_MASTER_RX0 (0x00110000UL)
1044 #define CY_SCB_I2C_MASTER_RX1 (0x00120000UL)
1045 #define CY_SCB_I2C_MASTER_ADDR (0x10130000UL)
1046 #define CY_SCB_I2C_MASTER_TX (0x00140000UL)
1047 #define CY_SCB_I2C_MASTER_TX_DONE (0x00150000UL)
1048 #define CY_SCB_I2C_MASTER_STOP (0x00160000UL)
1049 #define CY_SCB_I2C_MASTER_WAIT_STOP (0x00170000UL)
1050 #define CY_SCB_I2C_MASTER_CMPLT (0x00180000UL)
1051
1052 /* Slave states */
1053 #define CY_SCB_I2C_SLAVE_ACTIVE (0x00001000UL)
1054 #define CY_SCB_I2C_SLAVE_RX_MASK (0x00001001UL)
1055 #define CY_SCB_I2C_SLAVE_RX (0x00001001UL)
1056 #define CY_SCB_I2C_SLAVE_TX (0x00001002UL)
1057
1058 /* FIFO size */
1059 #define CY_SCB_I2C_FIFO_SIZE CY_SCB_FIFO_SIZE
1060 #define CY_SCB_I2C_HALF_FIFO_SIZE (CY_SCB_FIFO_SIZE / 2UL)
1061
1062 #define CY_SCB_I2C_DEFAULT_RETURN (0xFFUL)
1063
1064 /* Convert the timeout in milliseconds to microseconds */
1065 #define CY_SCB_I2C_CONVERT_TIMEOUT_TO_US(timeoutMs) ((timeoutMs) * 1000UL)
1066
1067 /* I2C data rates max (Hz): standard, fast and fast plus modes */
1068 #define CY_SCB_I2C_STD_DATA_RATE (100000U)
1069 #define CY_SCB_I2C_FST_DATA_RATE (400000U)
1070 #define CY_SCB_I2C_FSTP_DATA_RATE (1000000U)
1071
1072 /* Slave clock limits */
1073 #define CY_SCB_I2C_SLAVE_STD_CLK_MIN (1550000U)
1074 #define CY_SCB_I2C_SLAVE_STD_CLK_MAX (12800000U)
1075 #define CY_SCB_I2C_SLAVE_FST_CLK_MIN (7820000U)
1076 #define CY_SCB_I2C_SLAVE_FST_CLK_MAX (15380000U)
1077 #define CY_SCB_I2C_SLAVE_FSTP_CLK_MIN (15840000U)
1078 #define CY_SCB_I2C_SLAVE_FSTP_CLK_MAX (89000000U)
1079
1080 /* Master clock (Hz) and duty cycle limits for standard mode */
1081 #define CY_SCB_I2C_MASTER_STD_CLK_MIN (1550000U)
1082 #define CY_SCB_I2C_MASTER_STD_CLK_MAX (3200000U)
1083 #define CY_SCB_I2C_MASTER_STD_LOW_PHASE_MIN (8U)
1084 #define CY_SCB_I2C_MASTER_STD_HIGH_PHASE_MIN (8U)
1085
1086 /* Master clock (Hz) and duty cycle limits for fast mode */
1087 #define CY_SCB_I2C_MASTER_FST_CLK_MIN (7820000U)
1088 #define CY_SCB_I2C_MASTER_FST_CLK_MAX (10000000U)
1089 #define CY_SCB_I2C_MASTER_FST_LOW_PHASE_MIN (13U)
1090 #define CY_SCB_I2C_MASTER_FST_HIGH_PHASE_MIN (8U)
1091
1092 /* Master clock (Hz) and duty cycle limits for fast plus mode */
1093 #define CY_SCB_I2C_MASTER_FSTP_CLK_MIN (14320000U)
1094 #define CY_SCB_I2C_MASTER_FSTP_CLK_MAX (25800000U)
1095 #define CY_SCB_I2C_MASTER_FSTP_LOW_PHASE_MIN (9U)
1096 #define CY_SCB_I2C_MASTER_FSTP_HIGH_PHASE_MIN (6U)
1097
1098 /* SCL low and high time in ns. Takes into account tF and tR */
1099 #define CY_SCB_I2C_MASTER_STD_SCL_LOW (5000U) /* tLOW + tF = 4700 + 300 */
1100 #define CY_SCB_I2C_MASTER_STD_SCL_HIGH (5000U) /* tHIGH + tR = 4000 + 1000 */
1101 #define CY_SCB_I2C_MASTER_FST_SCL_LOW (1600U) /* tLOW + tF = 1300 + 300 */
1102 #define CY_SCB_I2C_MASTER_FST_SCL_HIGH (900U) /* tHIGH + tR = 600 + 300 */
1103 #define CY_SCB_I2C_MASTER_FSTP_SCL_LOW (620U) /* tLOW + tF = 500 + 120 */
1104 #define CY_SCB_I2C_MASTER_FSTP_SCL_HIGH (380U) /* tHIGH + tR = 260 + 120 */
1105
1106 /* Master duty cycle limits */
1107 #define CY_SCB_I2C_LOW_PHASE_MAX (16U)
1108 #define CY_SCB_I2C_HIGH_PHASE_MAX (16U)
1109 #define CY_SCB_I2C_DUTY_CYCLE_MAX (CY_SCB_I2C_LOW_PHASE_MAX + CY_SCB_I2C_HIGH_PHASE_MAX)
1110
1111 /* Analog filter settings. */
1112 #define CY_SCB_I2C_ENABLE_ANALOG_FITLER (CY_SCB_I2C_CFG_DEF_VAL)
1113 #define CY_SCB_I2C_DISABLE_ANALOG_FITLER (CY_SCB_I2C_CFG_DEF_VAL & \
1114 (uint32_t) ~(SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk | \
1115 SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk))
1116
1117 #define CY_SCB_I2C_IS_MODE_VALID(mode) ( (CY_SCB_I2C_SLAVE == (mode)) || \
1118 (CY_SCB_I2C_MASTER == (mode)) || \
1119 (CY_SCB_I2C_MASTER_SLAVE == (mode)) )
1120
1121 #define CY_SCB_I2C_IS_RW_BIT_VALID(dir) ( (CY_SCB_I2C_WRITE_XFER == (dir)) || \
1122 (CY_SCB_I2C_READ_XFER == (dir)) )
1123
1124 #define CY_SCB_I2C_IS_RESPONSE_VALID(cmd) ( (CY_SCB_I2C_ACK == (cmd)) || \
1125 (CY_SCB_I2C_NAK == (cmd)) )
1126
1127 #define CY_SCB_I2C_IS_ADDR_MASK_VALID(mask) ( (0U == ((mask) & 0x01U)) )
1128
1129 #define CY_SCB_I2C_IS_PHASE_OVERSAMPLE_VALID(phaseOvs) ((phaseOvs) <= 16U)
1130
1131 #define CY_SCB_I2C_IS_DATA_RATE_VALID(dataRateHz) ( ((dataRateHz) > 0UL) && \
1132 ((dataRateHz) <= CY_SCB_I2C_FSTP_DATA_RATE) )
1133
1134 #define CY_SCB_I2C_IS_TIMEOUT_VALID(timeoutMs) ( (timeoutMs) <= (0xFFFFFFFFUL / 1000UL) )
1135 #define CY_SCB_I2C_IS_LOW_PHASE_CYCLES_VALID(clockCycles) ( ((clockCycles) >= 7UL) && ((clockCycles) <= 16UL) )
1136 #define CY_SCB_I2C_IS_HIGH_PHASE_CYCLES_VALID(clockCycles) ( ((clockCycles) >= 5UL) && ((clockCycles) <= 16UL) )
1137 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=3)) || defined (CY_IP_MXS22SCB))
1138 #define CY_SCB_I2C_STRETCH_THRESHOLD_VALUE_VALID(value) ( (value) <= SCB_I2C_STRETCH_CTRL_STRETCH_THRESHOLD_Msk )
1139 #endif /* CY_IP_MXSCB_VERSION */
1140
1141 /** \endcond */
1142
1143 /** \} group_scb_i2c_macros */
1144
1145
1146 /*******************************************************************************
1147 * In-line Function Implementation
1148 *******************************************************************************/
1149
1150 /**
1151 * \addtogroup group_scb_i2c_general_functions
1152 * \{
1153 */
1154
1155 /*******************************************************************************
1156 * Function Name: Cy_SCB_I2C_Enable
1157 ****************************************************************************//**
1158 *
1159 * Enables the SCB block for the I2C operation
1160 *
1161 * \param base
1162 * The pointer to the I2C SCB instance.
1163 * \note
1164 * Ensure SCB is initialized with \ref Cy_SCB_I2C_Init before calling this function
1165 *
1166 *******************************************************************************/
Cy_SCB_I2C_Enable(CySCB_Type * base)1167 __STATIC_INLINE void Cy_SCB_I2C_Enable(CySCB_Type *base)
1168 {
1169 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk;
1170 }
1171
1172
1173 /*******************************************************************************
1174 * Function Name: Cy_SCB_I2C_IsBusBusy
1175 ****************************************************************************//**
1176 *
1177 * Checks whether the I2C bus is busy.
1178 *
1179 * \param base
1180 * The pointer to the I2C SCB instance.
1181 *
1182 * \return
1183 * A bus status: busy or not busy.
1184 *
1185 * \note
1186 * After the SCB block is enabled or reset, the valid bus busy-status returns
1187 * after half of the SCL period.
1188 *
1189 *******************************************************************************/
Cy_SCB_I2C_IsBusBusy(CySCB_Type const * base)1190 __STATIC_INLINE bool Cy_SCB_I2C_IsBusBusy(CySCB_Type const *base)
1191 {
1192 return _FLD2BOOL(SCB_I2C_STATUS_BUS_BUSY, SCB_I2C_STATUS(base));
1193 }
1194
1195
1196 /*******************************************************************************
1197 * Function Name: Cy_SCB_I2C_SlaveSetAddress
1198 ****************************************************************************//**
1199 *
1200 * Sets the slave address for the I2C slave.
1201 *
1202 * \param base
1203 * The pointer to the I2C SCB instance.
1204 *
1205 * \param addr
1206 * The 7-bit right justified slave address.
1207 *
1208 *******************************************************************************/
Cy_SCB_I2C_SlaveSetAddress(CySCB_Type * base,uint8_t addr)1209 __STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddress(CySCB_Type *base, uint8_t addr)
1210 {
1211 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr));
1212
1213 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL)));
1214 }
1215
1216
1217 /*******************************************************************************
1218 * Function Name: Cy_SCB_I2C_SlaveGetAddress
1219 ****************************************************************************//**
1220 *
1221 * Returns the slave address of the I2C slave.
1222 *
1223 * \param base
1224 * The pointer to the I2C SCB instance.
1225 *
1226 * \return
1227 * The 7-bit right justified slave address.
1228 *
1229 *******************************************************************************/
Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const * base)1230 __STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddress(CySCB_Type const *base)
1231 {
1232 return (_FLD2VAL(SCB_RX_MATCH_ADDR, SCB_RX_MATCH(base)) >> 1UL);
1233 }
1234
1235
1236 /*******************************************************************************
1237 * Function Name: Cy_SCB_I2C_SlaveSetAddressMask
1238 ****************************************************************************//**
1239 *
1240 * Sets the slave address mask for the I2C slave. The LSBit must always be 0.
1241 * In all other bit positions a 1 indicates that the incoming address must match
1242 * the corresponding bit in the slave address. A 0 in the mask means that the
1243 * incoming address does not need to match.
1244 * Example Slave Address = 0x0C. Slave Address Mask = 0x08. This means that the
1245 * hardware will accept both 0x08 and 0x0C as valid addresses.
1246 *
1247 * \param base
1248 * The pointer to the I2C SCB instance.
1249 *
1250 * \param addrMask
1251 * The 8-bit address mask, the upper 7 bits correspond to the slave address.
1252 * LSBit must always be 0.
1253 *
1254 *******************************************************************************/
Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type * base,uint8_t addrMask)1255 __STATIC_INLINE void Cy_SCB_I2C_SlaveSetAddressMask(CySCB_Type *base, uint8_t addrMask)
1256 {
1257 CY_ASSERT_L2(CY_SCB_I2C_IS_ADDR_MASK_VALID(addrMask));
1258
1259 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_MASK, ((uint32_t) addrMask));
1260 }
1261
1262
1263 /*******************************************************************************
1264 * Function Name: Cy_SCB_I2C_SlaveGetAddressMask
1265 ****************************************************************************//**
1266 *
1267 * Returns the slave address mask.
1268 *
1269 * \param base
1270 * The pointer to the I2C SCB instance.
1271 *
1272 * \return
1273 * The 8-bit address mask, the upper 7 bits correspond to the slave address.
1274 * LSBit must always be 0.
1275 *
1276 *******************************************************************************/
Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const * base)1277 __STATIC_INLINE uint32_t Cy_SCB_I2C_SlaveGetAddressMask(CySCB_Type const *base)
1278 {
1279 return _FLD2VAL(SCB_RX_MATCH_MASK, SCB_RX_MATCH(base));
1280 }
1281
1282
1283 /*******************************************************************************
1284 * Function Name: Cy_SCB_I2C_MasterSetLowPhaseDutyCycle
1285 ****************************************************************************//**
1286 *
1287 * This function sets the number of SCB clock cycles in the low phase of SCL.
1288 * If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values
1289 * specified in this function are overwritten.
1290 *
1291 * \param base
1292 * The pointer to the I2C SCB instance.
1293 *
1294 * \param clockCycles
1295 * The number of SCB clock cycles in the low phase of SCL.
1296 * The valid range is 7 to 16.
1297 *
1298 * \note
1299 * This function should be used at your own risk. Changing the number of clock
1300 * cycles in a phase of SCL may violate the I2C specification. Make this
1301 * change only while the block is disabled.
1302 *
1303 * Please refer to the section \ref group_scb_i2c_mclk_sync for more information.
1304 *
1305 *******************************************************************************/
Cy_SCB_I2C_MasterSetLowPhaseDutyCycle(CySCB_Type * base,uint32_t clockCycles)1306 __STATIC_INLINE void Cy_SCB_I2C_MasterSetLowPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles)
1307 {
1308 CY_ASSERT_L2(CY_SCB_I2C_IS_LOW_PHASE_CYCLES_VALID(clockCycles));
1309
1310 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_LOW_PHASE_OVS, (clockCycles - 1UL));
1311 }
1312
1313
1314 /*******************************************************************************
1315 * Function Name: Cy_SCB_I2C_MasterSetHighPhaseDutyCycle
1316 ****************************************************************************//**
1317 *
1318 * This function sets the number of SCB clock cycles in the high phase of SCL.
1319 * If \ref Cy_SCB_I2C_SetDataRate is called after this function, the values
1320 * specified in this function get overwritten.
1321 *
1322 * \param base
1323 * The pointer to the I2C SCB instance.
1324 *
1325 * \param clockCycles
1326 * The number of SCB clock cycles in the high phase of SCL.
1327 * The valid range is 5 to 16.
1328 *
1329 * \note
1330 * This function should be used at your own risk. Changing the number of clock
1331 * cycles in a phase of SCL may violate the I2C specification. Make this
1332 * change only while the block is disabled.
1333 *
1334 *******************************************************************************/
Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type * base,uint32_t clockCycles)1335 __STATIC_INLINE void Cy_SCB_I2C_MasterSetHighPhaseDutyCycle(CySCB_Type *base, uint32_t clockCycles)
1336 {
1337 CY_ASSERT_L2(CY_SCB_I2C_IS_HIGH_PHASE_CYCLES_VALID(clockCycles));
1338
1339 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_HIGH_PHASE_OVS, (clockCycles - 1UL));
1340 }
1341 /** \} group_scb_i2c_general_functions */
1342
1343 /**
1344 * \addtogroup group_scb_i2c_interrupt_functions
1345 * \{
1346 */
1347
1348 /*******************************************************************************
1349 * Function Name: Cy_SCB_I2C_RegisterEventCallback
1350 ****************************************************************************//**
1351 *
1352 * Registers a callback function that notifies that
1353 * \ref group_scb_i2c_macros_callback_events occurred in the
1354 * \ref Cy_SCB_I2C_Interrupt.
1355 *
1356 * \param base
1357 * The pointer to the I2C SCB instance.
1358 *
1359 * \param callback
1360 * The pointer to a callback function.
1361 * See \ref cy_cb_scb_i2c_handle_events_t for the function prototype.
1362 *
1363 * \param context
1364 * The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
1365 * the user. The structure is used while the I2C operation for internal
1366 * configuration and data retention. The user should not modify anything in
1367 * this structure.
1368 *
1369 * \note
1370 * To remove the callback, pass NULL as the pointer to the callback function.
1371 *
1372 *******************************************************************************/
Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const * base,cy_cb_scb_i2c_handle_events_t callback,cy_stc_scb_i2c_context_t * context)1373 __STATIC_INLINE void Cy_SCB_I2C_RegisterEventCallback(CySCB_Type const *base,
1374 cy_cb_scb_i2c_handle_events_t callback, cy_stc_scb_i2c_context_t *context)
1375 {
1376 /* Suppress a compiler warning about unused variables */
1377 (void) base;
1378
1379 context->cbEvents = callback;
1380 }
1381
1382
1383 /*******************************************************************************
1384 * Function Name: Cy_SCB_I2C_RegisterAddrCallback
1385 ****************************************************************************//**
1386 *
1387 * Registers a callback function that notifies that
1388 * \ref group_scb_i2c_macros_addr_callback_events occurred in the
1389 * \ref Cy_SCB_I2C_Interrupt.
1390 *
1391 * \param base
1392 * The pointer to the I2C SCB instance.
1393 *
1394 * \param callback
1395 * The pointer to a callback function.
1396 * See \ref cy_cb_scb_i2c_handle_addr_t for the function prototype.
1397 *
1398 * \param context
1399 * The pointer to context structure \ref cy_stc_scb_i2c_context_t allocated by
1400 * the user. The structure is used during the I2C operation for internal
1401 * configuration and data retention. The user should not modify anything in
1402 * this structure.
1403 *
1404 * \note
1405 * To remove the callback, pass NULL as the pointer to a callback function.
1406 *
1407 *******************************************************************************/
Cy_SCB_I2C_RegisterAddrCallback(CySCB_Type const * base,cy_cb_scb_i2c_handle_addr_t callback,cy_stc_scb_i2c_context_t * context)1408 __STATIC_INLINE void Cy_SCB_I2C_RegisterAddrCallback(CySCB_Type const *base,
1409 cy_cb_scb_i2c_handle_addr_t callback, cy_stc_scb_i2c_context_t *context)
1410 {
1411 /* Suppress a compiler warning about unused variables */
1412 (void) base;
1413
1414 context->cbAddr = callback;
1415 }
1416 /** \} group_scb_i2c_interrupt_functions */
1417
1418 #if defined(__cplusplus)
1419 }
1420 #endif
1421
1422 /** \} group_scb_i2c */
1423
1424 #endif /* (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB)) */
1425
1426 #endif /* (CY_SCB_I2C_H) */
1427
1428 /* [] END OF FILE */
1429
