1 /***************************************************************************//**
2 * \file cy_prot.h
3 * \version 1.100
4 *
5 * \brief
6 * Provides an API declaration of the Protection Unit driver
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation
11 * (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26
27 /**
28 * \addtogroup group_prot
29 * \{
30 *
31 * The Protection Unit driver provides an API to configure the Memory Protection
32 * Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection
33 * Units (PPU). These are separate from the ARM Core MPUs and provide additional
34 * mechanisms for securing resource accesses. The Protection units address the
35 * following concerns in an embedded design:
36 * - <b>Security requirements:</b> This includes the prevention of malicious attacks
37 * to access secure memory or peripherals.
38 * - <b>Safety requirements:</b> This includes detection of accidental (non-malicious)
39 * SW errors and random HW errors. It is important to enable failure analysis
40 * to investigate the root cause of a safety violation.
41 *
42 * The functions and other declarations used in this driver are in cy_prot.h.
43 * You can include cy_pdl.h to get access to all functions
44 * and declarations in the PDL.
45 *
46 * \section group_prot_protection_type Protection Types
47 *
48 * Protection units are hardware configuration structures that control bus accesses
49 * to the resources that they protect. By combining these individual configuration
50 * structures, a system is built to allow strict restrictions on the capabilities
51 * of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes.
52 * This architecture can then be integrated into the overall security system
53 * of the end application. To build this system, 3 main protection unit types
54 * are available; MPU, SMPU and PPU. When a resource is accessed (memory/register),
55 * it must pass the evaluation performed for each category. These access evaluations
56 * are prioritized, where MPU has the highest priority, followed by SMPU, followed
57 * by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is
58 * denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
59 * denial-of-service scenario and the application should pay special attention in
60 * taking ownership of the protection unit configurations.
61 *
62 * \subsection group_prot_memory_protection Memory Protection
63 *
64 * Memory access control for a bus master is controlled using an MPU. These are
65 * most often used to distinguish user and privileged accesses from a single bus
66 * master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
67 * core MPUs are used to perform this task. For other non-ARM bus masters such
68 * as Crypto, MPU structs are available, which can be used in a similar manner
69 * as the ARM core MPUs. These MPUs however must be configured by the ARM cores.
70 * Other bus masters that do not have an MPU, such as DMA (DW), inherit the access
71 * control attributes of the bus master that configured the channel. Also note
72 * that unlike other protection units, MPUs do not support protection context
73 * evaluation. MPU structs have a descending priority, where larger index struct
74 * has higher priority access evaluation over lower index structs. E.g. MPU_STRUCT15
75 * has higher priority than MPU_STRUCT14 and its access will be evaluated before
76 * MPU_STRUCT14. If both target the same memory, then the higher index (MPU_STRUCT15)
77 * will be used, and the lower index (MPU_STRUCT14) will be ignored.
78 *
79 * \subsection group_prot_shared_memory_protection Shared Memory Protection
80 *
81 * In order to protect a region of memory from all bus masters, an SMPU is used.
82 * This protection effectively allows only those with correct bus master access
83 * settings to read/write/execute the memory region. This type of protection
84 * is used in general memory such as Flash and SRAM. Peripheral registers are
85 * best configured using the peripheral protection units instead. SMPU structs
86 * have a descending priority, where larger index struct has higher priority
87 * access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority
88 * than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
89 * If both target the same memory, then the higher index (MPU_STRUCT15) will be
90 * used, and the lower index (SMPU_STRUCT14) will be ignored.
91 *
92 * \subsection group_prot_peripheral_protection Peripheral Protection
93 *
94 * Peripheral protection is provided by PPUs and allow control of peripheral
95 * register accesses by bus masters. Four types of PPUs are available.
96 * - <b>Fixed Group (GR) PPUs</b> are used to protect an entire peripheral MMIO group
97 * from invalid bus master accesses. The MMIO grouping information and which
98 * resource belongs to which group is device specific and can be obtained
99 * from the device technical reference manual (TRM). Group PPUs have the highest
100 * priority in the PPU category. Therefore their access evaluations take precedence
101 * over the other types of PPUs.
102 * - <b>Programmable (PROG) PPUs</b> are used to protect any peripheral memory region
103 * in a device from invalid bus master accesses. It is the most versatile
104 * type of peripheral protection unit. Programmable PPUs have the second highest
105 * priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs,
106 * higher index PROG PPUs have higher priority than lower indexes PROG PPUs.
107 * - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
108 * instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
109 * SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence
110 * over Slave PPUs.
111 * - <b>Fixed Slave (SL) PPUs</b> are used to protect specified regions of peripheral
112 * instances. For example, individual DW channel structs, SMPU structs, and
113 * IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and
114 * therefore are evaluated last.
115 *
116 * \section group_prot_protection_context Protection Context
117 *
118 * Protection context (PC) attribute is present in all bus masters and is evaluated
119 * when accessing memory protected by an SMPU or a PPU. There are no limitations
120 * to how the PC values are allocated to the bus masters and this makes it
121 * possible for multiple bus masters to essentially share protection context
122 * values. The exception to this rule is the PC value 0.
123 *
124 * \subsection group_prot_pc0 PC=0
125 *
126 * Protection context 0 is a hardware controlled protection context update
127 * mechanism that allows only a single entry point for transitioning into PC=0
128 * value. This mechanism is only present for the secure CM0+ core and is a
129 * fundamental feature in defining a security solution. While all bus masters
130 * are configured to PC=0 at device boot, it is up to the security solution
131 * to transition these bus masters to PC!=0 values. Once this is done, those
132 * bus masters can no longer revert back to PC=0 and can no longer access
133 * resources protected at PC=0.
134 *
135 * In order to enter PC=0, the CM0+ core must assign an interrupt vector or
136 * an exception handler address to the CPUSS.CM0_PC0_HANDLER register. This
137 * allows the hardware to check whether the executing code address matches the
138 * value in this register. If they match, the current PC value is saved and
139 * the CM0+ bus master automatically transitions to PC=0. It is then up to
140 * the executing code to decide if and when it will revert to a PC!=0 value.
141 * At that point, the only way to re-transition to PC=0 is through the defined
142 * exception/interrupt handler.
143 *
144 * \note Devices with CPUSS ver_2 have a hardware-controlled protection context
145 * update mechanism that allows only a single-entry point for transitioning
146 * into PC=0, 1, 2, and 3. The interrupt vector or the exception handler
147 * address can be assigned to the CPUSS.CM0_PC0_HANDLER, CPUSS.CM0_PC1_HANDLER,
148 * CPUSS.CM0_PC2_HANDLER or CPUSS.CM0_PC2_HANDLER register. Also, the control
149 * register CPUSS.CM0_PC_CTL of the CM0+ protection context must be set:
150 * bit 0 - the valid field for CM0_PC0_HANDLER,
151 * bit 1 - the valid field for CM0_PC1_HANDLER,
152 * bit 2 - the valid field for CM0_PC2_HANDLER,
153 * and bit 3 - the valid field for CM0_PC3_HANDLER.
154 *
155 * The example of using of the single entry point mechanism is shown below.
156 * \snippet prot/snippet/main.c snippet_Cy_Prot_ProtectionContext
157 *
158 * \section group_prot_access_evaluation Access Evaluation
159 *
160 * Each protection unit is capable of evaluating several access types. These can
161 * be used to build a system of logical evaluations for different kinds of
162 * bus master modes of operations. These access types can be divided into
163 * three broad access categories.
164 *
165 * - <b>User/Privileged access:</b> The ARM convention of user mode versus privileged
166 * mode is applied in the protection units. For ARM cores, switching between
167 * user and privileged modes is handled by updating its Control register or
168 * by exception entries. Other bus masters such as Crypto have their own
169 * user/privileged settings bit in the bus master control register. This is
170 * then controlled by the ARM cores. Bus masters that do not have
171 * user/privileged access controls, such as DMA, inherit their attributes
172 * from the bus master that configured it. The user/privileged distinction
173 * is used mainly in the MPUs for single bus master accesses but they can
174 * also be used in all other protection units.
175 * - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
176 * identifier to distinguish between two separate modes of operations. Much
177 * like the user/privileged access, the secure/non-secure mode flag is present
178 * in the bus master control register. The ARM core does not have this
179 * attribute in its control register and must use the bus master control
180 * register instead. Bus masters that inherit their attributes, such as DMA,
181 * inherit the secure/non-secure attribute. The primary use-case for this
182 * access evaluation is to define a region to be secure or non-secure using
183 * an SMPU or a PPU. A bus master with a secure attribute can access
184 * both secure and non-secure regions, whereas a bus master with non-secure
185 * attribute can only access non-secure regions.
186 * - <b>Protection Context access:</b> Protection Context is an attribute
187 * that serves two purposes; To enter the hardware controlled secure PC=0
188 * mode of operation from non-secure modes and to provide finer granularity
189 * to the bus master access definitions. It is used in SMPU and PPU configuration
190 * to control which bus master protection context can access the resources
191 * that they protect.
192 *
193 * \section group_prot_protection_structure Protection Structure
194 *
195 * Each protection unit is comprised of a master struct and a slave struct pair.
196 * The exception to this rule is MPU structs, which only have the slave struct
197 * equivalent. The protection units apply their access evaluations in a decreasing
198 * index order. For example, if SMPU1 and SMPU2 both protect a specific memory region,
199 * the the higher index (SMPU2) will be evaluated first. In a secure system, the
200 * higher index protection structs would then provide the high level of security
201 * and the lower indexes would provide the lower level of security. Refer to the
202 * \ref group_prot_protection_type section for more information.
203 *
204 * \subsection group_prot_slave_struct Slave Struct
205 *
206 * The slave struct is used to configure the protection settings for the resource
207 * of interest (memory/registers). Depending on the type of protection unit,
208 * the available attributes differ. However all Slave protection units have the
209 * following general format.
210 *
211 * \subsubsection group_prot_slave_addr Slave Struct Address Definition
212 *
213 * - Address: For MPU, SMPU and PROG PPU, the address field is used to define
214 * the base memory region to apply the protection. This field has a dependency
215 * on the region size, which dictates the alignment of the protection unit. E.g.
216 * if the region size is 64KB, the address field is aligned to 64KB. Hence
217 * the lowest bits [15:0] are ignored. For instance, if the address is defined
218 * at 0x0800FFFF, the protection unit would apply its protection settings from
219 * 0x08000000. Thus alignment must be checked before defining the protection
220 * address. The address field for other PPUs are not used, as they are bound
221 * to their respective peripheral memory locations.
222 * - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define
223 * the memory block size to apply the protection settings, starting from the
224 * defined base address. It is also used to define the 8 sub-regions for the
225 * chosen memory block. E.g. If the region size is 64KB, each subregion would
226 * be 8KB. This information can then be used to disable the protection
227 * settings for select subregions, which gives finer granularity to the
228 * memory regions. PPUs do not have region size definitions as they are bound
229 * to their respective peripheral memory locations.
230 * - Subregions: The memory block defined by the address and region size fields
231 * is divided into 8 (0 to 7) equally spaced subregions. The protection settings
232 * of the protection unit can be disabled for these subregions. E.g. for a
233 * given 64KB of memory block starting from address 0x08000000, disabling
234 * subregion 0 would result in the protection settings not affecting the memory
235 * located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
236 * definitions as they are bound to their respective peripheral memory locations.
237 *
238 * \subsubsection group_prot_slave_attr Slave Struct Attribute Definition
239 *
240 * - User Permission: Protection units can control the access restrictions
241 * of the read (R), write (W) and execute (X) (subject to their availability
242 * depending on the type of protection unit) operations on the memory block
243 * when the bus master is operating in user mode. PPU structs do not provide
244 * execute attributes.
245 * - Privileged Permission: Similar to the user permission, protection units can
246 * control the access restrictions of the read (R), write (W) and execute (X)
247 * (subject to their availability depending on the type of protection unit)
248 * operations on the memory block when the bus master is operating in
249 * privileged mode. PPU structs do not provide execute attributes.
250 * - Secure/Non-secure: Applies the secure/non-secure protection settings to
251 * the defined memory region. Secure protection allows only bus masters that
252 * access the memory with secure attribute. Non-secure protection allows
253 * bus masters that have either secure or non-secure attributes.
254 * - PC match: This attribute allows the protection unit to either apply the
255 * 3 access evaluations (user/privileged, secure/non-secure, protection context)
256 * or to only provide an address range match. This is useful when multiple
257 * protection units protect an overlapping memory region and it's desirable
258 * to only have access evaluations applied from only one of these protection
259 * units. For example, SMPU1 protects memory A and SMPU2 protects memory B.
260 * There exists a region where A and B intersect and this is accessed by a
261 * bus master. Both SMPU1 and SMPU2 are configured to operate in "match" mode.
262 * In this scenario, the access evaluation will only be applied by the higher
263 * index protection unit (i.e. SMPU2) and the access attributes of SMPU1 will
264 * be ignored. If the bus master then tries to access a memory region A (that
265 * does not intersect with B), the access evaluation from SMPU1 will be used.
266 * Note that the PC match functionality is only available in SMPUs.
267 * - PC mask: Defines the allowed protection context values that can access the
268 * protected memory. The bus master attribute must be operating in one of the
269 * protection context values allowed by the protection unit. E.g. If SMPU1 is
270 * configured to allow only PC=1 and PC=5, a bus master (such as CM4) must
271 * be operating at PC=1 or PC=5 when accessing the protected memory region.
272 *
273 * \subsection group_prot_master_struct Master Struct
274 *
275 * The master struct protects its slave struct in the protection unit. This
276 * architecture makes possible for the slave configuration to be protected from
277 * reconfiguration by an unauthorized bus master. The configuration attributes
278 * and the format are similar to that of the slave structs.
279 *
280 * \subsubsection group_prot_master_addr Master Struct Address Definition
281 *
282 * - Address: The address definition for master struct is fixed to the slave
283 * struct that it protects.
284 * - Region Size: The region size is fixed to 256B region.
285 * - Subregion: This value is fixed to only enable the first 64B subregions,
286 * which applies the protection settings to the entire protection unit.
287 *
288 * \subsubsection group_prot_master_attr Master Struct Attribute Definition
289 *
290 * - User Permission: Only the write (W) access attribute is allowed for
291 * master structs, which controls whether a bus master operating in user
292 * mode has the write access.
293 * - Privileged Permission: Only the write (W) access attribute is allowed for
294 * master structs, which controls whether a bus master operating in privileged
295 * mode has the write access.
296 * - Secure/Non-Secure: Same behavior as slave struct.
297 * - PC match: Same behavior as slave struct.
298 * - PC mask: Same behavior as slave struct.
299 *
300 * \section group_prot_driver_usage Driver Usage
301 *
302 * Setting up and using protection units can be summed up in four stages:
303 *
304 * - Configure the bus master attributes. This defines the capabilities of
305 * the bus master when trying to access the protected resources.
306 * - Configure the slave struct of a given protection unit. This defines
307 * the protection attributes to be applied to the bus master accessing
308 * the protected resource and also defines the size and location of the
309 * memory block to protect.
310 * - Configure the master struct of the protection unit. This defines the
311 * attributes to be checked against the bus master that is trying to
312 * reconfigure the slave struct.
313 * - Set the active PC value of the bus master and place it in the correct
314 * mode of operation (user/privileged, secure/non-secure). Then access
315 * the protected memory.
316 *
317 * For example, by configuring the CM0+ bus master configuration to allow
318 * only protection contexts 2 and 3, the bus master will be able to
319 * set its protection context only to 2 or 3. During runtime, the CM0+ core
320 * can set its protection context to 2 by calling Cy_Prot_SetActivePC()
321 * and access all regions of protected memory that allow PC=2. A fault will
322 * be triggered if a resource is protected with different protection settings.
323 *
324 * Note that each protection unit is distinguished by its type (e.g.
325 * PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be
326 * obtained from the device definition header file. Choose a protection unit
327 * of interest, and call its corresponding Cy_Prot_Config<X>Struct() function
328 * with its software protection unit configuration structure populated. Then
329 * enable the protection unit by calling the Cy_Prot_Enable<X>Struct() function.
330 *
331 * Note that the bus master ID (en_prot_master_t) is defined in the device
332 * config header file.
333 *
334 * \section group_prot_configuration Configuration Considerations
335 *
336 * When a resource (memory/register) is accessed, it must pass evaluation of
337 * all three protection unit categories in the following order: MPU->SMPU->PPU.
338 * The application should ensure that a denial-of-service attack cannot be
339 * made on the PPU by the SMPU. For this reason, it is recommended that the
340 * application's security policy limit the ability for the non-secure client
341 * from configuring the SMPUs.
342 *
343 * Within each category, the priority hierarchy must be carefully considered
344 * to ensure that a higher priority protection unit cannot be configured to
345 * override the security configuration of a lower index protection unit.
346 * Therefore if a lower index protection unit is configured, relevant higher
347 * priority indexes should be configured (or protected from unwanted
348 * reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that
349 * overlaps with the protected registers should also be configured. SImilar
350 * to SMPUs, it is recommended that the configuration of PPU_PROG be limited.
351 * Otherwise they can be used to override the protection settings of PPU_RG
352 * and PPU_SL structs.
353 *
354 * All bus masters are set to PC=0 value at device reset and therefore have full
355 * access to all resources. It is up to the security solution to implement
356 * what privileges each bus master has. Once transitioned to a PC!=0 value,
357 * only the CM0+ core is capable of re-entering the PC=0 via the user-defined
358 * exception entry in the CPUSS.CM0_PC0_HANDLER register.
359 *
360 * - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at
361 * device boot.
362 * - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
363 * device boot.
364 * - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot.
365 *
366 * \section group_prot_more_information More Information
367 *
368 * Refer to Technical Reference Manual (TRM) and the device datasheet.
369 *
370 * \section group_prot_changelog Changelog
371 * <table class="doxtable">
372 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
373 * <tr>
374 * <td>1.100</td>
375 * <td>Updating implementation of internal function that configures attributes.</td>
376 * <td>Defect fix.</td>
377 * </tr>
378 * <tr>
379 * <td>1.90</td>
380 * <td>Added support for TRAVEO™ II Body Entry devices.<br>
381 * Updated conditions in pre-processor check for if the device has a CM4 to also check for for MXPERI ver. 1.<br>
382 * Cleaned up redundant code.<br>
383 * Bug fix: Updates some API availability based on the PERI version. Some devices may have a reduced set of functions
384 * available. If code called APIs not appropriate for the version of PERI, that code will not build without updating
385 * to reflect new API availability. Please note, however, that if code was calling those APIs and the functions are
386 * no longer available, there will be no functional difference as the calls were available before but did nothing if
387 * the device hardware didn't support the function. This change makes the API accurately reflect hardware capability.</td>
388 * <td>Code enhancement and support for new devices.</td>
389 * </tr>
390 * <tr>
391 * <td>1.80</td>
392 * <td>\ref Cy_Prot_ConfigPpuProgSlaveAddr(), \ref Cy_Prot_EnablePpuProgSlaveRegion() \ref Cy_Prot_DisablePpuProgSlaveRegion()
393 * APIs are only available for PSoC6 devices</td>
394 * <td>MISRA C-2012 compliance and Move PERI version-1 APIs to supported devices</td>
395 * </tr>
396 * <tr>
397 * <td>1.70</td>
398 * <td> Added support for CAT1C devices. </td>
399 * <td> New device added. </td>
400 * </tr>
401 * <tr>
402 * <td>1.60</td>
403 * <td>Modified \ref Cy_Prot_ConfigPpuProgMasterAtt() & \ref Cy_Prot_ConfigPpuFixedMasterAtt()
404 * functions to ignore unavailable protection context.</td>
405 * <td>Defect fix.</td>
406 * </tr>
407 * <tr>
408 * <td rowspan="3">1.50</td>
409 * <td>Updated implementation of the \ref Cy_Prot_ConfigPpuProgMasterAtt(),
410 * \ref Cy_Prot_ConfigPpuProgSlaveAtt(), \ref Cy_Prot_ConfigPpuFixedMasterAtt(),
411 * and \ref Cy_Prot_ConfigPpuFixedSlaveAtt() to start registers update from
412 * the higher-numbered PCs in order to prevent lockup for the case when registers
413 * are configured to read-only.</td>
414 * <td>Defect fix.</td>
415 * </tr>
416 * <tr>
417 * <td>Added macros for memory region size setting in \ref cy_en_prot_size_t initialization.</td>
418 * <td>The macros can be useful for the pre-processor checks.</td>
419 * </tr>
420 * <tr>
421 * <td>Fixed/Documented MISRA 2012 violations.</td>
422 * <td>MISRA 2012 compliance.</td>
423 * </tr>
424 * <tr>
425 * <td>1.40</td>
426 * <td>
427 * - Updated the \ref Cy_Prot_SetActivePC() function to report an error when called
428 * on the secure CYB06xx7 devices as no access privileges are available.
429 * - Updated the \ref Cy_Prot_GetActivePC() function for the secure CYB06xx7
430 * devices to access the protected registers via the \ref group_pra driver.
431 * </td>
432 * <td>Added PSoC 64 devices support.</td>
433 * </tr>
434 * <tr>
435 * <td>1.30.3</td>
436 * <td>Minor documentation updates.</td>
437 * <td>Documentation enhancement.</td>
438 * </tr>
439 * <tr>
440 * <td>1.30.2</td>
441 * <td>Clarified the description of the next API functions: \ref Cy_Prot_ConfigPpuProgMasterAtt,\n
442 * \ref Cy_Prot_ConfigPpuProgSlaveAtt, \ref Cy_Prot_ConfigPpuFixedMasterAtt, \ref Cy_Prot_ConfigPpuFixedSlaveAtt.</td>
443 * <td>API enhancement based on usability feedback.</td>
444 * </tr>
445 * <tr>
446 * <td>1.30.1</td>
447 * <td>Snippet updated.</td>
448 * <td>Old snippet outdated.</td>
449 * </tr>
450 * <tr>
451 * <td>1.30</td>
452 * <td>Defect in \ref Cy_Prot_GetPpuProgStruct() function due to faulty defines is fixed.</td>
453 * <td>Defect fixing.</td>
454 * </tr>
455 * <tr>
456 * <td rowspan="3">1.20</td>
457 * <td>Flattened the organization of the driver source code into the single
458 * source directory and the single include directory.</td>
459 * <td>Driver library directory-structure simplification.</td>
460 * </tr>
461 * <tr>
462 * <td>Added functions for CPUSS ver_2:
463 * - \ref Cy_Prot_ConfigPpuProgMasterAtt()
464 * - \ref Cy_Prot_ConfigPpuProgSlaveAddr()
465 * - \ref Cy_Prot_ConfigPpuProgSlaveAtt()
466 * - \ref Cy_Prot_EnablePpuProgSlaveRegion()
467 * - \ref Cy_Prot_DisablePpuProgSlaveRegion()
468 * - \ref Cy_Prot_ConfigPpuFixedMasterAtt()
469 * - \ref Cy_Prot_ConfigPpuFixedSlaveAtt()
470 * </td>
471 * <td>Added support for CPUSS ver_2.</td>
472 * </tr>
473 * <tr>
474 * <td>Added register access layer. Use register access macros instead
475 * of direct register access using dereferenced pointers.</td>
476 * <td>Makes register access device-independent, so that the PDL does
477 * not need to be recompiled for each supported part number.</td>
478 * </tr>
479 * <tr>
480 * <td rowspan="2">1.10</td>
481 * <td>Added input parameter validation to the API functions.<br>
482 * cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
483 * types are set to typedef enum</td>
484 * <td>Improved debugging capability</td>
485 * </tr>
486 * <tr>
487 * <td>Expanded documentation</td>
488 * <td></td>
489 * </tr>
490 * <tr>
491 * <td>1.0</td>
492 * <td>Initial version</td>
493 * <td></td>
494 * </tr>
495 * </table>
496 *
497 * \defgroup group_prot_macros Macros
498 * \defgroup group_prot_functions Functions
499 * \{
500 * \defgroup group_prot_functions_busmaster Bus Master and PC Functions
501 * \defgroup group_prot_functions_mpu MPU Functions
502 * \defgroup group_prot_functions_smpu SMPU Functions
503 * \defgroup group_prot_functions_ppu_prog_v2 PPU Programmable (PROG) v2 Functions
504 * \defgroup group_prot_functions_ppu_fixed_v2 PPU Fixed (FIXED) v2 Functions
505 * \defgroup group_prot_functions_ppu_prog PPU Programmable (PROG) v1 Functions
506 * \defgroup group_prot_functions_ppu_gr PPU Group (GR) v1 Functions
507 * \defgroup group_prot_functions_ppu_sl PPU Slave (SL) v1 Functions
508 * \defgroup group_prot_functions_ppu_rg PPU Region (RG) v1 Functions
509 * \}
510 * \defgroup group_prot_data_structures Data Structures
511 * \defgroup group_prot_enums Enumerated Types
512 */
513
514 #if !defined (CY_CY_PROT_PDL_H)
515 #define CY_CY_PROT_PDL_H
516
517 #include "cy_device.h"
518
519 #if defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS)
520
521 #include <stdbool.h>
522 #include <stddef.h>
523 #include "cy_device_headers.h"
524 #include "cy_syslib.h"
525
526 #if defined(__cplusplus)
527 extern "C" {
528 #endif
529
530 /** \addtogroup group_prot_macros
531 * \{
532 */
533
534 /** Driver major version */
535 #define CY_PROT_DRV_VERSION_MAJOR 1
536
537 /** Driver minor version */
538 #define CY_PROT_DRV_VERSION_MINOR 100
539
540 /** Prot driver ID */
541 #define CY_PROT_ID (CY_PDL_DRV_ID(0x30U))
542
543 /** \} group_prot_macros */
544
545 /**
546 * \addtogroup group_prot_enums
547 * \{
548 */
549
550 /**
551 * Prot Driver error codes
552 */
553 typedef enum
554 {
555 CY_PROT_SUCCESS = 0x00U, /**< Returned successful */
556 CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
557 CY_PROT_INVALID_STATE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x02U, /**< The operation is not setup */
558 CY_PROT_FAILURE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x03U, /**< The resource is locked */
559 CY_PROT_UNAVAILABLE = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x04U /**< The resource is unavailable */
560 } cy_en_prot_status_t;
561
562 /**
563 * User/Privileged permission
564 */
565 typedef enum
566 {
567 CY_PROT_PERM_DISABLED = 0x00U, /**< Read, Write and Execute disabled */
568 CY_PROT_PERM_R = 0x01U, /**< Read enabled */
569 CY_PROT_PERM_W = 0x02U, /**< Write enabled */
570 CY_PROT_PERM_RW = 0x03U, /**< Read and Write enabled */
571 CY_PROT_PERM_X = 0x04U, /**< Execute enabled */
572 CY_PROT_PERM_RX = 0x05U, /**< Read and Execute enabled */
573 CY_PROT_PERM_WX = 0x06U, /**< Write and Execute enabled */
574 CY_PROT_PERM_RWX = 0x07U /**< Read, Write and Execute enabled */
575 }cy_en_prot_perm_t;
576
577 /**
578 * Constants for memory region size setting.
579 * These may be useful for pre-processor-time tests.
580 */
581 #define PROT_SIZE_4B_BIT_SHIFT 1U /**< 4 bytes */
582 #define PROT_SIZE_8B_BIT_SHIFT 2U /**< 8 bytes */
583 #define PROT_SIZE_16B_BIT_SHIFT 3U /**< 16 bytes */
584 #define PROT_SIZE_32B_BIT_SHIFT 4U /**< 32 bytes */
585 #define PROT_SIZE_64B_BIT_SHIFT 5U /**< 64 bytes */
586 #define PROT_SIZE_128B_BIT_SHIFT 6U /**< 128 bytes */
587 #define PROT_SIZE_256B_BIT_SHIFT 7U /**< 256 bytes */
588 #define PROT_SIZE_512B_BIT_SHIFT 8U /**< 512 bytes */
589
590 #define PROT_SIZE_1KB_BIT_SHIFT 9U /**< 1 Kilobyte */
591 #define PROT_SIZE_2KB_BIT_SHIFT 10U /**< 2 Kilobytes */
592 #define PROT_SIZE_4KB_BIT_SHIFT 11U /**< 4 Kilobytes */
593 #define PROT_SIZE_8KB_BIT_SHIFT 12U /**< 8 Kilobytes */
594 #define PROT_SIZE_16KB_BIT_SHIFT 13U /**< 16 Kilobytes */
595 #define PROT_SIZE_32KB_BIT_SHIFT 14U /**< 32 Kilobytes */
596 #define PROT_SIZE_64KB_BIT_SHIFT 15U /**< 64 Kilobytes */
597 #define PROT_SIZE_128KB_BIT_SHIFT 16U /**< 128 Kilobytes */
598 #define PROT_SIZE_256KB_BIT_SHIFT 17U /**< 256 Kilobytes */
599 #define PROT_SIZE_512KB_BIT_SHIFT 18U /**< 512 Kilobytes */
600
601 #define PROT_SIZE_1MB_BIT_SHIFT 19U /**< 1 Megabyte */
602 #define PROT_SIZE_2MB_BIT_SHIFT 20U /**< 2 Megabytes */
603 #define PROT_SIZE_4MB_BIT_SHIFT 21U /**< 4 Megabytes */
604 #define PROT_SIZE_8MB_BIT_SHIFT 22U /**< 8 Megabytes */
605 #define PROT_SIZE_16MB_BIT_SHIFT 23U /**< 16 Megabytes */
606 #define PROT_SIZE_32MB_BIT_SHIFT 24U /**< 32 Megabytes */
607 #define PROT_SIZE_64MB_BIT_SHIFT 25U /**< 64 Megabytes */
608 #define PROT_SIZE_128MB_BIT_SHIFT 26U /**< 128 Megabytes */
609 #define PROT_SIZE_256MB_BIT_SHIFT 27U /**< 256 Megabytes */
610 #define PROT_SIZE_512MB_BIT_SHIFT 28U /**< 512 Megabytes */
611
612 #define PROT_SIZE_1GB_BIT_SHIFT 29U /**< 1 Gigabyte */
613 #define PROT_SIZE_2GB_BIT_SHIFT 30U /**< 2 Gigabytes */
614 #define PROT_SIZE_4GB_BIT_SHIFT 31U /**< 4 Gigabytes */
615
616 /**
617 * Memory region size
618 */
619 typedef enum
620 {
621 CY_PROT_SIZE_4B = PROT_SIZE_4B_BIT_SHIFT, /**< 4 bytes */
622 CY_PROT_SIZE_8B = PROT_SIZE_8B_BIT_SHIFT, /**< 8 bytes */
623 CY_PROT_SIZE_16B = PROT_SIZE_16B_BIT_SHIFT, /**< 16 bytes */
624 CY_PROT_SIZE_32B = PROT_SIZE_32B_BIT_SHIFT, /**< 32 bytes */
625 CY_PROT_SIZE_64B = PROT_SIZE_64B_BIT_SHIFT, /**< 64 bytes */
626 CY_PROT_SIZE_128B = PROT_SIZE_128B_BIT_SHIFT, /**< 128 bytes */
627 CY_PROT_SIZE_256B = PROT_SIZE_256B_BIT_SHIFT, /**< 256 bytes */
628 CY_PROT_SIZE_512B = PROT_SIZE_512B_BIT_SHIFT, /**< 512 bytes */
629 CY_PROT_SIZE_1KB = PROT_SIZE_1KB_BIT_SHIFT, /**< 1 Kilobyte */
630 CY_PROT_SIZE_2KB = PROT_SIZE_2KB_BIT_SHIFT, /**< 2 Kilobytes */
631 CY_PROT_SIZE_4KB = PROT_SIZE_4KB_BIT_SHIFT, /**< 4 Kilobytes */
632 CY_PROT_SIZE_8KB = PROT_SIZE_8KB_BIT_SHIFT, /**< 8 Kilobytes */
633 CY_PROT_SIZE_16KB = PROT_SIZE_16KB_BIT_SHIFT, /**< 16 Kilobytes */
634 CY_PROT_SIZE_32KB = PROT_SIZE_32KB_BIT_SHIFT, /**< 32 Kilobytes */
635 CY_PROT_SIZE_64KB = PROT_SIZE_64KB_BIT_SHIFT, /**< 64 Kilobytes */
636 CY_PROT_SIZE_128KB = PROT_SIZE_128KB_BIT_SHIFT, /**< 128 Kilobytes */
637 CY_PROT_SIZE_256KB = PROT_SIZE_256KB_BIT_SHIFT, /**< 256 Kilobytes */
638 CY_PROT_SIZE_512KB = PROT_SIZE_512KB_BIT_SHIFT, /**< 512 Kilobytes */
639 CY_PROT_SIZE_1MB = PROT_SIZE_1MB_BIT_SHIFT, /**< 1 Megabyte */
640 CY_PROT_SIZE_2MB = PROT_SIZE_2MB_BIT_SHIFT, /**< 2 Megabytes */
641 CY_PROT_SIZE_4MB = PROT_SIZE_4MB_BIT_SHIFT, /**< 4 Megabytes */
642 CY_PROT_SIZE_8MB = PROT_SIZE_8MB_BIT_SHIFT, /**< 8 Megabytes */
643 CY_PROT_SIZE_16MB = PROT_SIZE_16MB_BIT_SHIFT, /**< 16 Megabytes */
644 CY_PROT_SIZE_32MB = PROT_SIZE_32MB_BIT_SHIFT, /**< 32 Megabytes */
645 CY_PROT_SIZE_64MB = PROT_SIZE_64MB_BIT_SHIFT, /**< 64 Megabytes */
646 CY_PROT_SIZE_128MB = PROT_SIZE_128MB_BIT_SHIFT, /**< 128 Megabytes */
647 CY_PROT_SIZE_256MB = PROT_SIZE_256MB_BIT_SHIFT, /**< 256 Megabytes */
648 CY_PROT_SIZE_512MB = PROT_SIZE_512MB_BIT_SHIFT, /**< 512 Megabytes */
649 CY_PROT_SIZE_1GB = PROT_SIZE_1GB_BIT_SHIFT, /**< 1 Gigabyte */
650 CY_PROT_SIZE_2GB = PROT_SIZE_2GB_BIT_SHIFT, /**< 2 Gigabytes */
651 CY_PROT_SIZE_4GB = PROT_SIZE_4GB_BIT_SHIFT /**< 4 Gigabytes */
652 }cy_en_prot_size_t;
653
654 /**
655 * Protection Context (PC)
656 */
657 enum cy_en_prot_pc_t
658 {
659 CY_PROT_PC1 = 1U, /**< PC = 1 */
660 CY_PROT_PC2 = 2U, /**< PC = 2 */
661 CY_PROT_PC3 = 3U, /**< PC = 3 */
662 CY_PROT_PC4 = 4U, /**< PC = 4 */
663 CY_PROT_PC5 = 5U, /**< PC = 5 */
664 CY_PROT_PC6 = 6U, /**< PC = 6 */
665 CY_PROT_PC7 = 7U, /**< PC = 7 */
666 CY_PROT_PC8 = 8U, /**< PC = 8 */
667 CY_PROT_PC9 = 9U, /**< PC = 9 */
668 CY_PROT_PC10 = 10U, /**< PC = 10 */
669 CY_PROT_PC11 = 11U, /**< PC = 11 */
670 CY_PROT_PC12 = 12U, /**< PC = 12 */
671 CY_PROT_PC13 = 13U, /**< PC = 13 */
672 CY_PROT_PC14 = 14U, /**< PC = 14 */
673 CY_PROT_PC15 = 15U /**< PC = 15 */
674 };
675
676 /**
677 * Subregion disable (0-7)
678 */
679 enum cy_en_prot_subreg_t
680 {
681 CY_PROT_SUBREGION_DIS0 = 0x01U, /**< Disable subregion 0 */
682 CY_PROT_SUBREGION_DIS1 = 0x02U, /**< Disable subregion 1 */
683 CY_PROT_SUBREGION_DIS2 = 0x04U, /**< Disable subregion 2 */
684 CY_PROT_SUBREGION_DIS3 = 0x08U, /**< Disable subregion 3 */
685 CY_PROT_SUBREGION_DIS4 = 0x10U, /**< Disable subregion 4 */
686 CY_PROT_SUBREGION_DIS5 = 0x20U, /**< Disable subregion 5 */
687 CY_PROT_SUBREGION_DIS6 = 0x40U, /**< Disable subregion 6 */
688 CY_PROT_SUBREGION_DIS7 = 0x80U /**< Disable subregion 7 */
689 };
690
691 /**
692 * Protection context mask (PC_MASK)
693 */
694 enum cy_en_prot_pcmask_t
695 {
696 CY_PROT_PCMASK1 = 0x0001U, /**< Mask to allow PC = 1 */
697 CY_PROT_PCMASK2 = 0x0002U, /**< Mask to allow PC = 2 */
698 CY_PROT_PCMASK3 = 0x0004U, /**< Mask to allow PC = 3 */
699 CY_PROT_PCMASK4 = 0x0008U, /**< Mask to allow PC = 4 */
700 CY_PROT_PCMASK5 = 0x0010U, /**< Mask to allow PC = 5 */
701 CY_PROT_PCMASK6 = 0x0020U, /**< Mask to allow PC = 6 */
702 CY_PROT_PCMASK7 = 0x0040U, /**< Mask to allow PC = 7 */
703 CY_PROT_PCMASK8 = 0x0080U, /**< Mask to allow PC = 8 */
704 CY_PROT_PCMASK9 = 0x0100U, /**< Mask to allow PC = 9 */
705 CY_PROT_PCMASK10 = 0x0200U, /**< Mask to allow PC = 10 */
706 CY_PROT_PCMASK11 = 0x0400U, /**< Mask to allow PC = 11 */
707 CY_PROT_PCMASK12 = 0x0800U, /**< Mask to allow PC = 12 */
708 CY_PROT_PCMASK13 = 0x1000U, /**< Mask to allow PC = 13 */
709 CY_PROT_PCMASK14 = 0x2000U, /**< Mask to allow PC = 14 */
710 CY_PROT_PCMASK15 = 0x4000U /**< Mask to allow PC = 15 */
711 };
712
713 /**
714 * Request mode to get the SMPU or programmed PU structure
715 */
716 typedef enum
717 {
718 CY_PROT_REQMODE_HIGHPRIOR = 0U, /**< Request mode to return PU structure with highest priority */
719 CY_PROT_REQMODE_LOWPRIOR = 1U, /**< Request mode to return PU structure with lowest priority */
720 CY_PROT_REQMODE_INDEX = 2U /**< Request mode to return PU structure with specific index */
721 }cy_en_prot_req_mode_t;
722
723 /** \} group_prot_enums */
724
725
726 /***************************************
727 * Constants
728 ***************************************/
729
730 /** \cond INTERNAL */
731
732 /* Number of SMPU structures with highest priority */
733 #define PROT_SMPU_STRUCT_WTH_HIGHEST_PR (15)
734
735 /* Number of Programmable PPU structures with lowest priority */
736 #define PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR (15)
737
738 /* Define to check maximum value of active PC */
739 #define PROT_PC_MAX (16U)
740
741 /* Define to check maximum mask of PC */
742 #define PROT_PC_MASK_MAX (0x7FFFUL)
743
744 /* General Masks and shifts */
745 #define CY_PROT_MSX_CTL_SHIFT (0x02UL) /**< Shift for MSx_CTL register */
746 #define CY_PROT_STRUCT_ENABLE (0x01UL) /**< Enable protection unit struct */
747 #define CY_PROT_STRUCT_DISABLE (0x00UL) /**< Disable protection unit struct */
748 #define CY_PROT_ADDR_SHIFT (8UL) /**< Address shift for MPU, SMPU and PROG PPU structs */
749 #define CY_PROT_PCMASK_CHECK (0x01UL) /**< Shift and mask for pcMask check */
750 #define CY_PROT_PCMASK_VALID ((0xFFFFUL) & (~(0xFFFFUL << PERI_PC_NR))) /**< Bitmask to mask pcMask for unavailable protection contexts */
751
752 /* Permission masks and shifts */
753 #define CY_PROT_ATT_PERMISSION_MASK (0x07UL) /**< Protection Unit attribute permission mask */
754 #define CY_PROT_ATT_PRIV_PERMISSION_SHIFT (0x03UL) /**< Protection Unit privileged attribute permission shift */
755
756 #define CY_PROT_ATT_PERI_USER_PERM_Pos (0UL) /**< PERI v2 privileged attribute permission shift */
757 #define CY_PROT_ATT_PERI_USER_PERM_Msk (0x03UL) /**< PERI v2 attribute permission mask */
758 #define CY_PROT_ATT_PERI_PRIV_PERM_Pos (2UL) /**< PERI v2 privileged attribute permission shift */
759 #define CY_PROT_ATT_PERI_PRIV_PERM_Msk ((uint32_t)(0x03UL << CY_PROT_ATT_PERI_PRIV_PERM_Pos)) /**< PERI v2 attribute permission mask */
760
761 #define CY_PROT_ATT_REGS_MAX (4U) /**< Maximum number of ATT registers */
762 #define CY_PROT_ATT_PC_MAX (4U) /**< Maximum PC value per ATT reg */
763
764 /* BWC macros */
765 #define CY_PROT_ATT_PERI_PERM_MASK (0x03UL)
766 #define CY_PROT_ATT_PERI_PRIV_PERM_SHIFT (0x02UL)
767 /* End of BWC macros */
768
769 #define CY_PROT_SMPU_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
770 #define CY_PROT_PPU_PROG_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
771 #define CY_PROT_PPU_FIXED_PC_LIMIT_MASK ((uint32_t) 0xFFFFFFFFUL << (CY_PROT_PC_MAX - 1UL))
772
773 #define CY_PROT_SMPU_ATT0_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk))
774 #define CY_PROT_SMPU_ATT1_MASK ((uint32_t)~(PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk \
775 | PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk \
776 | PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk \
777 | PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk \
778 ))
779
780 #define CY_PROT_PPU_PROG_ATT0_MASK ((uint32_t)~(PERI_PPU_PR_ATT0_UX_Msk \
781 | PERI_PPU_PR_ATT0_PX_Msk \
782 | PERI_PPU_PR_ATT0_PC_MASK_0_Msk \
783 ))
784 #define CY_PROT_PPU_PROG_ATT1_MASK ((uint32_t)~(PERI_PPU_PR_ATT1_UX_Msk \
785 | PERI_PPU_PR_ATT1_PX_Msk \
786 | PERI_PPU_PR_ATT1_PC_MASK_0_Msk \
787 | PERI_PPU_PR_ATT1_REGION_SIZE_Msk \
788 ))
789 #define CY_PROT_PPU_GR_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
790 | PERI_PPU_GR_ATT0_PX_Msk \
791 | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
792 | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
793 ))
794 #define CY_PROT_PPU_GR_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
795 | PERI_PPU_GR_ATT1_PX_Msk \
796 | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
797 | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
798 ))
799 #define CY_PROT_PPU_SL_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
800 | PERI_PPU_GR_ATT0_PX_Msk \
801 | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
802 | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
803 ))
804 #define CY_PROT_PPU_SL_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
805 | PERI_PPU_GR_ATT1_PX_Msk \
806 | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
807 | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
808 ))
809 #define CY_PROT_PPU_RG_ATT0_MASK ((uint32_t)~(PERI_PPU_GR_ATT0_UX_Msk \
810 | PERI_PPU_GR_ATT0_PX_Msk \
811 | PERI_PPU_GR_ATT0_PC_MASK_0_Msk \
812 | PERI_PPU_GR_ATT0_REGION_SIZE_Msk \
813 ))
814 #define CY_PROT_PPU_RG_ATT1_MASK ((uint32_t)~(PERI_PPU_GR_ATT1_UX_Msk \
815 | PERI_PPU_GR_ATT1_PX_Msk \
816 | PERI_PPU_GR_ATT1_PC_MASK_0_Msk \
817 | PERI_PPU_GR_ATT1_REGION_SIZE_Msk \
818 ))
819
820 /* Parameter check macros */
821 #define CY_PROT_IS_BUS_MASTER_VALID(busMaster) ((CY_PROT_BUS_MASTER_MASK & (1UL << (uint32_t)(busMaster))) != 0UL)
822
823 #define CY_PROT_IS_MPU_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
824 ((permission) == CY_PROT_PERM_R) || \
825 ((permission) == CY_PROT_PERM_W) || \
826 ((permission) == CY_PROT_PERM_RW) || \
827 ((permission) == CY_PROT_PERM_X) || \
828 ((permission) == CY_PROT_PERM_RX) || \
829 ((permission) == CY_PROT_PERM_WX) || \
830 ((permission) == CY_PROT_PERM_RWX))
831
832 #define CY_PROT_IS_SMPU_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
833 ((permission) == CY_PROT_PERM_RW))
834
835 #define CY_PROT_IS_SMPU_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
836 ((permission) == CY_PROT_PERM_R) || \
837 ((permission) == CY_PROT_PERM_W) || \
838 ((permission) == CY_PROT_PERM_RW) || \
839 ((permission) == CY_PROT_PERM_X) || \
840 ((permission) == CY_PROT_PERM_RX) || \
841 ((permission) == CY_PROT_PERM_WX) || \
842 ((permission) == CY_PROT_PERM_RWX))
843
844 #define CY_PROT_IS_PROG_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
845 ((permission) == CY_PROT_PERM_RW))
846
847 #define CY_PROT_IS_PROG_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
848 ((permission) == CY_PROT_PERM_R) || \
849 ((permission) == CY_PROT_PERM_W) || \
850 ((permission) == CY_PROT_PERM_RW))
851
852 #define CY_PROT_IS_FIXED_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
853 ((permission) == CY_PROT_PERM_R) || \
854 ((permission) == CY_PROT_PERM_W) || \
855 ((permission) == CY_PROT_PERM_RW))
856
857 #define CY_PROT_IS_FIXED_MS_MS_PERM_VALID(permission) (((permission) == CY_PROT_PERM_R) || \
858 ((permission) == CY_PROT_PERM_RW))
859
860
861 #define CY_PROT_IS_FIXED_SL_PERM_VALID(permission) (((permission) == CY_PROT_PERM_DISABLED) || \
862 ((permission) == CY_PROT_PERM_R) || \
863 ((permission) == CY_PROT_PERM_W) || \
864 ((permission) == CY_PROT_PERM_RW))
865
866 #define CY_PROT_IS_REGION_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_256B) || \
867 ((regionSize) == CY_PROT_SIZE_512B) || \
868 ((regionSize) == CY_PROT_SIZE_1KB) || \
869 ((regionSize) == CY_PROT_SIZE_2KB) || \
870 ((regionSize) == CY_PROT_SIZE_4KB) || \
871 ((regionSize) == CY_PROT_SIZE_8KB) || \
872 ((regionSize) == CY_PROT_SIZE_16KB) || \
873 ((regionSize) == CY_PROT_SIZE_32KB) || \
874 ((regionSize) == CY_PROT_SIZE_64KB) || \
875 ((regionSize) == CY_PROT_SIZE_128KB) || \
876 ((regionSize) == CY_PROT_SIZE_256KB) || \
877 ((regionSize) == CY_PROT_SIZE_512KB) || \
878 ((regionSize) == CY_PROT_SIZE_1MB) || \
879 ((regionSize) == CY_PROT_SIZE_2MB) || \
880 ((regionSize) == CY_PROT_SIZE_4MB) || \
881 ((regionSize) == CY_PROT_SIZE_8MB) || \
882 ((regionSize) == CY_PROT_SIZE_16MB) || \
883 ((regionSize) == CY_PROT_SIZE_32MB) || \
884 ((regionSize) == CY_PROT_SIZE_64MB) || \
885 ((regionSize) == CY_PROT_SIZE_128MB) || \
886 ((regionSize) == CY_PROT_SIZE_256MB) || \
887 ((regionSize) == CY_PROT_SIZE_512MB) || \
888 ((regionSize) == CY_PROT_SIZE_1GB) || \
889 ((regionSize) == CY_PROT_SIZE_2GB) || \
890 ((regionSize) == CY_PROT_SIZE_4GB))
891
892 #define CY_PROT_IS_PPU_V2_SIZE_VALID(regionSize) (((regionSize) == CY_PROT_SIZE_4B) || \
893 ((regionSize) == CY_PROT_SIZE_8B) || \
894 ((regionSize) == CY_PROT_SIZE_16B) || \
895 ((regionSize) == CY_PROT_SIZE_32B) || \
896 ((regionSize) == CY_PROT_SIZE_64B) || \
897 ((regionSize) == CY_PROT_SIZE_128B) || \
898 ((regionSize) == CY_PROT_SIZE_256B) || \
899 ((regionSize) == CY_PROT_SIZE_512B) || \
900 ((regionSize) == CY_PROT_SIZE_1KB) || \
901 ((regionSize) == CY_PROT_SIZE_2KB) || \
902 ((regionSize) == CY_PROT_SIZE_4KB) || \
903 ((regionSize) == CY_PROT_SIZE_8KB) || \
904 ((regionSize) == CY_PROT_SIZE_16KB) || \
905 ((regionSize) == CY_PROT_SIZE_32KB) || \
906 ((regionSize) == CY_PROT_SIZE_64KB) || \
907 ((regionSize) == CY_PROT_SIZE_128KB) || \
908 ((regionSize) == CY_PROT_SIZE_256KB) || \
909 ((regionSize) == CY_PROT_SIZE_512KB) || \
910 ((regionSize) == CY_PROT_SIZE_1MB) || \
911 ((regionSize) == CY_PROT_SIZE_2MB) || \
912 ((regionSize) == CY_PROT_SIZE_4MB) || \
913 ((regionSize) == CY_PROT_SIZE_8MB) || \
914 ((regionSize) == CY_PROT_SIZE_16MB) || \
915 ((regionSize) == CY_PROT_SIZE_32MB) || \
916 ((regionSize) == CY_PROT_SIZE_64MB) || \
917 ((regionSize) == CY_PROT_SIZE_128MB) || \
918 ((regionSize) == CY_PROT_SIZE_256MB) || \
919 ((regionSize) == CY_PROT_SIZE_512MB) || \
920 ((regionSize) == CY_PROT_SIZE_1GB) || \
921 ((regionSize) == CY_PROT_SIZE_2GB) || \
922 ((regionSize) == CY_PROT_SIZE_4GB))
923
924 #define CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \
925 ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \
926 ((reqMode) == CY_PROT_REQMODE_INDEX))
927
928 #define CY_PROT_IS_PPU_PROG_REQ_MODE_VALID(reqMode) (((reqMode) == CY_PROT_REQMODE_HIGHPRIOR) || \
929 ((reqMode) == CY_PROT_REQMODE_LOWPRIOR) || \
930 ((reqMode) == CY_PROT_REQMODE_INDEX))
931
932 #define CY_PROT_IS_SMPU_IDX_VALID(smpuIndex) ((smpuIndex) <= (uint32_t)PROT_SMPU_STRUCT_WTH_HIGHEST_PR)
933
934 #define CY_PROT_IS_PPU_PROG_IDX_VALID(ppuIndex) ((ppuIndex) <= (uint32_t)PROT_PPU_PROG_STRUCT_WTH_LOWEST_PR)
935
936 #define CY_PROT_IS_PC_VALID(pc) ((pc) < PROT_PC_MAX)
937 #define CY_PROT_IS_PC_MASK_VALID(pcMask) (((pcMask) & ((uint32_t)~PROT_PC_MASK_MAX)) == 0UL)
938
939 /** \endcond */
940
941
942 /***************************************
943 * Configuration Structures
944 ***************************************/
945
946 /**
947 * \addtogroup group_prot_data_structures
948 * \{
949 */
950
951 /** Configuration structure for MPU Struct initialization */
952 typedef struct
953 {
954 uint32_t* address; /**< Base address of the memory region */
955 cy_en_prot_size_t regionSize; /**< Size of the memory region */
956 uint8_t subregions; /**< Mask of the 8 subregions to disable */
957 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
958 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
959 bool secure; /**< Non Secure = 0, Secure = 1 */
960 } cy_stc_mpu_cfg_t;
961
962 /** Configuration structure for SMPU struct initialization */
963 typedef struct
964 {
965 uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
966 cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
967 uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
968 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
969 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
970 bool secure; /**< Non Secure = 0, Secure = 1 */
971 bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
972 uint16_t pcMask; /**< Mask of allowed protection context(s) */
973 } cy_stc_smpu_cfg_t;
974
975 /** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
976 typedef struct
977 {
978 uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
979 cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
980 uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
981 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
982 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
983 bool secure; /**< Non Secure = 0, Secure = 1 */
984 bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
985 uint16_t pcMask; /**< Mask of allowed protection context(s) */
986 } cy_stc_ppu_prog_cfg_t;
987
988 /** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
989 typedef struct
990 {
991 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
992 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
993 bool secure; /**< Non Secure = 0, Secure = 1 */
994 bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
995 uint16_t pcMask; /**< Mask of allowed protection context(s) */
996 } cy_stc_ppu_gr_cfg_t;
997
998 /** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
999 typedef struct
1000 {
1001 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
1002 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
1003 bool secure; /**< Non Secure = 0, Secure = 1 */
1004 bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
1005 uint16_t pcMask; /**< Mask of allowed protection context(s) */
1006 } cy_stc_ppu_sl_cfg_t;
1007
1008 /** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
1009 typedef struct
1010 {
1011 cy_en_prot_perm_t userPermission; /**< User permissions for the region */
1012 cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
1013 bool secure; /**< Non Secure = 0, Secure = 1 */
1014 bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
1015 uint16_t pcMask; /**< Mask of allowed protection context(s) */
1016 } cy_stc_ppu_rg_cfg_t;
1017
1018 /** \} group_prot_data_structures */
1019
1020
1021 /***************************************
1022 * Function Prototypes
1023 ***************************************/
1024
1025 /**
1026 * \addtogroup group_prot_functions
1027 * \{
1028 */
1029
1030 /**
1031 * \addtogroup group_prot_functions_busmaster
1032 * \{
1033 */
1034 cy_en_prot_status_t Cy_Prot_ConfigBusMaster(en_prot_master_t busMaster, bool privileged, bool secure, uint32_t pcMask);
1035 cy_en_prot_status_t Cy_Prot_SetActivePC(en_prot_master_t busMaster, uint32_t pc);
1036 uint32_t Cy_Prot_GetActivePC(en_prot_master_t busMaster);
1037 /** \} group_prot_functions_busmaster */
1038
1039 /**
1040 * \addtogroup group_prot_functions_mpu
1041 * \{
1042 */
1043 cy_en_prot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config);
1044 cy_en_prot_status_t Cy_Prot_EnableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
1045 cy_en_prot_status_t Cy_Prot_DisableMpuStruct(PROT_MPU_MPU_STRUCT_Type* base);
1046 /** \} group_prot_functions_mpu */
1047
1048 /**
1049 * \addtogroup group_prot_functions_smpu
1050 * \{
1051 */
1052 __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
1053 cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t smpuIndex);
1054
1055 cy_en_prot_status_t Cy_Prot_ConfigSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
1056 cy_en_prot_status_t Cy_Prot_ConfigSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base, const cy_stc_smpu_cfg_t* config);
1057 cy_en_prot_status_t Cy_Prot_EnableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
1058 cy_en_prot_status_t Cy_Prot_DisableSmpuMasterStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
1059 cy_en_prot_status_t Cy_Prot_EnableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
1060 cy_en_prot_status_t Cy_Prot_DisableSmpuSlaveStruct(PROT_SMPU_SMPU_STRUCT_Type* base);
1061
1062 /** \} group_prot_functions_smpu */
1063
1064
1065 #if (defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION > 1U)) || defined (CY_DOXYGEN)
1066 /**
1067 * \addtogroup group_prot_functions_ppu_prog_v2
1068 * \{
1069 */
1070 cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
1071 cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAtt(PERI_MS_PPU_PR_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
1072 cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, uint32_t address, cy_en_prot_size_t regionSize);
1073 cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base);
1074 cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base);
1075 /** \} group_prot_functions_ppu_prog_v2 */
1076
1077 /**
1078 * \addtogroup group_prot_functions_ppu_fixed_v2
1079 * \{
1080 */
1081 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
1082 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlaveAtt(PERI_MS_PPU_FX_Type* base, uint16_t pcMask, cy_en_prot_perm_t userPermission, cy_en_prot_perm_t privPermission, bool secure);
1083 /** \} group_prot_functions_ppu_fixed_v2 */
1084 #endif
1085
1086
1087 #if (defined (CY_IP_M4CPUSS) && defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U)) || defined (CY_DOXYGEN)
1088 /**
1089 * \addtogroup group_prot_functions_ppu_prog
1090 * \{
1091 */
1092 __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type* base);
1093
1094 cy_en_prot_status_t Cy_Prot_ConfigPpuProgMasterStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
1095 cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveStruct(PERI_PPU_PR_Type* base, const cy_stc_ppu_prog_cfg_t* config);
1096 cy_en_prot_status_t Cy_Prot_EnablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
1097 cy_en_prot_status_t Cy_Prot_DisablePpuProgMasterStruct(PERI_PPU_PR_Type* base);
1098 cy_en_prot_status_t Cy_Prot_EnablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
1099 cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveStruct(PERI_PPU_PR_Type* base);
1100
1101 cy_en_prot_status_t Cy_Prot_GetPpuProgStruct(PERI_PPU_PR_Type** base, cy_en_prot_req_mode_t reqMode, uint32_t ppuProgIndex);
1102
1103 /** \} group_prot_functions_ppu_prog */
1104
1105 /**
1106 * \addtogroup group_prot_functions_ppu_gr
1107 * \{
1108 */
1109 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrMasterStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
1110 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base, const cy_stc_ppu_gr_cfg_t* config);
1111 cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
1112 cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrMasterStruct(PERI_PPU_GR_Type* base);
1113 cy_en_prot_status_t Cy_Prot_EnablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
1114 cy_en_prot_status_t Cy_Prot_DisablePpuFixedGrSlaveStruct(PERI_PPU_GR_Type* base);
1115 /** \} group_prot_functions_ppu_gr */
1116
1117 /**
1118 * \addtogroup group_prot_functions_ppu_sl
1119 * \{
1120 */
1121 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
1122 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base, const cy_stc_ppu_sl_cfg_t* config);
1123 cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
1124 cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlMasterStruct(PERI_GR_PPU_SL_Type* base);
1125 cy_en_prot_status_t Cy_Prot_EnablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
1126 cy_en_prot_status_t Cy_Prot_DisablePpuFixedSlSlaveStruct(PERI_GR_PPU_SL_Type* base);
1127 /** \} group_prot_functions_ppu_sl */
1128
1129 /**
1130 * \addtogroup group_prot_functions_ppu_rg
1131 * \{
1132 */
1133 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
1134 cy_en_prot_status_t Cy_Prot_ConfigPpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base, const cy_stc_ppu_rg_cfg_t* config);
1135 cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
1136 cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgMasterStruct(PERI_GR_PPU_RG_Type* base);
1137 cy_en_prot_status_t Cy_Prot_EnablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
1138 cy_en_prot_status_t Cy_Prot_DisablePpuFixedRgSlaveStruct(PERI_GR_PPU_RG_Type* base);
1139 /** \} group_prot_functions_ppu_rg */
1140
1141 #endif /* (CY_IP_M4CPUSS) && defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U) */
1142
1143 /** \} group_prot_functions */
1144
1145
1146
1147 /**
1148 * \addtogroup group_prot_functions
1149 * \{
1150 */
1151
1152 /**
1153 * \addtogroup group_prot_functions_smpu
1154 * \{
1155 */
1156
1157 /*******************************************************************************
1158 * Function Name: Cy_Prot_DisableSmpuStruct
1159 ****************************************************************************//**
1160 *
1161 * This function disables both the master and slave parts of a protection unit.
1162 *
1163 * \param base
1164 * The base address for the SMPU structure to be disabled.
1165 *
1166 * \return
1167 * Status of the function call.
1168 *
1169 * Status | Description
1170 * ---------------------| -----------
1171 * CY_PROT_SUCCESS | The Master and Slave SMPU struct was disabled
1172 * CY_PROT_FAILURE | The Master and/or slave SMPU struct was not disabled
1173 * CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version
1174 *
1175 * \funcusage
1176 * \snippet prot/snippet/main.c snippet_Cy_Prot_DisableSmpuStruct
1177 *
1178 *******************************************************************************/
Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type * base)1179 __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisableSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type* base)
1180 {
1181 cy_en_prot_status_t status = Cy_Prot_DisableSmpuMasterStruct(base);
1182
1183 if (CY_PROT_SUCCESS == status)
1184 {
1185 status = Cy_Prot_DisableSmpuSlaveStruct(base);
1186 }
1187
1188 return status;
1189 }
1190 /** \} group_prot_functions_smpu */
1191
1192
1193 #if (defined (CY_IP_M4CPUSS) && defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U)) || defined (CY_DOXYGEN)
1194 /**
1195 * \addtogroup group_prot_functions_ppu_prog
1196 * \{
1197 */
1198 /*******************************************************************************
1199 * Function Name: Cy_Prot_DisablePpuProgStruct
1200 ****************************************************************************//**
1201 *
1202 * This function disables both the master and slave parts of a protection unit.
1203 *
1204 * \note
1205 * This functions has an effect only on devices with PERI IP version 1. Refer
1206 * to the device datasheet for information about PERI HW IP version.
1207 *
1208 * \param base
1209 * The base address for the Programmable PU structure to be disabled.
1210 *
1211 * \return
1212 * Status of the function call.
1213 *
1214 * Status | Description
1215 * ---------------------| -----------
1216 * CY_PROT_SUCCESS | The Master and Slave Programmable PU struct was disabled
1217 * CY_PROT_FAILURE | The Master and/or slave Programmable PU struct was not disabled
1218 * CY_PROT_INVALID_STATE | Function was called on the unsupported PERI IP version
1219 *
1220 * \funcusage
1221 * \snippet prot/snippet/main.c snippet_Cy_Prot_DisablePpuProgStruct
1222 *
1223 *******************************************************************************/
Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type * base)1224 __STATIC_INLINE cy_en_prot_status_t Cy_Prot_DisablePpuProgStruct(PERI_PPU_PR_Type* base)
1225 {
1226 cy_en_prot_status_t status = CY_PROT_INVALID_STATE;
1227
1228 #if (CY_IP_MXPERI_VERSION <= 1u)
1229 if (CY_PERI_V1 != 0U)
1230 {
1231 status = Cy_Prot_DisablePpuProgMasterStruct(base);
1232
1233 if (CY_PROT_SUCCESS == status)
1234 {
1235 status = Cy_Prot_DisablePpuProgSlaveStruct(base);
1236 }
1237 }
1238 #else
1239 CY_UNUSED_PARAMETER(base);
1240 #endif
1241
1242 return status;
1243 }
1244 /** \} group_prot_functions_ppu_prog */
1245 #endif /* (CY_IP_M4CPUSS) && defined (CY_IP_MXPERI_VERSION) && (CY_IP_MXPERI_VERSION == 1U) */
1246 /** \} group_prot_functions */
1247 /** \} group_prot */
1248
1249 #if defined(__cplusplus)
1250 }
1251 #endif
1252
1253 #endif /* defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) */
1254
1255 #endif /* CY_PROT_H */
1256
