1 /***************************************************************************//**
2 * \file cy_smartio.h
3 * \version 1.0.3
4 *
5 * \brief
6 * Provides an API declaration of the Smart I/O driver
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_smartio
28 * \{
29 * The Smart I/O driver provides an API to configure and access the Smart I/O hardware
30 * present between the GPIOs (pins) and HSIOMs (pin muxes) on select device ports.
31 *
32 * The functions and other declarations used in this driver are in cy_smartio.h.
33 * You can include cy_pdl.h to get access to all functions
34 * and declarations in the PDL.
35 *
36 * It can be used to perform simple logic operations on peripheral and GPIO signals at
37 * the GPIO port. Features include,
38 *
39 * 1. Purely combinatorial logic using 8 Look-Up Tables (LUT).
40 * 2. Mixed sequential and combinatorial logic using 8 LUTs and 1 Data Unit (DU).
41 * 3. Counters and shift registers using 8-bit multi-function DU (simplified ALU).
42 * 4. Operational in device active, sleep and deep-sleep power modes.
43 *
44 * \section group_smartio_configuration Configuration Considerations
45 *
46 * \subsection group_smartio_routing_fabric Routing Fabric
47 *
48 * The Smart I/O routing fabric is divided into two portions, where each portion is capable
49 * of accepting half of the data or GPIO signals. The LUTs have the following structure.
50 *
51 * - LUT 7...4 are capable of accepting signals from io/chip 7...4 as inputs.
52 * - LUT 3...0 are capable of accepting signals from io/chip 3...0 as inputs.
53 * - The LUTs can accept any LUT output as an input.
54 * - Each LUT output is dedicated to the corresponding output io/chip terminal. For
55 * example, LUT 0 can go to either io0 terminal output or chip0 terminal output or both.
56 *
57 * \subsection group_smartio_single_lut Single Source LUT Input
58 *
59 * If a LUT is used, all three inputs to the LUT must be designated. For example, even If a LUT is
60 * used to accept a single source as its input, all three inputs must accept that same signal. The
61 * lookup table should then be designed such that it only changes the output value when all
62 * three inputs satisfy the same condition. For example, consider the case where the signal on
63 * data0 must be inverted before being passed to io0. LUT0 accepts chip0 as input 0, 1 and 2.
64 * The truth table is defined such that it outputs a logic 1 only when the inputs are all 0.
65 *
66 * \subsection group_smartio_clk_rst Clock and Reset Behavior
67 *
68 * The Smart I/O hardware drives its synchronous elements using a single clock source.
69 * Depending on the clock source, the Smart I/O will have different reset behaviors, which
70 * will reset all the flip-flops in the LUTs and synchronizers to logic 0. The configuration
71 * registers will retain their values unless coming out of Power on Reset (POR). Notes:
72 *
73 * - If the block is only disabled, the values in the LUT flip-flips and I/O synchronizers are
74 * held as long as the chip remains in a valid power mode.
75 * - The selected clock for the fabric's synchronous logic is not phase aligned with other
76 * synchronous logic on the chip operating on the same clock. Therefore, communication between
77 * the Smart I/O and other synchronous logic should be treated as asynchronous (just as the
78 * communication between I/O input signals and other synchronous logic should be treated as
79 * asynchronous)
80 *
81 * <table class="doxtable">
82 * <tr>
83 * <th>Clock Source</th>
84 * <th>Reset Behavior</th>
85 * <th>Enable Delay</th>
86 * <th>Description</th>
87 * </tr>
88 * <tr>
89 * <td>io/chip 7...0</td>
90 * <td>Reset on POR</td>
91 * <td>2 clock edges</td>
92 * <td>If chosen as the clock source, that particular signal cannot also be used as an input
93 * to a LUT as it may cause a race condition. The fabric will be enabled after 2 clock
94 * edges of the signal on the gpio terminal.</td>
95 * </tr>
96 * <tr>
97 * <td>Divided Clock (Active)</td>
98 * <td>Reset when going to Deep Sleep, Hibernate or POR</td>
99 * <td>2 clock edges</td>
100 * <td>The fabric will be enabled after 2 clock edges of the divided clock. Any synchronous
101 * logic in the LUTs will be reset to 0 when in chip deep-sleep or hibernate modes.</td>
102 * </tr>
103 * <tr>
104 * <td>Divided Clock (Deep-Sleep)</td>
105 * <td>Reset when going to Hibernate or POR</td>
106 * <td>2 clock edges</td>
107 * <td>The fabric will be enabled after 2 clock edges of the divided clock. Any synchronous
108 * logic in the LUTs will be reset to 0 when in hibernate mode.</td>
109 * </tr>
110 * <tr>
111 * <td>Divided Clock (Hibernate)</td>
112 * <td>Reset on POR</td>
113 * <td>2 clock edges</td>
114 * <td>The fabric will be enabled after 2 clock edges of the divided clock.</td>
115 * </tr>
116 * <tr>
117 * <td>LFCLK</td>
118 * <td>Reset when going to Hibernate and POR</td>
119 * <td>2 clock edges</td>
120 * <td>The fabric will be enabled after 2 clock edges of the low frequency clock (LFCLK).
121 * Any synchronous logic in the LUTs will be reset to 0 when in hibernate mode.</td>
122 * </tr>
123 * <tr>
124 * <td>Asynchronous</td>
125 * <td>Reset on POR</td>
126 * <td>3 clock edges of SYSCLK</td>
127 * <td>The fabric will be enabled after 3 clock edges of the clk_peri source.</td>
128 * </tr>
129 * </table>
130 *
131 * \subsection group_smartio_sync_req Signal Synchronization Requirement
132 *
133 * If any of the signals coming in through the Smart I/O terminals are meant to be used
134 * in sequential elements in the LUTs, the terminal synchronizer must first be used to synchronize
135 * that signal to the Component clock. For example, if the signal on io0 must be used in LUT0 in
136 * Sequential output mode, the synchronization for io0 terminal should be enabled for reliable
137 * operation.
138 *
139 * \subsection group_smartio_comb_feedback LUT Combinatorial Feedback
140 *
141 * Since the LUTs can be configured as purely (or partially) combinatorial elements and since they
142 * can chain to each other in any fashion, combinatorial timing loops can occur. This causes
143 * oscillations that burn power and create unpredictable behavior. If a feedback is required, the
144 * signals should always go through a flip-flop before feeding back. For example, the following is a
145 * potentially problematic design; LUT1 and LUT2 are configured in combinatorial mode, where their
146 * respective outputs feed into the inputs of the other. This will result in oscillations.
147 * To prevent it, one of the LUTs should be configured to Gated Output mode.
148 *
149 * \subsection group_smartio_lpm Low Power Mode
150 *
151 * The Smart I/O hardware is capable of operating during chip Deep-Sleep mode. The block has
152 * the following requirements when operating in this mode:
153 *
154 * - All sequential elements must be clocked by a valid clock in these power domains. Refer to
155 * \ref group_smartio_clk_rst for more details.
156 * - All signals in the block (including the clock) must be less than 1 MHz when in Deep-Sleep
157 * mode.
158 * - The hold override functionality should be enabled when entering Deep-Sleep mode.
159 * This functionality should then be disabled when the chip is not in this mode.
160 *
161 * \section group_smartio_more_information More Information
162 *
163 * Refer to the technical reference manual (TRM) and the device datasheet.
164 *
165 * \section group_smartio_changelog Changelog
166 * <table class="doxtable">
167 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
168 * <tr>
169 * <td>1.0.3</td>
170 * <td>Updated driver guards.</td>
171 * <td>Support Added for future devices of the CAT1B.</td>
172 * </tr>
173 * <tr>
174 * <td>1.0.2</td>
175 * <td>Documented MISRA 2012 violations.</td>
176 * <td>MISRA 2012 compliance.</td>
177 * </tr>
178 * <tr>
179 * <td>1.0.1</td>
180 * <td>Minor documentation updates.</td>
181 * <td>Documentation enhancement.</td>
182 * </tr>
183 * <tr>
184 * <td>1.0</td>
185 * <td>The initial version.</td>
186 * <td></td>
187 * </tr>
188 * </table>
189 *
190 * \defgroup group_smartio_macros Macros
191 * \defgroup group_smartio_functions Functions
192 * \{
193 * \defgroup group_smartio_functions_init Initialization Functions
194 * \defgroup group_smartio_functions_general General Functions
195 * \defgroup group_smartio_functions_lut LUT Functions
196 * \defgroup group_smartio_functions_du Data Unit Functions
197 * \}
198 * \defgroup group_smartio_data_structures Data Structures
199 * \defgroup group_smartio_enums Enumerated Types
200 */
201
202 #if !defined(CY_SMARTIO_H)
203 #define CY_SMARTIO_H
204
205 #include "cy_device.h"
206
207 #if (defined (CY_IP_MXS40IOSS) || defined(CY_IP_MXS40SIOSS) || defined(CY_IP_MXS22IOSS))
208
209 #include <stdbool.h>
210 #include <stddef.h>
211 #include "cy_syslib.h"
212
213 #if defined(__cplusplus)
214 extern "C" {
215 #endif
216
217 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 12, \
218 'Value extracted from _FLD2VAL macro will not exceed enum range.')
219
220 /** \addtogroup group_smartio_macros
221 * \{
222 */
223
224 /** Driver major version */
225 #define CY_SMARTIO_DRV_VERSION_MAJOR 1
226
227 /** Driver minor version */
228 #define CY_SMARTIO_DRV_VERSION_MINOR 0
229
230 /** SmartIO driver ID */
231 #define CY_SMARTIO_ID CY_PDL_DRV_ID(0x42u)
232
233 /**
234 * \defgroup group_smartio_channels Smart I/O channel selection
235 * \{
236 * Constants for selecting the Smart I/O channels
237 */
238 #define CY_SMARTIO_CHANNEL_NONE 0x00u /**< No channels */
239 #define CY_SMARTIO_CHANNEL0 0x01u /**< Channel 0 (chip0 <-> io0) */
240 #define CY_SMARTIO_CHANNEL1 0x02u /**< Channel 1 (chip1 <-> io1) */
241 #define CY_SMARTIO_CHANNEL2 0x04u /**< Channel 2 (chip2 <-> io2) */
242 #define CY_SMARTIO_CHANNEL3 0x08u /**< Channel 3 (chip3 <-> io3) */
243 #define CY_SMARTIO_CHANNEL4 0x10u /**< Channel 4 (chip4 <-> io4) */
244 #define CY_SMARTIO_CHANNEL5 0x20u /**< Channel 5 (chip5 <-> io5) */
245 #define CY_SMARTIO_CHANNEL6 0x40u /**< Channel 6 (chip6 <-> io6) */
246 #define CY_SMARTIO_CHANNEL7 0x80u /**< Channel 7 (chip7 <-> io7) */
247 #define CY_SMARTIO_CHANNEL_ALL 0xffu /**< All channels */
248 /** \} */
249
250 /** \} group_smartio_macros */
251
252
253 /***************************************
254 * Constants
255 ***************************************/
256
257 /** \cond INTERNAL */
258 #define CY_SMARTIO_ENABLE 1UL
259 #define CY_SMARTIO_DISABLE 0UL
260 #define CY_SMARTIO_DEINIT 0UL
261 #define CY_SMARTIO_LUTMAX 8u
262 /** \endcond */
263
264 /***************************************
265 * Enumerations
266 ***************************************/
267 /**
268 * \addtogroup group_smartio_enums
269 * \{
270 */
271
272 /**
273 * Smart I/O driver error codes
274 */
275 typedef enum
276 {
277 CY_SMARTIO_SUCCESS = 0x00u, /**< Returned successful */
278 CY_SMARTIO_BAD_PARAM = CY_SMARTIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
279 CY_SMARTIO_LOCKED = CY_SMARTIO_ID | CY_PDL_STATUS_ERROR | 0x02u, /**< Smart I/O is not disabled */
280 } cy_en_smartio_status_t;
281
282 /**
283 * Smart I/O clock selection
284 */
285 typedef enum {
286 CY_SMARTIO_CLK_IO0 = 0, /**< Clock sourced from signal on io0 */
287 CY_SMARTIO_CLK_IO1 = 1, /**< Clock sourced from signal on io1 */
288 CY_SMARTIO_CLK_IO2 = 2, /**< Clock sourced from signal on io2 */
289 CY_SMARTIO_CLK_IO3 = 3, /**< Clock sourced from signal on io3 */
290 CY_SMARTIO_CLK_IO4 = 4, /**< Clock sourced from signal on io4 */
291 CY_SMARTIO_CLK_IO5 = 5, /**< Clock sourced from signal on io5 */
292 CY_SMARTIO_CLK_IO6 = 6, /**< Clock sourced from signal on io6 */
293 CY_SMARTIO_CLK_IO7 = 7, /**< Clock sourced from signal on io7 */
294 CY_SMARTIO_CLK_CHIP0 = 8, /**< Clock sourced from signal on chip0 */
295 CY_SMARTIO_CLK_CHIP1 = 9, /**< Clock sourced from signal on chip1 */
296 CY_SMARTIO_CLK_CHIP2 = 10, /**< Clock sourced from signal on chip2 */
297 CY_SMARTIO_CLK_CHIP3 = 11, /**< Clock sourced from signal on chip3 */
298 CY_SMARTIO_CLK_CHIP4 = 12, /**< Clock sourced from signal on chip4 */
299 CY_SMARTIO_CLK_CHIP5 = 13, /**< Clock sourced from signal on chip5 */
300 CY_SMARTIO_CLK_CHIP6 = 14, /**< Clock sourced from signal on chip6 */
301 CY_SMARTIO_CLK_CHIP7 = 15, /**< Clock sourced from signal on chip7 */
302 CY_SMARTIO_CLK_DIVACT = 16, /**< Clock sourced from a peripheral clock divider (Active) */
303 CY_SMARTIO_CLK_DIVDS = 17, /**< Clock sourced from a peripheral clock divider (Deep-Sleep) */
304 CY_SMARTIO_CLK_DIVHIB = 18, /**< Clock sourced from a peripheral clock divider (Hibernate) */
305 CY_SMARTIO_CLK_LFCLK = 19, /**< Clock sourced from LFCLK */
306 CY_SMARTIO_CLK_GATED = 20, /**< Disables the clock. Used when turning off the block */
307 CY_SMARTIO_CLK_ASYNC = 31, /**< Asynchronous operation (only allow combinatorial logic) */
308 }cy_en_smartio_clksrc_t;
309
310 /**
311 * Smart I/O LUT number
312 */
313 typedef enum {
314 CY_SMARTIO_LUT0 = 0, /**< Look-Up-Table #0 */
315 CY_SMARTIO_LUT1 = 1, /**< Look-Up-Table #1 */
316 CY_SMARTIO_LUT2 = 2, /**< Look-Up-Table #2 */
317 CY_SMARTIO_LUT3 = 3, /**< Look-Up-Table #3 */
318 CY_SMARTIO_LUT4 = 4, /**< Look-Up-Table #4 */
319 CY_SMARTIO_LUT5 = 5, /**< Look-Up-Table #5 */
320 CY_SMARTIO_LUT6 = 6, /**< Look-Up-Table #6 */
321 CY_SMARTIO_LUT7 = 7, /**< Look-Up-Table #7 */
322 }cy_en_smartio_lutnum_t;
323
324 /**
325 * Smart I/O input trigger number
326 */
327 typedef enum {
328 CY_SMARTIO_TR0 = 0, /**< Input trigger #0 */
329 CY_SMARTIO_TR1 = 1, /**< Input trigger #1 */
330 CY_SMARTIO_TR2 = 2, /**< Input trigger #2 */
331 }cy_en_smartio_trnum_t;
332
333 /**
334 * Smart I/O Data Unit's input "DATA" number
335 */
336 typedef enum {
337 CY_SMARTIO_DATA0 = 0, /**< Input DATA #0 */
338 CY_SMARTIO_DATA1 = 1, /**< Input DATA #1 */
339 }cy_en_smartio_datanum_t;
340
341 /**
342 * Smart I/O LUT input trigger source
343 */
344 typedef enum {
345 CY_SMARTIO_LUTTR_DU_OUT = 0, /**< Data Unit output */
346 CY_SMARTIO_LUTTR_LUT0_OUT = 0, /**< LUT0 output */
347 CY_SMARTIO_LUTTR_LUT1_OUT = 1, /**< LUT1 output */
348 CY_SMARTIO_LUTTR_LUT2_OUT = 2, /**< LUT2 output */
349 CY_SMARTIO_LUTTR_LUT3_OUT = 3, /**< LUT3 output */
350 CY_SMARTIO_LUTTR_LUT4_OUT = 4, /**< LUT4 output */
351 CY_SMARTIO_LUTTR_LUT5_OUT = 5, /**< LUT5 output */
352 CY_SMARTIO_LUTTR_LUT6_OUT = 6, /**< LUT6 output */
353 CY_SMARTIO_LUTTR_LUT7_OUT = 7, /**< LUT7 output */
354 CY_SMARTIO_LUTTR_CHIP0 = 8, /**< Chip signal 0 (for LUT 0,1,2,3) */
355 CY_SMARTIO_LUTTR_CHIP4 = 8, /**< Chip signal 4 (for LUT 4,5,6,7) */
356 CY_SMARTIO_LUTTR_CHIP1 = 9, /**< Chip signal 1 (for LUT 0,1,2,3) */
357 CY_SMARTIO_LUTTR_CHIP5 = 9, /**< Chip signal 5 (for LUT 4,5,6,7) */
358 CY_SMARTIO_LUTTR_CHIP2 = 10, /**< Chip signal 2 (for LUT 0,1,2,3) */
359 CY_SMARTIO_LUTTR_CHIP6 = 10, /**< Chip signal 6 (for LUT 4,5,6,7) */
360 CY_SMARTIO_LUTTR_CHIP3 = 11, /**< Chip signal 3 (for LUT 0,1,2,3) */
361 CY_SMARTIO_LUTTR_CHIP7 = 11, /**< Chip signal 7 (for LUT 4,5,6,7) */
362 CY_SMARTIO_LUTTR_IO0 = 12, /**< I/O signal 0 (for LUT 0,1,2,3) */
363 CY_SMARTIO_LUTTR_IO4 = 12, /**< I/O signal 4 (for LUT 4,5,6,7) */
364 CY_SMARTIO_LUTTR_IO1 = 13, /**< I/O signal 1 (for LUT 0,1,2,3) */
365 CY_SMARTIO_LUTTR_IO5 = 13, /**< I/O signal 5 (for LUT 4,5,6,7) */
366 CY_SMARTIO_LUTTR_IO2 = 14, /**< I/O signal 2 (for LUT 0,1,2,3) */
367 CY_SMARTIO_LUTTR_IO6 = 14, /**< I/O signal 6 (for LUT 4,5,6,7) */
368 CY_SMARTIO_LUTTR_IO3 = 15, /**< I/O signal 3 (for LUT 0,1,2,3) */
369 CY_SMARTIO_LUTTR_IO7 = 15, /**< I/O signal 7 (for LUT 4,5,6,7) */
370 CY_SMARTIO_LUTTR_INVALID = 255, /**< Invalid input trigger selection */
371 }cy_en_smartio_luttr_t;
372
373 /**
374 * Smart I/O LUT opcode
375 */
376 typedef enum {
377 CY_SMARTIO_LUTOPC_COMB = 0, /**< Combinatorial output */
378 CY_SMARTIO_LUTOPC_GATED_TR2 = 1, /**< TR2 gated, Combinatorial output */
379 CY_SMARTIO_LUTOPC_GATED_OUT = 2, /**< Sequential (gated) output */
380 CY_SMARTIO_LUTOPC_ASYNC_SR = 3, /**< Asynchronous Set/Reset mode */
381 }cy_en_smartio_lutopc_t;
382
383 /**
384 * Smart I/O Data Unit input trigger source
385 */
386 typedef enum {
387 CY_SMARTIO_DUTR_ZERO = 0, /**< Constant 0 */
388 CY_SMARTIO_DUTR_ONE = 1, /**< Constant 1 */
389 CY_SMARTIO_DUTR_DU_OUT = 2, /**< Data Unit output */
390 CY_SMARTIO_DUTR_LUT0_OUT = 3, /**< LUT0 output */
391 CY_SMARTIO_DUTR_LUT1_OUT = 4, /**< LUT1 output */
392 CY_SMARTIO_DUTR_LUT2_OUT = 5, /**< LUT2 output */
393 CY_SMARTIO_DUTR_LUT3_OUT = 6, /**< LUT3 output */
394 CY_SMARTIO_DUTR_LUT4_OUT = 7, /**< LUT4 output */
395 CY_SMARTIO_DUTR_LUT5_OUT = 8, /**< LUT5 output */
396 CY_SMARTIO_DUTR_LUT6_OUT = 9, /**< LUT6 output */
397 CY_SMARTIO_DUTR_LUT7_OUT = 10, /**< LUT7 output */
398 CY_SMARTIO_DUTR_INVALID = 255, /**< Invalid input trigger selected */
399 }cy_en_smartio_dutr_t;
400
401 /**
402 * Smart I/O Data Unit input "DATA" source
403 */
404 typedef enum {
405 CY_SMARTIO_DUDATA_ZERO = 0, /**< Constant 0 */
406 CY_SMARTIO_DUDATA_CHIP = 1, /**< Chip signal [7:0] */
407 CY_SMARTIO_DUDATA_IO = 2, /**< I/O signal [7:0] */
408 CY_SMARTIO_DUDATA_DATAREG = 3, /**< SMARTIO.DATA register */
409 }cy_en_smartio_dudata_t;
410
411 /**
412 * Smart I/O Data Unit opcode
413 */
414 typedef enum {
415 CY_SMARTIO_DUOPC_INCR = 1, /**< Increment (Count up) */
416 CY_SMARTIO_DUOPC_DECR = 2, /**< Decrement (Count down) */
417 CY_SMARTIO_DUOPC_INCR_WRAP = 3, /**< Increment and wrap-around (Count up and wrap) */
418 CY_SMARTIO_DUOPC_DECR_WRAP = 4, /**< Decrement and wrap-around (Count down and wrap) */
419 CY_SMARTIO_DUOPC_INCR_DECR = 5, /**< Increment or decrement (Count up/down) */
420 CY_SMARTIO_DUOPC_INCR_DECR_WRAP = 6, /**< Increment or decrement with wrap-around (Count up/down and wrap) */
421 CY_SMARTIO_DUOPC_ROR = 7, /**< Rotate right (shift right and wrap) */
422 CY_SMARTIO_DUOPC_SHR = 8, /**< Shift right and shift data in through MSB */
423 CY_SMARTIO_DUOPC_AND_OR = 9, /**< out = ((DATA0 & DATA1) == 0) ? 0 : 1 */
424 CY_SMARTIO_DUOPC_SHR_MAJ3 = 10, /**< Majority 3 (Check if 2 out of 3 LSB bits are logic 1) */
425 CY_SMARTIO_DUOPC_SHR_EQL = 11, /**< Check for equality against DATA1. Also perform Shift right */
426 }cy_en_smartio_duopc_t;
427
428 /**
429 * Smart I/O Data Unit operation bit size
430 */
431 typedef enum {
432 CY_SMARTIO_DUSIZE_1 = 0, /**< 1-bit size/width operand */
433 CY_SMARTIO_DUSIZE_2 = 1, /**< 2-bits size/width operand */
434 CY_SMARTIO_DUSIZE_3 = 2, /**< 3-bits size/width operand */
435 CY_SMARTIO_DUSIZE_4 = 3, /**< 4-bits size/width operand */
436 CY_SMARTIO_DUSIZE_5 = 4, /**< 5-bits size/width operand */
437 CY_SMARTIO_DUSIZE_6 = 5, /**< 6-bits size/width operand */
438 CY_SMARTIO_DUSIZE_7 = 6, /**< 7-bits size/width operand */
439 CY_SMARTIO_DUSIZE_8 = 7, /**< 8-bits size/width operand */
440 }cy_en_smartio_dusize_t;
441
442 /** \} group_smartio_enums */
443
444
445 /***************************************
446 * Configuration Structures
447 ***************************************/
448
449 /**
450 * \addtogroup group_smartio_data_structures
451 * \{
452 */
453
454 /** LUT configuration structure */
455 typedef struct {
456 cy_en_smartio_luttr_t tr0; /**< LUT input trigger 0 source selection */
457 cy_en_smartio_luttr_t tr1; /**< LUT input trigger 1 source selection */
458 cy_en_smartio_luttr_t tr2; /**< LUT input trigger 2 source selection */
459 cy_en_smartio_lutopc_t opcode; /**< LUT Opcode */
460 uint8_t lutMap; /**< LUT output mapping */
461 }cy_stc_smartio_lutcfg_t;
462
463 /** Data Unit (DU) configuration structure */
464 typedef struct {
465 cy_en_smartio_dutr_t tr0; /**< DU input trigger 0 source selection */
466 cy_en_smartio_dutr_t tr1; /**< DU input trigger 1 source selection */
467 cy_en_smartio_dutr_t tr2; /**< DU input trigger 2 source selection */
468 cy_en_smartio_dudata_t data0; /**< DU input DATA0 source selection */
469 cy_en_smartio_dudata_t data1; /**< DU input DATA1 source selection */
470 cy_en_smartio_duopc_t opcode; /**< DU op-code */
471 cy_en_smartio_dusize_t size; /**< DU operation bit size */
472 uint8_t dataReg; /**< DU DATA register value */
473 }cy_stc_smartio_ducfg_t;
474
475 /** Smart I/O configuration structure */
476 typedef struct {
477 cy_en_smartio_clksrc_t clkSrc; /**< Smart I/O instance clock source */
478 uint8_t bypassMask; /**< Smart I/O io<->chip channel bypass mask */
479 uint8_t ioSyncEn; /**< Synchronization enable/disable for I/O terminals */
480 uint8_t chipSyncEn; /**< Synchronization enable/disable for Chip terminals */
481 const cy_stc_smartio_lutcfg_t* lutCfg0; /**< Pointer to LUT0 configuration (NULL if not used) */
482 const cy_stc_smartio_lutcfg_t* lutCfg1; /**< Pointer to LUT1 configuration (NULL if not used) */
483 const cy_stc_smartio_lutcfg_t* lutCfg2; /**< Pointer to LUT2 configuration (NULL if not used) */
484 const cy_stc_smartio_lutcfg_t* lutCfg3; /**< Pointer to LUT3 configuration (NULL if not used) */
485 const cy_stc_smartio_lutcfg_t* lutCfg4; /**< Pointer to LUT4 configuration (NULL if not used) */
486 const cy_stc_smartio_lutcfg_t* lutCfg5; /**< Pointer to LUT5 configuration (NULL if not used) */
487 const cy_stc_smartio_lutcfg_t* lutCfg6; /**< Pointer to LUT6 configuration (NULL if not used) */
488 const cy_stc_smartio_lutcfg_t* lutCfg7; /**< Pointer to LUT7 configuration (NULL if not used) */
489 const cy_stc_smartio_ducfg_t* duCfg; /**< Pointer to Data Unit configuration (NULL if not used) */
490 bool hldOvr; /**< Hold override enable (true) / disable (false) */
491 }cy_stc_smartio_config_t;
492
493 /** \} group_smartio_data_structures */
494
495
496 /***************************************
497 * Function Prototypes
498 ***************************************/
499
500 /**
501 * \addtogroup group_smartio_functions
502 * \{
503 */
504
505 /**
506 * \addtogroup group_smartio_functions_init
507 * \{
508 */
509 cy_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smartio_config_t* config);
510 void Cy_SmartIO_Deinit(SMARTIO_PRT_Type* base);
511 void Cy_SmartIO_Enable(SMARTIO_PRT_Type* base);
512 void Cy_SmartIO_Disable(SMARTIO_PRT_Type* base);
513 /** \} group_smartio_functions_init */
514
515 /**
516 * \addtogroup group_smartio_functions_general
517 * \{
518 */
519 __STATIC_INLINE uint8_t Cy_SmartIO_GetChBypass(SMARTIO_PRT_Type* base);
520 cy_en_smartio_status_t Cy_SmartIO_SetChBypass(SMARTIO_PRT_Type* base, uint8_t bypassMask);
521 __STATIC_INLINE cy_en_smartio_clksrc_t Cy_SmartIO_GetClock(SMARTIO_PRT_Type* base);
522 cy_en_smartio_status_t Cy_SmartIO_SetClock(SMARTIO_PRT_Type* base, cy_en_smartio_clksrc_t clkSrc);
523 __STATIC_INLINE uint8_t Cy_SmartIO_GetIoSync(SMARTIO_PRT_Type* base);
524 cy_en_smartio_status_t Cy_SmartIO_SetIoSync(SMARTIO_PRT_Type* base, uint8_t ioSyncEn);
525 __STATIC_INLINE uint8_t Cy_SmartIO_GetChipSync(SMARTIO_PRT_Type* base);
526 cy_en_smartio_status_t Cy_SmartIO_SetChipSync(SMARTIO_PRT_Type* base, uint8_t chipSyncEn);
527 cy_en_smartio_status_t Cy_SmartIO_HoldOverride(SMARTIO_PRT_Type* base, bool hldOvr);
528 /** \} group_smartio_functions_general */
529
530 /**
531 * \addtogroup group_smartio_functions_lut
532 * \{
533 */
534 cy_en_smartio_luttr_t Cy_SmartIO_GetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_trnum_t trNum);
535 cy_en_smartio_status_t Cy_SmartIO_SetLutTr(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_trnum_t trNum, cy_en_smartio_luttr_t trSrc);
536 cy_en_smartio_status_t Cy_SmartIO_SetLutTrAll(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_luttr_t trSrc);
537 __STATIC_INLINE cy_en_smartio_lutopc_t Cy_SmartIO_GetLutOpcode(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum);
538 cy_en_smartio_status_t Cy_SmartIO_SetLutOpcode(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, cy_en_smartio_lutopc_t opcode);
539 __STATIC_INLINE uint8_t Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum);
540 cy_en_smartio_status_t Cy_SmartIO_SetLutMap(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum, uint8_t lutMap);
541 /** \} group_smartio_functions_lut */
542
543 /**
544 * \addtogroup group_smartio_functions_du
545 * \{
546 */
547 cy_en_smartio_dutr_t Cy_SmartIO_GetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_trnum_t trNum);
548 cy_en_smartio_status_t Cy_SmartIO_SetDuTr(SMARTIO_PRT_Type* base, cy_en_smartio_trnum_t trNum, cy_en_smartio_dutr_t trSrc);
549 cy_en_smartio_status_t Cy_SmartIO_SetDuTrAll(SMARTIO_PRT_Type* base, cy_en_smartio_dutr_t trSrc);
550 __STATIC_INLINE cy_en_smartio_dudata_t Cy_SmartIO_GetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum);
551 cy_en_smartio_status_t Cy_SmartIO_SetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum, cy_en_smartio_dudata_t dataSrc);
552 __STATIC_INLINE cy_en_smartio_duopc_t Cy_SmartIO_GetDuOpc(SMARTIO_PRT_Type* base);
553 __STATIC_INLINE cy_en_smartio_dusize_t Cy_SmartIO_GetDuSize(SMARTIO_PRT_Type* base);
554 cy_en_smartio_status_t Cy_SmartIO_SetDuOperation(SMARTIO_PRT_Type* base, cy_en_smartio_duopc_t opcode, cy_en_smartio_dusize_t size);
555 __STATIC_INLINE uint8_t Cy_SmartIO_GetDataReg(SMARTIO_PRT_Type* base);
556 cy_en_smartio_status_t Cy_SmartIO_SetDataReg(SMARTIO_PRT_Type* base, uint8_t dataReg);
557 /** \} group_smartio_functions_du */
558
559
560 /***************************************
561 * Functions
562 ***************************************/
563
564 /**
565 * \addtogroup group_smartio_functions_general
566 * \{
567 */
568
569 /*******************************************************************************
570 * Function Name: Cy_SmartIO_GetChBypass
571 ****************************************************************************//**
572 *
573 * \brief Gets the bypass/route state of all 8 channels in the Smart I/O
574 *
575 * <table class="doxtable">
576 * <tr><th>Bypass bit</th><th> Channel </th></tr>
577 * <tr><td> 0 </td><td> io0<->chip0 </td></tr>
578 * <tr><td> 1 </td><td> io1<->chip1 </td></tr>
579 * <tr><td> 2 </td><td> io2<->chip2 </td></tr>
580 * <tr><td> 3 </td><td> io3<->chip3 </td></tr>
581 * <tr><td> 4 </td><td> io4<->chip4 </td></tr>
582 * <tr><td> 5 </td><td> io5<->chip5 </td></tr>
583 * <tr><td> 6 </td><td> io6<->chip6 </td></tr>
584 * <tr><td> 7 </td><td> io7<->chip7 </td></tr>
585 * </table>
586 *
587 * \param base
588 * Pointer to the Smart I/O base address
589 *
590 * \return
591 * Bypass/Route state of 8 io<->chip channels (bits [7:0]): 1=bypass, 0=routed.
592 *
593 * \funcusage
594 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetChBypass
595 *
596 *******************************************************************************/
Cy_SmartIO_GetChBypass(SMARTIO_PRT_Type * base)597 __STATIC_INLINE uint8_t Cy_SmartIO_GetChBypass(SMARTIO_PRT_Type* base)
598 {
599 return((uint8_t)_FLD2VAL(SMARTIO_PRT_CTL_BYPASS, SMARTIO_PRT_CTL(base)));
600 }
601
602
603 /*******************************************************************************
604 * Function Name: Cy_SmartIO_GetClock
605 ****************************************************************************//**
606 *
607 * \brief Gets the clock source of the Smart I/O.
608 *
609 * \param base
610 * Pointer to the Smart I/O base address
611 *
612 * \return
613 * Clock source
614 *
615 * \funcusage
616 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetClock
617 *
618 *******************************************************************************/
Cy_SmartIO_GetClock(SMARTIO_PRT_Type * base)619 __STATIC_INLINE cy_en_smartio_clksrc_t Cy_SmartIO_GetClock(SMARTIO_PRT_Type* base)
620 {
621 return((cy_en_smartio_clksrc_t)_FLD2VAL(SMARTIO_PRT_CTL_CLOCK_SRC, SMARTIO_PRT_CTL(base)));
622 }
623
624
625 /*******************************************************************************
626 * Function Name: Cy_SmartIO_GetIoSync
627 ****************************************************************************//**
628 *
629 * \brief Gets the synchronization mode of the 8 I/O terminals.
630 *
631 * <table class="doxtable">
632 * <tr><th> Sync bit </th><th> I/O terminal </th></tr>
633 * <tr><td> 0 </td><td> io0 </td></tr>
634 * <tr><td> 1 </td><td> io1 </td></tr>
635 * <tr><td> 2 </td><td> io2 </td></tr>
636 * <tr><td> 3 </td><td> io3 </td></tr>
637 * <tr><td> 4 </td><td> io4 </td></tr>
638 * <tr><td> 5 </td><td> io5 </td></tr>
639 * <tr><td> 6 </td><td> io6 </td></tr>
640 * <tr><td> 7 </td><td> io7 </td></tr>
641 * </table>
642 *
643 * \param base
644 * Pointer to the Smart I/O base address
645 *
646 * \return
647 * Sync mode of 8 I/O terminals (bits [7:0]): 1=sync, 0=no sync.
648 *
649 * \funcusage
650 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetIoSync
651 *
652 *******************************************************************************/
Cy_SmartIO_GetIoSync(SMARTIO_PRT_Type * base)653 __STATIC_INLINE uint8_t Cy_SmartIO_GetIoSync(SMARTIO_PRT_Type* base)
654 {
655 return((uint8_t)_FLD2VAL(SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN, SMARTIO_PRT_SYNC_CTL(base)));
656 }
657
658
659 /*******************************************************************************
660 * Function Name: Cy_SmartIO_GetChipSync
661 ****************************************************************************//**
662 *
663 * \brief Gets the synchronization mode of the 8 chip-side terminals.
664 *
665 * <table class="doxtable">
666 * <tr><th> Sync bit </th><th> chip terminal </th></tr>
667 * <tr><td> 0 </td><td> chip0 </td></tr>
668 * <tr><td> 1 </td><td> chip1 </td></tr>
669 * <tr><td> 2 </td><td> chip2 </td></tr>
670 * <tr><td> 3 </td><td> chip3 </td></tr>
671 * <tr><td> 4 </td><td> chip4 </td></tr>
672 * <tr><td> 5 </td><td> chip5 </td></tr>
673 * <tr><td> 6 </td><td> chip6 </td></tr>
674 * <tr><td> 7 </td><td> chip7 </td></tr>
675 * </table>
676 *
677 * \param base
678 * Pointer to the Smart I/O base address
679 *
680 * \return
681 * Sync mode of 8 chip-side terminals (bits [7:0]): 1=sync, 0=no sync.
682 *
683 * \funcusage
684 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetChipSync
685 *
686 *******************************************************************************/
Cy_SmartIO_GetChipSync(SMARTIO_PRT_Type * base)687 __STATIC_INLINE uint8_t Cy_SmartIO_GetChipSync(SMARTIO_PRT_Type* base)
688 {
689 return((uint8_t)_FLD2VAL(SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN, SMARTIO_PRT_SYNC_CTL(base)));
690 }
691
692 /** \} group_smartio_functions_general */
693
694 /**
695 * \addtogroup group_smartio_functions_lut
696 * \{
697 */
698
699 /*******************************************************************************
700 * Function Name: Cy_SmartIO_GetLutOpcode
701 ****************************************************************************//**
702 *
703 * \brief Gets the opcode of the specified LUT.
704 *
705 * \param base
706 * Pointer to the Smart I/O base address
707 *
708 * \param lutNum
709 * LUT index number
710 *
711 * \return
712 * LUT opcode
713 *
714 * \funcusage
715 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetLutOpcode
716 *
717 *******************************************************************************/
Cy_SmartIO_GetLutOpcode(SMARTIO_PRT_Type * base,cy_en_smartio_lutnum_t lutNum)718 __STATIC_INLINE cy_en_smartio_lutopc_t Cy_SmartIO_GetLutOpcode(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum)
719 {
720 return((cy_en_smartio_lutopc_t)(_FLD2VAL(SMARTIO_PRT_LUT_CTL_LUT_OPC, SMARTIO_PRT_LUT_CTL(base, lutNum))));
721 }
722
723
724 /*******************************************************************************
725 * Function Name: Cy_SmartIO_GetLutMap
726 ****************************************************************************//**
727 *
728 * \brief Gets the 3:1 truth table of the specified LUT.
729 *
730 * <table class="doxtable">
731 * <tr><th>tr2</th><th>tr1</th><th>tr0</th><th>lutNum</th></tr>
732 * <tr><td> 0 </td><td> 0 </td><td> 0 </td><td> bit 0 </td></tr>
733 * <tr><td> 0 </td><td> 0 </td><td> 1 </td><td> bit 1 </td></tr>
734 * <tr><td> 0 </td><td> 1 </td><td> 0 </td><td> bit 2 </td></tr>
735 * <tr><td> 0 </td><td> 1 </td><td> 1 </td><td> bit 3 </td></tr>
736 * <tr><td> 1 </td><td> 0 </td><td> 0 </td><td> bit 4 </td></tr>
737 * <tr><td> 1 </td><td> 0 </td><td> 1 </td><td> bit 5 </td></tr>
738 * <tr><td> 1 </td><td> 1 </td><td> 0 </td><td> bit 6 </td></tr>
739 * <tr><td> 1 </td><td> 1 </td><td> 1 </td><td> bit 7 </td></tr>
740 * </table>
741 *
742 * \param base
743 * Pointer to the Smart I/O base address
744 *
745 * \param lutNum
746 * LUT index number
747 *
748 * \return
749 * Bitfield [7:0] mapping of the 3:1 LUT
750 *
751 * \funcusage
752 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetLutMap
753 *
754 *******************************************************************************/
Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type * base,cy_en_smartio_lutnum_t lutNum)755 __STATIC_INLINE uint8_t Cy_SmartIO_GetLutMap(SMARTIO_PRT_Type* base, cy_en_smartio_lutnum_t lutNum)
756 {
757 return((uint8_t)(_FLD2VAL(SMARTIO_PRT_LUT_CTL_LUT, SMARTIO_PRT_LUT_CTL(base, lutNum))));
758 }
759
760 /** \} group_smartio_functions_lut */
761
762 /**
763 * \addtogroup group_smartio_functions_du
764 * \{
765 */
766
767 /*******************************************************************************
768 * Function Name: Cy_SmartIO_GetDuData
769 ****************************************************************************//**
770 *
771 * \brief Gets the data unit's input "data" source.
772 *
773 * \param base
774 * Pointer to the Smart I/O base address
775 *
776 * \param dataNum
777 * Input data number
778 *
779 * \return
780 * Data unit input trigger source
781 *
782 * \funcusage
783 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuData
784 *
785 *******************************************************************************/
Cy_SmartIO_GetDuData(SMARTIO_PRT_Type * base,cy_en_smartio_datanum_t dataNum)786 __STATIC_INLINE cy_en_smartio_dudata_t Cy_SmartIO_GetDuData(SMARTIO_PRT_Type* base, cy_en_smartio_datanum_t dataNum)
787 {
788 return ((dataNum == CY_SMARTIO_DATA0) ?
789 (cy_en_smartio_dudata_t)_FLD2VAL(SMARTIO_PRT_DU_SEL_DU_DATA0_SEL, SMARTIO_PRT_DU_SEL(base)) :
790 (cy_en_smartio_dudata_t)_FLD2VAL(SMARTIO_PRT_DU_SEL_DU_DATA1_SEL, SMARTIO_PRT_DU_SEL(base)));
791 }
792
793
794 /*******************************************************************************
795 * Function Name: Cy_SmartIO_GetDuOpc
796 ****************************************************************************//**
797 *
798 * \brief Gets the data unit's opcode.
799 *
800 * \param base
801 * Pointer to the Smart I/O base address
802 *
803 * \return
804 * Data unit opcode
805 *
806 * \funcusage
807 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuOpc
808 *
809 *******************************************************************************/
Cy_SmartIO_GetDuOpc(SMARTIO_PRT_Type * base)810 __STATIC_INLINE cy_en_smartio_duopc_t Cy_SmartIO_GetDuOpc(SMARTIO_PRT_Type* base)
811 {
812 return ((cy_en_smartio_duopc_t)_FLD2VAL(SMARTIO_PRT_DU_CTL_DU_OPC, SMARTIO_PRT_DU_CTL(base)));
813 }
814
815
816 /*******************************************************************************
817 * Function Name: Cy_SmartIO_GetDuSize
818 ****************************************************************************//**
819 *
820 * \brief Gets the data unit's opcode operand bit-width.
821 *
822 * \param base
823 * Pointer to the Smart I/O base address
824 *
825 * \return
826 * Data unit operand bit-width
827 *
828 * \funcusage
829 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDuSize
830 *
831 *******************************************************************************/
Cy_SmartIO_GetDuSize(SMARTIO_PRT_Type * base)832 __STATIC_INLINE cy_en_smartio_dusize_t Cy_SmartIO_GetDuSize(SMARTIO_PRT_Type* base)
833 {
834 return ((cy_en_smartio_dusize_t)_FLD2VAL(SMARTIO_PRT_DU_CTL_DU_SIZE, SMARTIO_PRT_DU_CTL(base)));
835 }
836
837
838 /*******************************************************************************
839 * Function Name: Cy_SmartIO_GetDataReg
840 ****************************************************************************//**
841 *
842 * \brief Gets the data unit's DATA register value.
843 *
844 * \param base
845 * Pointer to the Smart I/O base address
846 *
847 * \return
848 * DATA register value
849 *
850 * \funcusage
851 * \snippet smartio/snippet/main.c snippet_Cy_SmartIO_GetDataReg
852 *
853 *******************************************************************************/
Cy_SmartIO_GetDataReg(SMARTIO_PRT_Type * base)854 __STATIC_INLINE uint8_t Cy_SmartIO_GetDataReg(SMARTIO_PRT_Type* base)
855 {
856 return ((uint8_t)(SMARTIO_PRT_DATA(base)));
857 }
858
859 /** \} group_smartio_functions_du */
860
861 /** \} group_smartio_functions */
862
863 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8')
864
865 #if defined(__cplusplus)
866 }
867 #endif
868
869 #endif /* (defined (CY_IP_MXS40IOSS) || defined(CY_IP_MXS40SIOSS) || defined(CY_IP_MXS22IOSS)) */
870
871 #endif /* CY_SMARTIO_H */
872
873 /** \} group_smartio */
874
875 /* [] END OF FILE */
876
