1 /***************************************************************************//**
2 * \file cy_device.c
3 * \version 2.30
4 *
5 * This file provides the definitions for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2019 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 /*******************************************************************************
29 * Global Variables
30 *******************************************************************************/
31
32 /* This is set in Cy_PDL_Init() to the device information relevant
33 * for the current target.
34 */
35 const cy_stc_device_t * cy_device;
36
37 /* Platform and peripheral block configuration */
38 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 =
39 {
40 /* Base HW addresses */
41 /* cpussBase */ 0x40210000UL,
42 /* flashcBase */ 0x40250000UL,
43 /* periBase */ 0x40010000UL,
44 /* udbBase */ 0x40340000UL,
45 /* protBase */ 0x40240000UL,
46 /* hsiomBase */ 0x40310000UL,
47 /* gpioBase */ 0x40320000UL,
48 /* passBase */ 0x411F0000UL,
49 /* ipcBase */ 0x40230000UL,
50 /* cryptoBase */ 0x40110000UL,
51 /* sar0Base */ 0x411D0000UL,
52
53 /* IP block versions [7:4] major, [3:0] minor */
54 /* cpussVersion */ 0x10U,
55 /* cryptoVersion */ 0x10U,
56 /* dwVersion */ 0x10U,
57 /* ipcVersion */ 0x10U,
58 /* periVersion */ 0x10U,
59 /* srssVersion */ 0x10U,
60 /* passVersion */ 0x10U,
61
62 /* Parameters */
63 /* cpussIpcNr */ 16U,
64 /* cpussIpcIrqNr */ 16U,
65 /* cpussDw0ChNr */ 16U,
66 /* cpussDw1ChNr */ 16U,
67 /* cpussFlashPaSize */ 128U,
68 /* cpussIpc0Irq */ 25,
69 /* cpussFmIrq */ 85,
70 /* cpussNotConnectedIrq */ 240,
71 /* srssNumClkpath */ 5U,
72 /* srssNumPll */ 1U,
73 /* srssNumHfroot */ 5U,
74 /* srssIsPiloPresent */ 1U,
75 /* periClockNr */ 59U,
76 /* smifDeviceNr */ 4U,
77 /* passSarChannels */ 16U,
78 /* epMonitorNr */ 28u,
79 /* udbPresent */ 1U,
80 /* sysPmSimoPresent */ 1U,
81 /* protBusMasterMask */ 0xC00FUL,
82 /* cryptoMemSize */ 1024u,
83 /* flashRwwRequired */ 1U,
84 /* flashPipeRequired */ 1U,
85 /* flashWriteDelay */ 1U,
86 /* flashProgramDelay */ 1U,
87 /* flashEraseDelay */ 1U,
88 /* flashCtlMainWs0Freq */ 29U,
89 /* flashCtlMainWs1Freq */ 58U,
90 /* flashCtlMainWs2Freq */ 87U,
91 /* flashCtlMainWs3Freq */ 120U,
92 /* flashCtlMainWs4Freq */ 150U,
93 /* tcpwmCC1Present */ 0U,
94 /* tcpwmAMCPresent */ 0U,
95 /* tcpwmSMCPrecent */ 0U,
96
97 /* Peripheral register offsets */
98
99 /* DW registers */
100 /* dwChOffset */ (uint16_t)offsetof(DW_V1_Type, CH_STRUCT),
101 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V1_Type),
102 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PRIO_Pos,
103 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos,
104 /* dwStatusChIdxPos */ (uint8_t)DW_STATUS_CH_IDX_Pos,
105 /* dwStatusChIdxMsk */ DW_STATUS_CH_IDX_Msk,
106
107 /* PERI registers */
108 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_CMD),
109 /* periTrCmdGrSelMsk */ (uint16_t)PERI_TR_CMD_GROUP_SEL_Msk,
110 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_GR),
111 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V1_Type),
112
113 /* periDivCmdDivSelMsk */ (uint8_t)PERI_DIV_CMD_DIV_SEL_Msk,
114 /* periDivCmdTypeSelPos */ (uint8_t)PERI_DIV_CMD_TYPE_SEL_Pos,
115 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_DIV_CMD_PA_DIV_SEL_Pos,
116 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_DIV_CMD_PA_TYPE_SEL_Pos,
117
118 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_8_CTL),
119 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_CTL),
120 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_5_CTL),
121 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_24_5_CTL),
122
123 /* GPIO registers */
124 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, INTR_CFG),
125 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG),
126 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_IN),
127 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_OUT),
128 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_SIO),
129
130 /* CPUSS registers */
131 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM0_CLOCK_CTL),
132 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM4_CLOCK_CTL),
133 /* cpussCm4StatusOffset */ offsetof(CPUSS_V1_Type, CM4_STATUS),
134 /* cpussCm0StatusOffset */ offsetof(CPUSS_V1_Type, CM0_STATUS),
135 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V1_Type, CM4_PWR_CTL),
136 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_RAM_CTL),
137 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_ROM_CTL),
138 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V1_Type, SYSTICK_CTL),
139
140 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM0_NMI_CTL),
141 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM4_NMI_CTL),
142 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V1_Type, ROM_CTL),
143 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM0_CTL0),
144 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_CTL0),
145 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_CTL0),
146 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM0_PWR_MACRO_CTL),
147 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_PWR_CTL),
148 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_PWR_CTL),
149
150 /* IPC registers */
151 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V1_Type),
152 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V1_Type, LOCK_STATUS),
153 };
154
155 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 =
156 {
157 /* Base HW addresses */
158 /* cpussBase */ 0x40200000UL,
159 /* flashcBase */ 0x40240000UL,
160 /* periBase */ 0x40000000UL,
161 /* udbBase */ 0UL,
162 /* protBase */ 0x40230000UL,
163 /* hsiomBase */ 0x40300000UL,
164 /* gpioBase */ 0x40310000UL,
165 /* passBase */ 0x409F0000UL,
166 /* ipcBase */ 0x40220000UL,
167 /* cryptoBase */ 0x40100000UL,
168 /* sar0Base */ 0x409D0000UL,
169
170 /* IP block versions [7:4] major, [3:0] minor */
171 /* cpussVersion */ 0x20U,
172 /* cryptoVersion */ 0x20U,
173 /* dwVersion */ 0x20U,
174 /* ipcVersion */ 0x20U,
175 /* periVersion */ 0x20U,
176 /* srssVersion */ 0x10U,
177 /* passVersion */ 0x10U,
178
179 /* Parameters */
180 /* cpussIpcNr */ 16U,
181 /* cpussIpcIrqNr */ 16U,
182 /* cpussDw0ChNr */ 29U,
183 /* cpussDw1ChNr */ 29U,
184 /* cpussFlashPaSize */ 128U,
185 /* cpussIpc0Irq */ 23,
186 /* cpussFmIrq */ 117,
187 /* cpussNotConnectedIrq */ 1023,
188 /* srssNumClkpath */ 6U,
189 /* srssNumPll */ 2U,
190 /* srssNumHfroot */ 6U,
191 /* srssIsPiloPresent */ 0U,
192 /* periClockNr */ 54U,
193 /* smifDeviceNr */ 4U,
194 /* passSarChannels */ 16U,
195 /* epMonitorNr */ 32u,
196 /* udbPresent */ 0U,
197 /* sysPmSimoPresent */ 0U,
198 /* protBusMasterMask */ 0xC07FUL,
199 /* cryptoMemSize */ 1024u,
200 /* flashRwwRequired */ 0U,
201 /* flashPipeRequired */ 0U,
202 /* flashWriteDelay */ 0U,
203 /* flashProgramDelay */ 0U,
204 /* flashEraseDelay */ 0U,
205 /* flashCtlMainWs0Freq */ 25U,
206 /* flashCtlMainWs1Freq */ 50U,
207 /* flashCtlMainWs2Freq */ 75U,
208 /* flashCtlMainWs3Freq */ 100U,
209 /* flashCtlMainWs4Freq */ 125U,
210 /* tcpwmCC1Present */ 0U,
211 /* tcpwmAMCPresent */ 0U,
212 /* tcpwmSMCPrecent */ 0U,
213
214 /* Peripheral register offsets */
215
216 /* DW registers */
217 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
218 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
219 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
220 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
221 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
222 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
223
224 /* PERI registers */
225 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
226 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
227 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
228 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
229
230 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
231 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
232 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
233 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
234
235 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
236 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
237 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
238 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
239
240 /* GPIO registers */
241 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
242 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
243 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
244 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
245 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
246
247 /* CPUSS registers */
248 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
249 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
250 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
251 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
252 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
253 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
254 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
255 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
256 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
257 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
258 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
259 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
260 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
261 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
262 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
263 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
264 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
265
266 /* IPC registers */
267 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
268 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
269 };
270
271 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 =
272 {
273 /* Base HW addresses */
274 /* cpussBase */ 0x40200000UL,
275 /* flashcBase */ 0x40240000UL,
276 /* periBase */ 0x40000000UL,
277 /* udbBase */ 0UL,
278 /* protBase */ 0x40230000UL,
279 /* hsiomBase */ 0x40300000UL,
280 /* gpioBase */ 0x40310000UL,
281 /* passBase */ 0x409F0000UL,
282 /* ipcBase */ 0x40220000UL,
283 /* cryptoBase */ 0x40100000UL,
284 /* sar0Base */ 0x409D0000UL,
285
286 /* IP block versions [7:4] major, [3:0] minor */
287 /* cpussVersion */ 0x20U,
288 /* cryptoVersion */ 0x20U,
289 /* dwVersion */ 0x20U,
290 /* ipcVersion */ 0x20U,
291 /* periVersion */ 0x20U,
292 /* srssVersion */ 0x13U,
293 /* passVersion */ 0x10U,
294
295 /* Parameters */
296 /* cpussIpcNr */ 16U,
297 /* cpussIpcIrqNr */ 16U,
298 /* cpussDw0ChNr */ 29U,
299 /* cpussDw1ChNr */ 32U,
300 /* cpussFlashPaSize */ 128U,
301 /* cpussIpc0Irq */ 23,
302 /* cpussFmIrq */ 117,
303 /* cpussNotConnectedIrq */ 1023,
304 /* srssNumClkpath */ 5U,
305 /* srssNumPll */ 1U,
306 /* srssNumHfroot */ 5U,
307 /* srssIsPiloPresent */ 0U,
308 /* periClockNr */ 28U,
309 /* smifDeviceNr */ 3U,
310 /* passSarChannels */ 16U,
311 /* epMonitorNr */ 0u,
312 /* udbPresent */ 0U,
313 /* sysPmSimoPresent */ 0U,
314 /* protBusMasterMask */ 0xC03FUL,
315 /* cryptoMemSize */ 1024u,
316 /* flashRwwRequired */ 0U,
317 /* flashPipeRequired */ 0U,
318 /* flashWriteDelay */ 0U,
319 /* flashProgramDelay */ 0U,
320 /* flashEraseDelay */ 0U,
321 /* flashCtlMainWs0Freq */ 25U,
322 /* flashCtlMainWs1Freq */ 50U,
323 /* flashCtlMainWs2Freq */ 75U,
324 /* flashCtlMainWs3Freq */ 100U,
325 /* flashCtlMainWs4Freq */ 125U,
326 /* tcpwmCC1Present */ 0U,
327 /* tcpwmAMCPresent */ 0U,
328 /* tcpwmSMCPrecent */ 0U,
329
330 /* Peripheral register offsets */
331
332 /* DW registers */
333 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
334 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
335 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
336 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
337 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
338 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
339
340 /* PERI registers */
341 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
342 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
343 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
344 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
345
346 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
347 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
348 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
349 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
350
351 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
352 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
353 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
354 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
355
356 /* GPIO registers */
357 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
358 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
359 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
360 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
361 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
362
363 /* CPUSS registers */
364 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
365 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
366 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
367 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
368 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
369 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
370 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
371 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
372 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
373 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
374 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
375 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
376 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
377 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
378 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
379 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
380 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
381
382 /* IPC registers */
383 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
384 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
385 };
386
387 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 =
388 {
389 /* Base HW addresses */
390 /* cpussBase */ 0x40200000UL,
391 /* flashcBase */ 0x40240000UL,
392 /* periBase */ 0x40000000UL,
393 /* udbBase */ 0UL,
394 /* protBase */ 0x40230000UL,
395 /* hsiomBase */ 0x40300000UL,
396 /* gpioBase */ 0x40310000UL,
397 /* passBase */ 0x409F0000UL,
398 /* ipcBase */ 0x40220000UL,
399 /* cryptoBase */ 0x40100000UL,
400 /* sar0Base */ 0x409B0000UL,
401
402 /* IP block versions [7:4] major, [3:0] minor */
403 /* cpussVersion */ 0x20U,
404 /* cryptoVersion */ 0x20U,
405 /* dwVersion */ 0x20U,
406 /* ipcVersion */ 0x20U,
407 /* periVersion */ 0x20U,
408 /* srssVersion */ 0x13U,
409 /* passVersion */ 0x20U,
410
411 /* Parameters */
412 /* cpussIpcNr */ 16U,
413 /* cpussIpcIrqNr */ 16U,
414 /* cpussDw0ChNr */ 30U,
415 /* cpussDw1ChNr */ 32U,
416 /* cpussFlashPaSize */ 128U,
417 /* cpussIpc0Irq */ 23,
418 /* cpussFmIrq */ 117,
419 /* cpussNotConnectedIrq */ 1023,
420 /* srssNumClkpath */ 5U,
421 /* srssNumPll */ 1U,
422 /* srssNumHfroot */ 4U,
423 /* srssIsPiloPresent */ 0U,
424 /* periClockNr */ 28U,
425 /* smifDeviceNr */ 3U,
426 /* passSarChannels */ 16U,
427 /* epMonitorNr */ 0u,
428 /* udbPresent */ 0U,
429 /* sysPmSimoPresent */ 0U,
430 /* protBusMasterMask */ 0xC01FUL,
431 /* cryptoMemSize */ 1024u,
432 /* flashRwwRequired */ 0U,
433 /* flashPipeRequired */ 0U,
434 /* flashWriteDelay */ 0U,
435 /* flashProgramDelay */ 0U,
436 /* flashEraseDelay */ 0U,
437 /* flashCtlMainWs0Freq */ 25U,
438 /* flashCtlMainWs1Freq */ 50U,
439 /* flashCtlMainWs2Freq */ 75U,
440 /* flashCtlMainWs3Freq */ 100U,
441 /* flashCtlMainWs4Freq */ 125U,
442 /* tcpwmCC1Present */ 0x02U,
443 /* tcpwmAMCPresent */ 0x02U,
444 /* tcpwmSMCPrecent */ 0x00U,
445
446 /* Peripheral register offsets */
447
448 /* DW registers */
449 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
450 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
451 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
452 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
453 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
454 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
455
456 /* PERI registers */
457 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
458 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
459 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
460 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
461
462 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
463 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
464 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
465 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
466
467 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
468 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
469 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
470 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
471
472 /* GPIO registers */
473 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
474 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
475 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
476 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
477 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
478
479 /* CPUSS registers */
480 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
481 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
482 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
483 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
484 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
485 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
486 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
487 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
488 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
489 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
490 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
491 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
492 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
493 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
494 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
495 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
496 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
497
498 /* IPC registers */
499 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
500 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
501 };
502
503
504 /******************************************************************************
505 * Function Name: Cy_PDL_Init
506 ****************************************************************************//**
507 *
508 * \brief Initializes the platform and peripheral block configuration for the
509 * given target device.
510 *
511 * \param device
512 * Pointer to the platform and peripheral block configuration
513 *
514 * \note
515 * This function must be called prior calling any function in PDL.
516 *
517 *******************************************************************************/
Cy_PDL_Init(const cy_stc_device_t * device)518 void Cy_PDL_Init(const cy_stc_device_t * device)
519 {
520 cy_device = device;
521 }
522
523
524 /* [] END OF FILE */
525
