1 /***************************************************************************//**
2 * \file cy_device.c
3 * \version 2.30
4 *
5 * This file provides the definitions for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2019 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 /*******************************************************************************
29 * Global Variables
30 *******************************************************************************/
31
32 /* This is set in Cy_PDL_Init() to the device information relevant
33 * for the current target.
34 */
35 const cy_stc_device_t * cy_device;
36
37 /* Platform and peripheral block configuration */
38
39 /* The header strategy used with TVIIBE does not bring in some legacy defines required
40 * for PSoC6_01 - ignore defining this device family when compiling for TVIIBE. */
41 #if !(defined(CY_DEVICE_TVIIBE))
42 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01 =
43 {
44 /* Base HW addresses */
45 /* cpussBase */ 0x40210000UL,
46 /* flashcBase */ 0x40250000UL,
47 /* periBase */ 0x40010000UL,
48 /* udbBase */ 0x40340000UL,
49 /* protBase */ 0x40240000UL,
50 /* hsiomBase */ 0x40310000UL,
51 /* gpioBase */ 0x40320000UL,
52 /* passBase */ 0x411F0000UL,
53 /* ipcBase */ 0x40230000UL,
54 /* cryptoBase */ 0x40110000UL,
55 /* sar0Base */ 0x411D0000UL,
56
57 /* IP block versions [7:4] major, [3:0] minor */
58 /* cpussVersion */ 0x10U,
59 /* cryptoVersion */ 0x10U,
60 /* dwVersion */ 0x10U,
61 /* flashcVersion */ 0x10U,
62 /* gpioVersion */ 0x10U,
63 /* hsiomVersion */ 0x10U,
64 /* ipcVersion */ 0x10U,
65 /* periVersion */ 0x10U,
66 /* protVersion */ 0x10U,
67 /* srssVersion */ 0x10U,
68 /* passVersion */ 0x10U,
69
70 /* Parameters */
71 /* cpussIpcNr */ 16U,
72 /* cpussIpcIrqNr */ 16U,
73 /* cpussDw0ChNr */ 16U,
74 /* cpussDw1ChNr */ 16U,
75 /* cpussFlashPaSize */ 128U,
76 /* cpussIpc0Irq */ 25,
77 /* cpussFmIrq */ 85,
78 /* cpussNotConnectedIrq */ 240,
79 /* srssNumClkpath */ 5U,
80 /* srssNumPll */ 1U,
81 /* srssNumHfroot */ 5U,
82 /* srssIsPiloPresent */ 1U,
83 /* periClockNr */ 59U,
84 /* smifDeviceNr */ 4U,
85 /* passSarChannels */ 16U,
86 /* epMonitorNr */ 28u,
87 /* udbPresent */ 1U,
88 /* sysPmSimoPresent */ 1U,
89 /* protBusMasterMask */ 0xC00FUL,
90 /* cryptoMemSize */ 1024u,
91 /* flashRwwRequired */ 1U,
92 /* flashPipeRequired */ 1U,
93 /* flashWriteDelay */ 1U,
94 /* flashProgramDelay */ 1U,
95 /* flashEraseDelay */ 1U,
96 /* flashCtlMainWs0Freq */ 29U,
97 /* flashCtlMainWs1Freq */ 58U,
98 /* flashCtlMainWs2Freq */ 87U,
99 /* flashCtlMainWs3Freq */ 120U,
100 /* flashCtlMainWs4Freq */ 150U,
101 /* tcpwmCC1Present */ 0U,
102 /* tcpwmAMCPresent */ 0U,
103 /* tcpwmSMCPrecent */ 0U,
104
105 /* Peripheral register offsets */
106
107 /* DW registers */
108 /* dwChOffset */ (uint16_t)offsetof(DW_V1_Type, CH_STRUCT),
109 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V1_Type),
110 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PRIO_Pos,
111 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos,
112 /* dwStatusChIdxPos */ (uint8_t)DW_STATUS_CH_IDX_Pos,
113 /* dwStatusChIdxMsk */ DW_STATUS_CH_IDX_Msk,
114
115 /* PERI registers */
116 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_CMD),
117 /* periTrCmdGrSelMsk */ (uint16_t)PERI_TR_CMD_GROUP_SEL_Msk,
118 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V1_Type, TR_GR),
119 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V1_Type),
120
121 /* periDivCmdDivSelMsk */ (uint8_t)PERI_DIV_CMD_DIV_SEL_Msk,
122 /* periDivCmdTypeSelPos */ (uint8_t)PERI_DIV_CMD_TYPE_SEL_Pos,
123 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_DIV_CMD_PA_DIV_SEL_Pos,
124 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_DIV_CMD_PA_TYPE_SEL_Pos,
125
126 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_8_CTL),
127 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_CTL),
128 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_16_5_CTL),
129 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V1_Type, DIV_24_5_CTL),
130
131 /* GPIO registers */
132 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, INTR_CFG),
133 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG),
134 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_IN),
135 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_OUT),
136 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V1_Type, CFG_SIO),
137
138 /* CPUSS registers */
139 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM0_CLOCK_CTL),
140 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V1_Type, CM4_CLOCK_CTL),
141 /* cpussCm4StatusOffset */ offsetof(CPUSS_V1_Type, CM4_STATUS),
142 /* cpussCm0StatusOffset */ offsetof(CPUSS_V1_Type, CM0_STATUS),
143 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V1_Type, CM4_PWR_CTL),
144 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_RAM_CTL),
145 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V1_Type, TRIM_ROM_CTL),
146 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V1_Type, SYSTICK_CTL),
147
148 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM0_NMI_CTL),
149 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V1_Type, CM4_NMI_CTL),
150 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V1_Type, ROM_CTL),
151 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM0_CTL0),
152 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_CTL0),
153 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_CTL0),
154 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM0_PWR_MACRO_CTL),
155 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_PWR_CTL),
156 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_PWR_CTL),
157
158 /* IPC registers */
159 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V1_Type),
160 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V1_Type, LOCK_STATUS),
161 };
162 #endif
163
164 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02 =
165 {
166 /* Base HW addresses */
167 /* cpussBase */ 0x40200000UL,
168 /* flashcBase */ 0x40240000UL,
169 /* periBase */ 0x40000000UL,
170 /* udbBase */ 0UL,
171 /* protBase */ 0x40230000UL,
172 /* hsiomBase */ 0x40300000UL,
173 /* gpioBase */ 0x40310000UL,
174 /* passBase */ 0x409F0000UL,
175 /* ipcBase */ 0x40220000UL,
176 /* cryptoBase */ 0x40100000UL,
177 /* sar0Base */ 0x409D0000UL,
178
179 /* IP block versions [7:4] major, [3:0] minor */
180 /* cpussVersion */ 0x20U,
181 /* cryptoVersion */ 0x20U,
182 /* dwVersion */ 0x20U,
183 /* flashcVersion */ 0x20U,
184 /* gpioVersion */ 0x20U,
185 /* hsiomVersion */ 0x20U,
186 /* ipcVersion */ 0x20U,
187 /* periVersion */ 0x20U,
188 /* protVersion */ 0x20U,
189 /* srssVersion */ 0x10U,
190 /* passVersion */ 0x10U,
191
192 /* Parameters */
193 /* cpussIpcNr */ 16U,
194 /* cpussIpcIrqNr */ 16U,
195 /* cpussDw0ChNr */ 29U,
196 /* cpussDw1ChNr */ 29U,
197 /* cpussFlashPaSize */ 128U,
198 /* cpussIpc0Irq */ 23,
199 /* cpussFmIrq */ 117,
200 /* cpussNotConnectedIrq */ 1023,
201 /* srssNumClkpath */ 6U,
202 /* srssNumPll */ 2U,
203 /* srssNumHfroot */ 6U,
204 /* srssIsPiloPresent */ 0U,
205 /* periClockNr */ 54U,
206 /* smifDeviceNr */ 4U,
207 /* passSarChannels */ 16U,
208 /* epMonitorNr */ 32u,
209 /* udbPresent */ 0U,
210 /* sysPmSimoPresent */ 0U,
211 /* protBusMasterMask */ 0xC07FUL,
212 /* cryptoMemSize */ 1024u,
213 /* flashRwwRequired */ 0U,
214 /* flashPipeRequired */ 0U,
215 /* flashWriteDelay */ 0U,
216 /* flashProgramDelay */ 0U,
217 /* flashEraseDelay */ 0U,
218 /* flashCtlMainWs0Freq */ 25U,
219 /* flashCtlMainWs1Freq */ 50U,
220 /* flashCtlMainWs2Freq */ 75U,
221 /* flashCtlMainWs3Freq */ 100U,
222 /* flashCtlMainWs4Freq */ 125U,
223 /* tcpwmCC1Present */ 0U,
224 /* tcpwmAMCPresent */ 0U,
225 /* tcpwmSMCPrecent */ 0U,
226
227 /* Peripheral register offsets */
228
229 /* DW registers */
230 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
231 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
232 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
233 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
234 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
235 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
236
237 /* PERI registers */
238 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
239 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
240 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
241 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
242
243 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
244 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
245 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
246 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
247
248 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
249 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
250 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
251 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
252
253 /* GPIO registers */
254 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
255 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
256 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
257 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
258 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
259
260 /* CPUSS registers */
261 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
262 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
263 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
264 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
265 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
266 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
267 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
268 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
269 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
270 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
271 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
272 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
273 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
274 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
275 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
276 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
277 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
278
279 /* IPC registers */
280 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
281 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
282 };
283
284 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 =
285 {
286 /* Base HW addresses */
287 /* cpussBase */ 0x40200000UL,
288 /* flashcBase */ 0x40240000UL,
289 /* periBase */ 0x40000000UL,
290 /* udbBase */ 0UL,
291 /* protBase */ 0x40230000UL,
292 /* hsiomBase */ 0x40300000UL,
293 /* gpioBase */ 0x40310000UL,
294 /* passBase */ 0x409F0000UL,
295 /* ipcBase */ 0x40220000UL,
296 /* cryptoBase */ 0x40100000UL,
297 /* sar0Base */ 0x409D0000UL,
298
299 /* IP block versions [7:4] major, [3:0] minor */
300 /* cpussVersion */ 0x20U,
301 /* cryptoVersion */ 0x20U,
302 /* dwVersion */ 0x20U,
303 /* flashcVersion */ 0x20U,
304 /* gpioVersion */ 0x20U,
305 /* hsiomVersion */ 0x20U,
306 /* ipcVersion */ 0x20U,
307 /* periVersion */ 0x20U,
308 /* protVersion */ 0x20U,
309 /* srssVersion */ 0x13U,
310 /* passVersion */ 0x10U,
311
312 /* Parameters */
313 /* cpussIpcNr */ 16U,
314 /* cpussIpcIrqNr */ 16U,
315 /* cpussDw0ChNr */ 29U,
316 /* cpussDw1ChNr */ 32U,
317 /* cpussFlashPaSize */ 128U,
318 /* cpussIpc0Irq */ 23,
319 /* cpussFmIrq */ 117,
320 /* cpussNotConnectedIrq */ 1023,
321 /* srssNumClkpath */ 5U,
322 /* srssNumPll */ 1U,
323 /* srssNumHfroot */ 5U,
324 /* srssIsPiloPresent */ 0U,
325 /* periClockNr */ 28U,
326 /* smifDeviceNr */ 3U,
327 /* passSarChannels */ 16U,
328 /* epMonitorNr */ 0u,
329 /* udbPresent */ 0U,
330 /* sysPmSimoPresent */ 0U,
331 /* protBusMasterMask */ 0xC03FUL,
332 /* cryptoMemSize */ 1024u,
333 /* flashRwwRequired */ 0U,
334 /* flashPipeRequired */ 0U,
335 /* flashWriteDelay */ 0U,
336 /* flashProgramDelay */ 0U,
337 /* flashEraseDelay */ 0U,
338 /* flashCtlMainWs0Freq */ 25U,
339 /* flashCtlMainWs1Freq */ 50U,
340 /* flashCtlMainWs2Freq */ 75U,
341 /* flashCtlMainWs3Freq */ 100U,
342 /* flashCtlMainWs4Freq */ 125U,
343 /* tcpwmCC1Present */ 0U,
344 /* tcpwmAMCPresent */ 0U,
345 /* tcpwmSMCPrecent */ 0U,
346
347 /* Peripheral register offsets */
348
349 /* DW registers */
350 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
351 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
352 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
353 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
354 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
355 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
356
357 /* PERI registers */
358 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
359 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
360 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
361 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
362
363 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
364 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
365 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
366 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
367
368 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
369 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
370 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
371 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
372
373 /* GPIO registers */
374 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
375 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
376 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
377 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
378 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
379
380 /* CPUSS registers */
381 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
382 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
383 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
384 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
385 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
386 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
387 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
388 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
389 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
390 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
391 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
392 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
393 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
394 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
395 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
396 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
397 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
398
399 /* IPC registers */
400 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
401 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
402 };
403
404 const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 =
405 {
406 /* Base HW addresses */
407 /* cpussBase */ 0x40200000UL,
408 /* flashcBase */ 0x40240000UL,
409 /* periBase */ 0x40000000UL,
410 /* udbBase */ 0UL,
411 /* protBase */ 0x40230000UL,
412 /* hsiomBase */ 0x40300000UL,
413 /* gpioBase */ 0x40310000UL,
414 /* passBase */ 0x409F0000UL,
415 /* ipcBase */ 0x40220000UL,
416 /* cryptoBase */ 0x40100000UL,
417 /* sar0Base */ 0x409B0000UL,
418
419 /* IP block versions [7:4] major, [3:0] minor */
420 /* cpussVersion */ 0x20U,
421 /* cryptoVersion */ 0x20U,
422 /* dwVersion */ 0x20U,
423 /* flashcVersion */ 0x20U,
424 /* gpioVersion */ 0x20U,
425 /* hsiomVersion */ 0x20U,
426 /* ipcVersion */ 0x20U,
427 /* periVersion */ 0x20U,
428 /* protVersion */ 0x20U,
429 /* srssVersion */ 0x13U,
430 /* passVersion */ 0x20U,
431
432 /* Parameters */
433 /* cpussIpcNr */ 16U,
434 /* cpussIpcIrqNr */ 16U,
435 /* cpussDw0ChNr */ 30U,
436 /* cpussDw1ChNr */ 32U,
437 /* cpussFlashPaSize */ 128U,
438 /* cpussIpc0Irq */ 23,
439 /* cpussFmIrq */ 117,
440 /* cpussNotConnectedIrq */ 1023,
441 /* srssNumClkpath */ 5U,
442 /* srssNumPll */ 1U,
443 /* srssNumHfroot */ 4U,
444 /* srssIsPiloPresent */ 0U,
445 /* periClockNr */ 28U,
446 /* smifDeviceNr */ 3U,
447 /* passSarChannels */ 16U,
448 /* epMonitorNr */ 0u,
449 /* udbPresent */ 0U,
450 /* sysPmSimoPresent */ 0U,
451 /* protBusMasterMask */ 0xC01FUL,
452 /* cryptoMemSize */ 1024u,
453 /* flashRwwRequired */ 0U,
454 /* flashPipeRequired */ 0U,
455 /* flashWriteDelay */ 0U,
456 /* flashProgramDelay */ 0U,
457 /* flashEraseDelay */ 0U,
458 /* flashCtlMainWs0Freq */ 25U,
459 /* flashCtlMainWs1Freq */ 50U,
460 /* flashCtlMainWs2Freq */ 75U,
461 /* flashCtlMainWs3Freq */ 100U,
462 /* flashCtlMainWs4Freq */ 125U,
463 /* tcpwmCC1Present */ 0x02U,
464 /* tcpwmAMCPresent */ 0x02U,
465 /* tcpwmSMCPrecent */ 0x00U,
466
467 /* Peripheral register offsets */
468
469 /* DW registers */
470 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
471 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
472 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
473 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
474 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
475 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
476
477 /* PERI registers */
478 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
479 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
480 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
481 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
482
483 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
484 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
485 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
486 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
487
488 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
489 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
490 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
491 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
492
493 /* GPIO registers */
494 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
495 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
496 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
497 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
498 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
499
500 /* CPUSS registers */
501 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
502 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
503 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
504 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
505 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
506 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
507 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
508 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
509 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
510 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
511 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
512 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
513 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
514 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
515 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
516 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
517 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
518
519 /* IPC registers */
520 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
521 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
522 };
523
524 const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE4M =
525 {
526 /* Base HW addresses */
527 /* cpussBase */ 0x40200000UL,
528 /* flashcBase */ 0x40240000UL,
529 /* periBase */ 0x40000000UL,
530 /* udbBase */ 0UL,
531 /* protBase */ 0x40230000UL,
532 /* hsiomBase */ 0x40300000UL,
533 /* gpioBase */ 0x40310000UL,
534 /* passBase */ 0x40900000UL,
535 /* ipcBase */ 0x40220000UL,
536 /* cryptoBase */ 0x40100000UL,
537 /* sar0Base */ 0x40900000UL,
538
539 /* IP block versions [7:4] major, [3:0] minor */
540 /* cpussVersion */ 0x20U,
541 /* cryptoVersion */ 0x20U,
542 /* dwVersion */ 0x20U,
543 /* flashcVersion */ 0x20U,
544 /* gpioVersion */ 0x20U,
545 /* hsiomVersion */ 0x20U,
546 /* ipcVersion */ 0x20U,
547 /* periVersion */ 0x20U,
548 /* protVersion */ 0x20U,
549 /* srssVersion */ 0x30U,
550 /* passVersion */ 0x20U,
551
552 /* Parameters */
553 /* cpussIpcNr */ 8U,
554 /* cpussIpcIrqNr */ 8U,
555 /* cpussDw0ChNr */ 92U,
556 /* cpussDw1ChNr */ 44U,
557 /* cpussFlashPaSize */ 128U,
558 /* cpussIpc0Irq */ 0,
559 /* cpussFmIrq */ 46,
560 /* cpussNotConnectedIrq */ 1023,
561 /* srssNumClkpath */ 4U,
562 /* srssNumPll */ 1U,
563 /* srssNumHfroot */ 3U,
564 /* srssIsPiloPresent */ 0U,
565 /* periClockNr */ 124U,
566 /* smifDeviceNr */ 0U,
567 /* passSarChannels */ 64U,
568 /* epMonitorNr */ 0u,
569 /* udbPresent */ 0U,
570 /* sysPmSimoPresent */ 0U,
571 /* protBusMasterMask */ 0xFE7FUL,
572 /* cryptoMemSize */ 1024u,
573 /* flashRwwRequired */ 0U,
574 /* flashPipeRequired */ 0U,
575 /* flashWriteDelay */ 0U,
576 /* flashProgramDelay */ 0U,
577 /* flashEraseDelay */ 0U,
578 /* flashCtlMainWs0Freq */ 25U,
579 /* flashCtlMainWs1Freq */ 50U,
580 /* flashCtlMainWs2Freq */ 75U,
581 /* flashCtlMainWs3Freq */ 100U,
582 /* flashCtlMainWs4Freq */ 125U,
583
584 /* tcpwmCC1Present */ 0x07U,
585 /* tcpwmAMCPresent */ 0x02U,
586 /* tcpwmSMCPrecent */ 0x02U,
587
588 /* Peripheral register offsets */
589
590 /* DW registers */
591 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
592 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
593 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
594 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
595 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
596 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
597
598 /* PERI registers */
599 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
600 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
601 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
602 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
603
604 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
605 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
606 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
607 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
608
609 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
610 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
611 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
612 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
613
614 /* GPIO registers */
615 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
616 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
617 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
618 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
619 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
620
621 /* CPUSS registers */
622 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
623 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
624 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
625 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
626 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
627 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
628 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
629 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
630 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
631 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
632 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
633 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
634 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
635 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
636 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
637 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
638 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
639
640 /* IPC registers */
641 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
642 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
643 };
644
645 const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE2M =
646 {
647 /* Base HW addresses */
648 /* cpussBase */ 0x40200000UL,
649 /* flashcBase */ 0x40240000UL,
650 /* periBase */ 0x40000000UL,
651 /* udbBase */ 0UL,
652 /* protBase */ 0x40230000UL,
653 /* hsiomBase */ 0x40300000UL,
654 /* gpioBase */ 0x40310000UL,
655 /* passBase */ 0x40900000UL,
656 /* ipcBase */ 0x40220000UL,
657 /* cryptoBase */ 0x40100000UL,
658 /* sar0Base */ 0x40900000UL,
659
660 /* IP block versions [7:4] major, [3:0] minor */
661 /* cpussVersion */ 0x20U,
662 /* cryptoVersion */ 0x20U,
663 /* dwVersion */ 0x20U,
664 /* flashcVersion */ 0x20U,
665 /* gpioVersion */ 0x20U,
666 /* hsiomVersion */ 0x20U,
667 /* ipcVersion */ 0x20U,
668 /* periVersion */ 0x20U,
669 /* protVersion */ 0x20U,
670 /* srssVersion */ 0x20U,
671 /* passVersion */ 0x20U,
672
673 /* Parameters */
674 /* cpussIpcNr */ 8U,
675 /* cpussIpcIrqNr */ 8U,
676 /* cpussDw0ChNr */ 92U,
677 /* cpussDw1ChNr */ 44U,
678 /* cpussFlashPaSize */ 128U,
679 /* cpussIpc0Irq */ 0,
680 /* cpussFmIrq */ 46,
681 /* cpussNotConnectedIrq */ 1023,
682 /* srssNumClkpath */ 4U,
683 /* srssNumPll */ 1U,
684 /* srssNumHfroot */ 3U,
685 /* srssIsPiloPresent */ 0U,
686 /* periClockNr */ 124U,
687 /* smifDeviceNr */ 0U,
688 /* passSarChannels */ 64U,
689 /* epMonitorNr */ 0u,
690 /* udbPresent */ 0U,
691 /* sysPmSimoPresent */ 0U,
692 /* protBusMasterMask */ 0xFE7FUL,
693 /* cryptoMemSize */ 1024u,
694 /* flashRwwRequired */ 0U,
695 /* flashPipeRequired */ 0U,
696 /* flashWriteDelay */ 0U,
697 /* flashProgramDelay */ 0U,
698 /* flashEraseDelay */ 0U,
699 /* flashCtlMainWs0Freq */ 25U,
700 /* flashCtlMainWs1Freq */ 50U,
701 /* flashCtlMainWs2Freq */ 75U,
702 /* flashCtlMainWs3Freq */ 100U,
703 /* flashCtlMainWs4Freq */ 125U,
704
705 /* tcpwmCC1Present */ 0x07U,
706 /* tcpwmAMCPresent */ 0x02U,
707 /* tcpwmSMCPrecent */ 0x02U,
708
709 /* Peripheral register offsets */
710
711 /* DW registers */
712 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
713 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
714 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
715 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
716 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
717 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
718
719 /* PERI registers */
720 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
721 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
722 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
723 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
724
725 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
726 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
727 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
728 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
729
730 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
731 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
732 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
733 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
734
735 /* GPIO registers */
736 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
737 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
738 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
739 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
740 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
741
742 /* CPUSS registers */
743 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
744 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
745 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
746 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
747 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
748 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
749 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
750 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
751 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
752 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
753 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
754 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
755 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
756 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
757 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
758 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
759 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
760
761 /* IPC registers */
762 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
763 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
764 };
765
766 const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE1M =
767 {
768 /* Base HW addresses */
769 /* cpussBase */ 0x40200000UL,
770 /* flashcBase */ 0x40240000UL,
771 /* periBase */ 0x40000000UL,
772 /* udbBase */ 0UL,
773 /* protBase */ 0x40230000UL,
774 /* hsiomBase */ 0x40300000UL,
775 /* gpioBase */ 0x40310000UL,
776 /* passBase */ 0x40900000UL,
777 /* ipcBase */ 0x40220000UL,
778 /* cryptoBase */ 0x40100000UL,
779 /* sar0Base */ 0x40900000UL,
780
781 /* IP block versions [7:4] major, [3:0] minor */
782 /* cpussVersion */ 0x20U,
783 /* cryptoVersion */ 0x20U,
784 /* dwVersion */ 0x20U,
785 /* flashcVersion */ 0x20U,
786 /* gpioVersion */ 0x20U,
787 /* hsiomVersion */ 0x20U,
788 /* ipcVersion */ 0x20U,
789 /* periVersion */ 0x20U,
790 /* protVersion */ 0x20U,
791 /* srssVersion */ 0x20U,
792 /* passVersion */ 0x20U,
793
794 /* Parameters */
795 /* cpussIpcNr */ 8U,
796 /* cpussIpcIrqNr */ 8U,
797 #if !defined (CY_DEVICE_SERIES_CYT2B6)
798 /* cpussDw0ChNr */ 89U,
799 /* cpussDw1ChNr */ 33U,
800 #else
801 /* Traveo II BE 512K devices have fewer datawire channels than the 1M devices. */
802 /* cpussDw0ChNr */ 54U,
803 /* cpussDw1ChNr */ 26U,
804 #endif
805 /* cpussFlashPaSize */ 128U,
806 /* cpussIpc0Irq */ 0,
807 /* cpussFmIrq */ 46,
808 /* cpussNotConnectedIrq */ 1023,
809 /* srssNumClkpath */ 4U,
810 /* srssNumPll */ 1U,
811 /* srssNumHfroot */ 3U,
812 /* srssIsPiloPresent */ 0U,
813 /* periClockNr */ 110U,
814 /* smifDeviceNr */ 0U,
815 /* passSarChannels */ 64U,
816 /* epMonitorNr */ 0u,
817 /* udbPresent */ 0U,
818 /* sysPmSimoPresent */ 0U,
819 /* protBusMasterMask */ 0xFE7FUL,
820 /* cryptoMemSize */ 1024u,
821 /* flashRwwRequired */ 0U,
822 /* flashPipeRequired */ 0U,
823 /* flashWriteDelay */ 0U,
824 /* flashProgramDelay */ 0U,
825 /* flashEraseDelay */ 0U,
826 /* flashCtlMainWs0Freq */ 25U,
827 /* flashCtlMainWs1Freq */ 50U,
828 /* flashCtlMainWs2Freq */ 75U,
829 /* flashCtlMainWs3Freq */ 100U,
830 /* flashCtlMainWs4Freq */ 125U,
831
832 /* tcpwmCC1Present */ 0x07U,
833 /* tcpwmAMCPresent */ 0x02U,
834 /* tcpwmSMCPrecent */ 0x02U,
835
836 /* Peripheral register offsets */
837
838 /* DW registers */
839 /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT),
840 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_V2_Type),
841 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
842 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
843 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
844 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
845
846 /* PERI registers */
847 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD),
848 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
849 /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR),
850 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_V2_Type),
851
852 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
853 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
854 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
855 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
856
857 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL),
858 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL),
859 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL),
860 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL),
861
862 /* GPIO registers */
863 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG),
864 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG),
865 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN),
866 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT),
867 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO),
868
869 /* CPUSS registers */
870 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL),
871 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL),
872 /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS),
873 /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS),
874 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL),
875 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL),
876 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL),
877 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
878 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL),
879 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL),
880 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL),
881 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0),
882 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
883 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
884 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_PWR_MACRO_CTL),
885 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
886 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
887
888 /* IPC registers */
889 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_V2_Type),
890 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS),
891 };
892
893 const cy_stc_device_t cy_deviceIpBlockCfgFX3G2 =
894 {
895 /* Base HW addresses */
896 /* cpussBase */ 0x40200000UL,
897 /* flashcBase */ 0x40240000UL,
898 /* periBase */ 0x40000000UL,
899 /* udbBase */ 0UL,
900 /* protBase */ 0x40230000UL,
901 /* hsiomBase */ 0x40300000UL,
902 /* gpioBase */ 0x40310000UL,
903 /* passBase */ 0UL,
904 /* ipcBase */ 0x40220000UL,
905 /* cryptoBase */ 0x40100000UL,
906 /* sar0Base */ 0UL,
907
908 /* IP block versions [7:4] major, [3:0] minor */
909 /* cpussVersion */ 0x20U,
910 /* cryptoVersion */ 0x20U,
911 /* dwVersion */ 0x20U,
912 /* flashcVersion */ 0x20U,
913 /* gpioVersion */ 0x50U,
914 /* hsiomVersion */ 0x50U,
915 /* ipcVersion */ 0x20U,
916 /* periVersion */ 0x20U,
917 /* protVersion */ 0x20U,
918 /* srssVersion */ 0x13U,
919 /* passVersion */ 0x00U,
920
921 /* Parameters */
922 /* cpussIpcNr */ 16U,
923 /* cpussIpcIrqNr */ 16U,
924 /* cpussDw0ChNr */ 24U,
925 /* cpussDw1ChNr */ 24U,
926 /* cpussFlashPaSize */ 128U,
927 /* cpussIpc0Irq */ 19,
928 /* cpussFmIrq */ 109,
929 /* cpussNotConnectedIrq */ 1023,
930 /* srssNumClkpath */ 5U,
931 /* srssNumPll */ 2U,
932 /* srssNumHfroot */ 6U,
933 /* srssIsPiloPresent */ 0U,
934 /* periClockNr */ 19U,
935 /* smifDeviceNr */ 3U,
936 /* passSarChannels */ 0U,
937 /* epMonitorNr */ 0U,
938 /* udbPresent */ 0U,
939 /* sysPmSimoPresent */ 0U,
940 /* protBusMasterMask */ 0xC01FUL,
941 /* cryptoMemSize */ 1024u,
942 /* flashRwwRequired */ 0U,
943 /* flashPipeRequired */ 0U,
944 /* flashWriteDelay */ 0U,
945 /* flashProgramDelay */ 0U,
946 /* flashEraseDelay */ 0U,
947 /* flashCtlMainWs0Freq */ 25U,
948 /* flashCtlMainWs1Freq */ 50U,
949 /* flashCtlMainWs2Freq */ 75U,
950 /* flashCtlMainWs3Freq */ 100U,
951 /* flashCtlMainWs4Freq */ 125U,
952 /* tcpwmCC1Present */ 0U,
953 /* tcpwmAMCPresent */ 0U,
954 /* tcpwmSMCPrecent */ 0U,
955
956 /* Peripheral register offsets */
957
958 /* DW registers */
959 /* dwChOffset */ (uint16_t)offsetof(DW_Type, CH_STRUCT),
960 /* dwChSize */ (uint16_t)sizeof(DW_CH_STRUCT_Type),
961 /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos,
962 /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos,
963 /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos,
964 /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk,
965
966 /* PERI registers */
967 /* periTrCmdOffset */ (uint16_t)offsetof(PERI_Type, TR_CMD),
968 /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk,
969 /* periTrGrOffset */ (uint16_t)offsetof(PERI_Type, TR_GR),
970 /* periTrGrSize */ (uint16_t)sizeof(PERI_TR_GR_Type),
971
972 /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk,
973 /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos,
974 /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos,
975 /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos,
976
977 /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_Type, DIV_8_CTL),
978 /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_Type, DIV_16_CTL),
979 /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_Type, DIV_16_5_CTL),
980 /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_Type, DIV_24_5_CTL),
981
982 /* GPIO registers */
983 /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_Type, INTR_CFG),
984 /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_Type, CFG),
985 /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_Type, CFG_IN),
986 /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_Type, CFG_OUT),
987 /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_Type, CFG_SIO),
988
989 /* CPUSS registers */
990 /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_Type, CM0_CLOCK_CTL),
991 /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_Type, CM4_CLOCK_CTL),
992 /* cpussCm4StatusOffset */ offsetof(CPUSS_Type, CM4_STATUS),
993 /* cpussCm0StatusOffset */ offsetof(CPUSS_Type, CM0_STATUS),
994 /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_Type, CM4_PWR_CTL),
995 /* cpussTrimRamCtlOffset */ offsetof(CPUSS_Type, TRIM_RAM_CTL),
996 /* cpussTrimRomCtlOffset */ offsetof(CPUSS_Type, TRIM_ROM_CTL),
997 /* cpussSysTickCtlOffset */ offsetof(CPUSS_Type, SYSTICK_CTL),
998 /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_Type, CM0_NMI_CTL),
999 /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_Type, CM4_NMI_CTL),
1000 /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_Type, ROM_CTL),
1001 /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_Type, RAM0_CTL0),
1002 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_Type, RAM1_CTL0),
1003 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_Type, RAM2_CTL0),
1004 /* cpussRam0PwrCtl */ (uint16_t)offsetof(CPUSS_Type, RAM0_PWR_MACRO_CTL),
1005 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_Type, RAM1_PWR_CTL),
1006 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_Type, RAM2_PWR_CTL),
1007
1008 /* IPC registers */
1009 /* ipcStructSize */ (uint16_t)sizeof(IPC_STRUCT_Type),
1010 /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_Type, LOCK_STATUS),
1011 };
1012
1013 /******************************************************************************
1014 * Function Name: Cy_PDL_Init
1015 ****************************************************************************//**
1016 *
1017 * \brief Initializes the platform and peripheral block configuration for the
1018 * given target device.
1019 *
1020 * \param device
1021 * Pointer to the platform and peripheral block configuration
1022 *
1023 * \note
1024 * This function must be called prior calling any function in PDL.
1025 *
1026 *******************************************************************************/
Cy_PDL_Init(const cy_stc_device_t * device)1027 void Cy_PDL_Init(const cy_stc_device_t * device)
1028 {
1029 cy_device = device;
1030 }
1031
1032
1033 /* [] END OF FILE */
1034
