1/* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <arm/armv8-m.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 13#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 14 15/ { 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu1: cpu@0 { 21 compatible = "arm,cortex-m33f"; 22 reg = <0>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 mpu: mpu@e000ed90 { 27 compatible = "arm,armv8m-mpu"; 28 reg = <0xe000ed90 0x40>; 29 }; 30 }; 31 }; 32 33 soc { 34 sram: sram@10000000 { 35 ranges = <0x0 0x10000000 0x780000 36 0x20000000 0x30000000 0x780000>; 37 }; 38 39 peripheral: peripheral@50000000 { 40 ranges = <0x0 0x50000000 0x10000000>; 41 }; 42 43 xspi2: spi@50411000 { 44 reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; 45 }; 46 47 }; 48 49 pinctrl: pinctrl { 50 compatible = "nxp,rt-iocon-pinctrl"; 51 }; 52}; 53 54&sram { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 /* RT7XX SRAM partitions are shared between code and data. Boards can 59 * override the reg properties of either sram0 or sram_code nodes to 60 * change the balance of SRAM allocation. 61 * 62 * The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data. 63 * The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application. 64 * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application. 65 */ 66 67 sram_code: memory@600000{ 68 compatible = "mmio-sram"; 69 reg = <0x600000 DT_SIZE_K(512)>; 70 }; 71 72 /* This partition is shared with code in RAM */ 73 sram_shared_code: memory@20058000{ 74 compatible = "mmio-sram"; 75 reg = <0x20058000 DT_SIZE_K(256)>; 76 }; 77 78 sram0: memory@205C0000 { 79 compatible = "mmio-sram"; 80 /* Only use 256K, align with SDK */ 81 reg = <0x205C0000 DT_SIZE_K(256)>; 82 }; 83}; 84 85&peripheral { 86 #address-cells = <1>; 87 #size-cells = <1>; 88 /* 89 * Note that the offsets here are relative to the base address. 90 * The base addresses differ between non-secure (0x40000000) 91 * and secure modes (0x50000000). 92 */ 93 94 lpadc0: adc@20c000 { 95 compatible = "nxp,lpc-lpadc"; 96 reg = <0x20c000 0x304>; 97 interrupts = <15 0>; 98 status = "disabled"; 99 clk-divider = <1>; 100 clk-source = <0>; 101 voltage-ref= <1>; 102 calibration-average = <128>; 103 power-level = <0>; 104 offset-value-a = <10>; 105 offset-value-b = <10>; 106 #io-channel-cells = <1>; 107 clocks = <&clkctl3 MCUX_LPADC1_CLK>; 108 }; 109 110 rstctl1: reset@40000 { 111 compatible = "nxp,rstctl"; 112 reg = <0x40000 0x1000>; 113 #reset-cells = <1>; 114 }; 115 116 rstctl2: reset@67000 { 117 compatible = "nxp,rstctl"; 118 reg = <0x67000 0x1000>; 119 #reset-cells = <1>; 120 }; 121 122 rstctl3: reset@60000 { 123 compatible = "nxp,rstctl"; 124 reg = <0x60000 0x1000>; 125 #reset-cells = <1>; 126 }; 127 128 rstctl4: reset@a0000 { 129 compatible = "nxp,rstctl"; 130 reg = <0xa0000 0x1000>; 131 #reset-cells = <1>; 132 }; 133 134 clkctl1: clkctl@41000 { 135 compatible = "nxp,lpc-syscon"; 136 reg = <0x41000 0x1000>; 137 #clock-cells = <1>; 138 }; 139 140 clkctl2: clkctl@65000 { 141 compatible = "nxp,lpc-syscon"; 142 reg = <0x65000 0x1000>; 143 #clock-cells = <1>; 144 }; 145 146 clkctl3: clkctl@61000 { 147 compatible = "nxp,lpc-syscon"; 148 reg = <0x61000 0x1000>; 149 #clock-cells = <1>; 150 }; 151 152 clkctl4: clkctl@a1000 { 153 compatible = "nxp,lpc-syscon"; 154 reg = <0xa1000 0x1000>; 155 #clock-cells = <1>; 156 }; 157 158 ctimer5: ctimer@48000 { 159 compatible = "nxp,lpc-ctimer"; 160 reg = <0x48000 0x1000>; 161 interrupts = <7 0>; 162 status = "disabled"; 163 clk-source = <1>; 164 clocks = <&clkctl1 MCUX_CTIMER5_CLK>; 165 mode = <0>; 166 input = <0>; 167 prescale = <0>; 168 }; 169 170 ctimer6: ctimer@49000 { 171 compatible = "nxp,lpc-ctimer"; 172 reg = <0x49000 0x1000>; 173 interrupts = <8 0>; 174 status = "disabled"; 175 clk-source = <1>; 176 clocks = <&clkctl1 MCUX_CTIMER6_CLK>; 177 mode = <0>; 178 input = <0>; 179 prescale = <0>; 180 }; 181 182 ctimer7: ctimer@4a000 { 183 compatible = "nxp,lpc-ctimer"; 184 reg = <0x4a000 0x1000>; 185 interrupts = <9 0>; 186 status = "disabled"; 187 clk-source = <1>; 188 clocks = <&clkctl1 MCUX_CTIMER7_CLK>; 189 mode = <0>; 190 input = <0>; 191 prescale = <0>; 192 }; 193 194 syscon1: syscon@42000 { 195 compatible = "nxp,lpc-syscon"; 196 reg = <0x42000 0x1000>; 197 #clock-cells = <1>; 198 }; 199 200 syscon2: syscon@66000 { 201 compatible = "nxp,lpc-syscon"; 202 reg = <0x66000 0x1000>; 203 #clock-cells = <1>; 204 }; 205 206 syscon3: syscon@62000 { 207 compatible = "nxp,lpc-syscon"; 208 reg = <0x62000 0x1000>; 209 #clock-cells = <1>; 210 }; 211 212 syscon4: syscon@a2000 { 213 compatible = "nxp,lpc-syscon"; 214 reg = <0xa2000 0x1000>; 215 #clock-cells = <1>; 216 }; 217 218 iocon1: iocon@64000 { 219 compatible = "nxp,lpc-iocon"; 220 reg = <0x64000 0x1000>; 221 status = "okay"; 222 }; 223 224 iocon2: iocon@a5000 { 225 compatible = "nxp,lpc-iocon"; 226 reg = <0xa5000 0x1000>; 227 status = "okay"; 228 }; 229 230 gpio8: gpio@320000 { 231 compatible = "nxp,kinetis-gpio"; 232 status = "disabled"; 233 reg = <0x320000 0x1000>; 234 interrupts = <61 0>,<62 0>; 235 gpio-controller; 236 #gpio-cells = <2>; 237 nxp,kinetis-port = <&gpio8>; 238 gpio-port-offest = <8>; 239 }; 240 241 gpio9: gpio@322000 { 242 compatible = "nxp,kinetis-gpio"; 243 status = "disabled"; 244 reg = <0x322000 0x1000>; 245 interrupts = <63 0>,<64 0>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 nxp,kinetis-port = <&gpio9>; 249 gpio-port-offest = <8>; 250 }; 251 252 gpio10: gpio@324000 { 253 compatible = "nxp,kinetis-gpio"; 254 status = "disabled"; 255 reg = <0x324000 0x1000>; 256 interrupts = <65 0>,<66 0>; 257 gpio-controller; 258 #gpio-cells = <2>; 259 nxp,kinetis-port = <&gpio10>; 260 gpio-port-offest = <8>; 261 }; 262 263 flexcomm17: flexcomm@326000 { 264 compatible = "nxp,lp-flexcomm"; 265 reg = <0x326000 0x1000>; 266 interrupts = <11 0>; 267 status = "disabled"; 268 269 /* Empty ranges property implies parent and child address space is identical */ 270 ranges = <>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 274 flexcomm17_lpuart17: uart@326000 { 275 compatible = "nxp,lpuart"; 276 reg = <0x326000 0x1000>; 277 clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; 278 status = "disabled"; 279 }; 280 flexcomm17_lpspi17: lpspi@326000 { 281 compatible = "nxp,lpspi"; 282 reg = <0x326000 0x1000>; 283 clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 tx-fifo-size = <8>; 287 rx-fifo-size = <8>; 288 status = "disabled"; 289 }; 290 flexcomm17_lpi2c17: lpi2c@326800 { 291 compatible = "nxp,lpi2c"; 292 reg = <0x326800 0x1000>; 293 clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 status = "disabled"; 297 }; 298 }; 299 300 flexcomm18: flexcomm@327000 { 301 compatible = "nxp,lp-flexcomm"; 302 reg = <0x327000 0x1000>; 303 interrupts = <12 0>; 304 status = "disabled"; 305 306 /* Empty ranges property implies parent and child address space is identical */ 307 ranges = <>; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 311 flexcomm18_lpuart18: uart@327000 { 312 compatible = "nxp,lpuart"; 313 reg = <0x327000 0x1000>; 314 clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; 315 status = "disabled"; 316 }; 317 flexcomm18_lpspi18: lpspi@327000 { 318 compatible = "nxp,lpspi"; 319 reg = <0x327000 0x1000>; 320 clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 tx-fifo-size = <8>; 324 rx-fifo-size = <8>; 325 status = "disabled"; 326 }; 327 flexcomm18_lpi2c18: lpi2c@327800 { 328 compatible = "nxp,lpi2c"; 329 reg = <0x327800 0x1000>; 330 clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 status = "disabled"; 334 }; 335 }; 336 337 flexcomm19: flexcomm@328000 { 338 compatible = "nxp,lp-flexcomm"; 339 reg = <0x328000 0x1000>; 340 interrupts = <13 0>; 341 status = "disabled"; 342 343 /* Empty ranges property implies parent and child address space is identical */ 344 ranges = <>; 345 #address-cells = <1>; 346 #size-cells = <1>; 347 348 flexcomm19_lpuart19: uart@328000 { 349 compatible = "nxp,lpuart"; 350 reg = <0x328000 0x1000>; 351 clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; 352 status = "disabled"; 353 }; 354 flexcomm19_lpspi19: lpspi@328000 { 355 compatible = "nxp,lpspi"; 356 reg = <0x328000 0x1000>; 357 clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 tx-fifo-size = <8>; 361 rx-fifo-size = <8>; 362 status = "disabled"; 363 }; 364 flexcomm19_lpi2c19: lpi2c@328800 { 365 compatible = "nxp,lpi2c"; 366 reg = <0x328800 0x1000>; 367 clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 status = "disabled"; 371 }; 372 }; 373 374 flexcomm20: flexcomm@329000 { 375 compatible = "nxp,lp-flexcomm"; 376 reg = <0x329000 0x1000>; 377 interrupts = <14 0>; 378 status = "disabled"; 379 380 /* Empty ranges property implies parent and child address space is identical */ 381 ranges = <>; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 385 flexcomm20_lpuart20: uart@329000 { 386 compatible = "nxp,lpuart"; 387 reg = <0x329000 0x1000>; 388 clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; 389 status = "disabled"; 390 }; 391 flexcomm20_lpspi20: lpspi@329000 { 392 compatible = "nxp,lpspi"; 393 reg = <0x329000 0x1000>; 394 clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 tx-fifo-size = <8>; 398 rx-fifo-size = <8>; 399 status = "disabled"; 400 }; 401 flexcomm20_lpi2c20: lpi2c@329800 { 402 compatible = "nxp,lpi2c"; 403 reg = <0x329800 0x1000>; 404 clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 }; 410 411 /* LPFlexcomm15 only support LPI2C function. */ 412 lpi2c15: i2c@213000 { 413 compatible = "nxp,lpi2c"; 414 reg = <0x213000 0x1000>; 415 interrupts = <14 0>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&clkctl4 MCUX_LPI2C15_CLK>; 419 status = "disabled"; 420 }; 421 422 os_timer_cpu1: timers@209000 { 423 compatible = "nxp,os-timer"; 424 reg = <0x209000 0x1000>; 425 interrupts = <30 0>; 426 status = "disabled"; 427 }; 428}; 429 430&nvic { 431 arm,num-irq-priority-bits = <3>; 432}; 433 434&systick { 435 /* 436 * RT700 cm33_cpu1 relies by default on the OS Timer for system 437 * clock implementation, so the SysTick node is not to be enabled. 438 */ 439 status = "disabled"; 440}; 441
