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Searched defs:csr (Results 1 – 7 of 7) sorted by relevance

/Zephyr-Core-3.5.0/drivers/regulator/
Dregulator_nxp_vref.c37 volatile uint32_t *const csr = &base->CSR; in regulator_nxp_vref_enable() local
74 uint32_t csr = base->CSR; in regulator_nxp_vref_set_mode() local
111 uint32_t csr = base->CSR; in regulator_nxp_vref_get_mode() local
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_swerv_pic.c37 #define swerv_piccsr(csr) SWERV_PIC_##csr argument
39 #define swerv_pic_readcsr(csr, value) \ argument
41 #define swerv_pic_writecsr(csr, value) \ argument
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dcsr.h185 #define csr_read(csr) \ argument
193 #define csr_write(csr, val) \ argument
202 #define csr_read_set(csr, val) \ argument
211 #define csr_set(csr, val) \ argument
219 #define csr_read_clear(csr, val) \ argument
228 #define csr_clear(csr, val) \ argument
/Zephyr-Core-3.5.0/drivers/timer/
Drv32m1_lptmr_timer.c76 uint32_t csr, psr, sircdiv; /* LPTMR registers */ in sys_clock_driver_init() local
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Dadsp_ipc_regs.h23 uint32_t csr; member
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Dadsp_ipc_regs.h30 uint32_t csr; member
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/
Dadsp_ipc_regs.h30 uint32_t csr; member