1 /***************************************************************************//**
2 * \file cy_mcwdt.h
3 * \version 1.70
4 *
5 * Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_mcwdt
28 * \{
29 * A MCWDT has two 16-bit counters and one 32-bit counter.
30 *
31 * The functions and other declarations used in this driver are in cy_mcwdt.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * You can use this driver to create a free-running
36 * timer or generate periodic interrupts. The driver also
37 * includes support for the watchdog function to recover from CPU or
38 * firmware failures.
39 *
40 * There are two primary use cases for MCWDT: generating periodic CPU interrupts;
41 * and implementing a free-running timer. Both have many applications in
42 * embedded systems:
43 * * Measuring time between events
44 * * Generating periodic events
45 * * Synchronizing actions
46 * * Real-time clocking
47 * * Polling
48 *
49 * An additional use case is to implement a watchdog used for recovering from a CPU or
50 * firmware failure.
51 *
52 * \section group_mcwdt_configuration Configuration Considerations
53 *
54 * Each MCWDT may be configured for a particular product.
55 * One MCWDT block can be associated with only one CPU during runtime.
56 * A single MCWDT is not intended to be used by multiple CPUs simultaneously.
57 * Each block contains three sub-counters, each of which can be configured for
58 * various system utility functions - free running counter, periodic interrupts,
59 * watchdog reset, or three interrupts followed by a watchdog reset.
60 * All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
61 * counter.
62 * A simplified diagram of the MCWDT hardware is shown below:
63 * \image html mcwdt.png
64 * The frequency of the periodic interrupts can be configured using the Match
65 * value with combining Clear on match option, which can be set individually
66 * for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
67 * is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
68 * after 65535 counts and the match value defines the shift between interrupts
69 * (see the figure below). The enabled Clear on match option
70 * resets the counter when the interrupt occurs.
71 * \image html mcwdt_counters.png
72 * 32-bit sub-counter C2 does not have Clear on match option.
73 * The interrupt of counter C2 occurs when the counts equal
74 * 2<sup>Toggle bit</sup> value.
75 * \image html mcwdt_subcounters.png
76 * To set up an MCWDT, provide the configuration parameters in the
77 * cy_stc_mcwdt_config_t structure. Then call
78 * Cy_MCWDT_Init() to initialize the driver.
79 * Call Cy_MCWDT_Enable() to enable all specified counters.
80 *
81 * You can also set the mode of operation for any counter. If you choose
82 * interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
83 * parameter for the masks described in Macro Section. All counter interrupts
84 * are OR'd together to from a single combined MCWDT interrupt.
85 * Additionally, enable the Global interrupts and initialize the referenced
86 * interrupt by setting the priority and the interrupt vector using
87 * \ref Cy_SysInt_Init() of the sysint driver.
88 *
89 * The values of the MCWDT counters can be monitored using
90 * Cy_MCWDT_GetCount().
91 *
92 * CAT1C devices supports MCWDT_B type of counters, which are slightly different
93 * from MCWDT, which is explained above
94 *
95 * A simplified diagram of the MCWDT_B hardware is shown below:
96 * \image html mcwdt_b.png
97 *
98 * \note Please refer to TRM for more information on CAT1C supported MCWDT_B counters.
99 *
100 * \note In addition to the MCWDTs, each device has a separate watchdog timer
101 * (WDT) that can also be used to generate a watchdog reset or periodic
102 * interrupts. For more information on the WDT, see the appropriate section
103 * of the PDL.
104 *
105 * \section group_mcwdt_more_information More Information
106 *
107 * For more information on the MCWDT peripheral, refer to
108 * the technical reference manual (TRM).
109 *
110 * \section group_mcwdt_changelog Changelog
111 * <table class="doxtable">
112 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
113 * <tr>
114 * <td>1.70</td>
115 * <td>Added MCWDT_B type support required for CAT1C devices.<br>Newly added APIs:
116 * \n Cy_MCWDT_SetLowerAction(),
117 * \n Cy_MCWDT_SetUpperAction(),
118 * \n Cy_MCWDT_SetWarnAction(),
119 * \n Cy_MCWDT_SetSubCounter2Action(),
120 * \n Cy_MCWDT_GetLowerAction(),
121 * \n Cy_MCWDT_GetUpperAction(),
122 * \n Cy_MCWDT_GetWarnAction(),
123 * \n Cy_MCWDT_GetSubCounter2Action(),
124 * \n Cy_MCWDT_SetAutoService(),
125 * \n Cy_MCWDT_GetAutoService(),
126 * \n Cy_MCWDT_SetSleepDeepPause(),
127 * \n Cy_MCWDT_GetSleepDeepPause(),
128 * \n Cy_MCWDT_SetDebugRun(),
129 * \n Cy_MCWDT_GetDebugRun(),
130 * \n Cy_MCWDT_SetLowerLimit(),
131 * \n Cy_MCWDT_SetUpperLimit(),
132 * \n Cy_MCWDT_SetWarnLimit(),
133 * \n Cy_MCWDT_GetLowerLimit(),
134 * \n Cy_MCWDT_GetUpperLimit(),
135 * \n Cy_MCWDT_GetWarnLimit(),
136 * \n Cy_MCWDT_WaitForCounterReset(),
137 * \n Cy_MCWDT_CpuSelectForDpSlpPauseAction(),
138 * \n Cy_MCWDT_GetCascadeMatchCombined().</td>
139 * <td>Support for new devices.</td>
140 * </tr>
141 * <tr>
142 * <td>1.60</td>
143 * <td>CAT1B, CAT1C devices support.<br>Newly added APIs:
144 * \n Cy_MCWDT_GetLowerLimit() to get the lower limit value of the specified counter,
145 * \n Cy_MCWDT_SetLowerLimit() to set the the lower limit value of the specified counter,
146 * \n Cy_MCWDT_GetLowerLimitMode() to get the lower limit mode of the specified counter,
147 * \n Cy_MCWDT_SetLowerLimitMode() to set the lower limit mode of the specified counter,
148 * \n Cy_MCWDT_GetLowerLimitCascaded() to get the lower limit registers cascaded value,
149 * \n Cy_MCWDT_SetCascadeCarryOutRollOver() to enable the Rollover mode for carryout,
150 * \n Cy_MCWDT_GetCascadeCarryOutRollOver() to check if Rollover mode enabled for carryout or not,
151 * \n Cy_MCWDT_SetCascadeMatchCombined() to set the match to combined cascade counters,
152 * \n Cy_MCWDT_GetCascadeMatchCombined() to report if match is enabled with combined cascade counters or not.</td>
153 * <td>Support for new devices.</td>
154 * </tr>
155 * <tr>
156 * <td>1.50.1</td>
157 * <td>Minor documentation updates.</td>
158 * <td>Documentation enhancement.</td>
159 * </tr>
160 * <tr>
161 * <td>1.50</td>
162 * <td>Added support for new family of devices.</td>
163 * <td>New device support.</td>
164 * </tr>
165 * <tr>
166 * <td>1.40</td>
167 * <td>Fixed/documented MISRA 2012 violations.</td>
168 * <td>MISRA 2012 compliance.</td>
169 * </tr>
170 * <tr>
171 * <td>1.30.1</td>
172 * <td>Minor documentation updates.</td>
173 * <td>Documentation enhancement.</td>
174 * </tr>
175 * <tr>
176 * <td>1.30</td>
177 * <td>In version 1.20 the Cy_MCWDT_GetCountCascaded() function
178 * returned the wrong value when counter#1 overflowed.
179 * This bug is corrected in version 1.30.
180 * </td>
181 * <td>Defect fixes.
182 * </td>
183 * </tr>
184 * <tr>
185 * <td rowspan="2">1.20</td>
186 * <td>Flattened the organization of the driver source code into the single
187 * source directory and the single include directory.
188 * </td>
189 * <td>Driver library directory-structure simplification.</td>
190 * </tr>
191 * <tr>
192 * <td>Added register access layer. Use register access macros instead
193 * of direct register access using dereferenced pointers.</td>
194 * <td>Makes register access device-independent, so that the PDL does
195 * not need to be recompiled for each supported part number.</td>
196 * </tr>
197 * <tr>
198 * <td>1.10.1</td>
199 * <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
200 * <td>Documentation update and clarification</td>
201 * </tr>
202 * <tr>
203 * <td>1.10</td>
204 * <td>Added input parameter validation to the API functions.<br>
205 * Added API function GetCountCascaded()</td>
206 * <td></td>
207 * </tr>
208 * <tr>
209 * <td>1.0</td>
210 * <td>Initial version</td>
211 * <td></td>
212 * </tr>
213 * </table>
214 *
215 * \defgroup group_mcwdt_macros Macros
216 * \defgroup group_mcwdt_functions Functions
217 * \defgroup group_mcwdt_data_structures Data Structures
218 * \defgroup group_mcwdt_enums Enumerated Types
219 */
220
221 #ifndef CY_MCWDT_H
222 #define CY_MCWDT_H
223
224 #if defined(__cplusplus)
225 extern "C" {
226 #endif
227
228 #include "cy_device.h"
229
230 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS)
231
232 #include <stdbool.h>
233 #include <stddef.h>
234 #include "cy_syslib.h"
235
236
237 /**
238 * \addtogroup group_mcwdt_macros
239 * \{
240 */
241
242 /** Driver major version */
243 #define CY_MCWDT_DRV_VERSION_MAJOR 1
244
245 /** Driver minor version */
246 #define CY_MCWDT_DRV_VERSION_MINOR 70
247
248 /** \cond INTERNAL_MACROS */
249
250 /***************************************
251 * Registers Constants
252 ***************************************/
253
254 #define CY_MCWDT_LOCK_CLR0 (1u)
255 #define CY_MCWDT_LOCK_CLR1 (2u)
256 #define CY_MCWDT_LOCK_SET01 (3u)
257
258 #define CY_MCWDT_BYTE_SHIFT (8u)
259 #define CY_MCWDT_C0C1_MODE_MASK (3u)
260 #define CY_MCWDT_C2_MODE_MASK (1u)
261
262
263 /***************************************
264 * API Constants
265 ***************************************/
266
267 #define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
268 MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
269
270 #define CY_MCWDT_CTR0_Pos (0u)
271 #define CY_MCWDT_CTR1_Pos (1u)
272 #define CY_MCWDT_CTR2_Pos (2u)
273 #define CY_MCWDT_CTR_Pos (0UL)
274
275 /** \endcond */
276
277 #define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
278
279 #define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
280 that handle multiple counters, including Cy_MCWDT_Enable(),
281 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
282 #define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
283 that handle multiple counters, including Cy_MCWDT_Enable(),
284 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
285 #define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
286 that handle multiple counters, including Cy_MCWDT_Enable(),
287 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
288 #define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
289 that handle multiple counters, including Cy_MCWDT_Enable(),
290 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
291
292 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
293 /** For compatibility with CAT1C MCWDT driver */
294 #define MCWDT_STRUCT_Type MCWDT_Type
295 #endif
296
297 /** \} group_mcwdt_macros */
298
299
300 /**
301 * \addtogroup group_mcwdt_enums
302 * \{
303 */
304
305 /** The mcwdt sub-counter identifiers. */
306 typedef enum
307 {
308 CY_MCWDT_COUNTER0, /**< Sub-counter#0 identifier. */
309 CY_MCWDT_COUNTER1, /**< Sub-counter#1 identifier. */
310 CY_MCWDT_COUNTER2 /**< Sub-counter#2 identifier. */
311 } cy_en_mcwdtctr_t;
312
313 /** The mcwdt modes. */
314 typedef enum
315 {
316 CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
317 CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
318 CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
319 CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
320 Set/GetMode functions. */
321 } cy_en_mcwdtmode_t;
322
323 /** The mcwdt cascading. */
324 typedef enum
325 {
326 CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
327 CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
328 It is used for Set/GetCascade functions. */
329 CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
330 It is used for Set/GetCascade functions. */
331 CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
332 and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
333 It is used for Set/GetCascade functions. */
334 } cy_en_mcwdtcascade_t;
335
336 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
337 /** The mcwdt lower limit identifiers. */
338 /**
339 * \note
340 * This enum is available for CAT1B devices.
341 **/
342 typedef enum
343 {
344 CY_MCWDT_LOWER_LIMIT0, /**< Lower limit for Sub-counter#0 identifier. */
345 CY_MCWDT_LOWER_LIMIT1, /**< Lower limit for Sub-counter#1 identifier. */
346 } cy_en_mcwdtlowerlimit_t;
347
348 /** The mcwdt lower limit mode identifiers. */
349 /**
350 * \note
351 * This enum is available for CAT1B devices.
352 **/
353 typedef enum
354 {
355 CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, /**< Do nothing. */
356 CY_MCWDT_LOWER_LIMIT_MODE_INT, /**< Assert WDT_INTx. */
357 CY_MCWDT_LOWER_LIMIT_MODE_RESET, /**< Assert WDT Reset. */
358 } cy_en_mcwdtlowerlimitmode_t;
359 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS*/
360
361 /** The MCWDT error codes. */
362 typedef enum
363 {
364 CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
365 CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
366 } cy_en_mcwdt_status_t;
367
368 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
369 /** The MCWDT Enable/Disable identifiers. */
370 /**
371 * \note
372 * Below enum is available for CAT1C devices only.
373 **/
374 typedef enum
375 {
376 CY_MCWDT_DISABLE = 0u,
377 CY_MCWDT_ENABLE,
378 } cy_en_mcwdt_enable_t;
379
380 /** The MCWDT Deep Sleep Cores identifiers. */
381 /**
382 * \note
383 * Below enum is available for CAT1C devices only.
384 **/
385 typedef enum
386 {
387 CY_MCWDT_PAUSED_BY_DPSLP_CM0 = 0u,
388 CY_MCWDT_PAUSED_BY_DPSLP_CM7_0 = 1u,
389 CY_MCWDT_PAUSED_BY_DPSLP_CM7_1 = 2u,
390 CY_MCWDT_PAUSED_BY_NO_CORE = 3u,
391 } cy_en_mcwdt_select_core_t;
392
393 /** The MCWDT subcounter 2 actions. */
394 /**
395 * \note
396 * Below enum is available for CAT1C devices only.
397 **/
398 typedef enum
399 {
400 CY_MCWDT_CNT2_ACTION_NONE,
401 CY_MCWDT_CNT2_ACTION_INT,
402 } cy_en_mcwdt_cnt2_action_t;
403
404 /** The MCWDT lower and upper actions. */
405 /**
406 * \note
407 * Below enum is available for CAT1C devices only.
408 **/
409 typedef enum
410 {
411 CY_MCWDT_ACTION_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
412 CY_MCWDT_ACTION_FAULT, /**< The Fault mode. It is used for Set/GetMode functions. */
413 CY_MCWDT_ACTION_FAULT_THEN_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
414 } cy_en_mcwdt_lower_upper_action_t;
415
416 /** The MCWDT warn actions. */
417 typedef enum
418 {
419 CY_MCWDT_WARN_ACTION_NONE,
420 CY_MCWDT_WARN_ACTION_INT,
421 } cy_en_mcwdt_warn_action_t;
422
423 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) */
424
425 /** \} group_mcwdt_enums */
426
427 /**
428 * \addtogroup group_mcwdt_data_structures
429 * \{
430 */
431
432 /** The MCWDT component configuration structure. */
433 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
434 typedef struct
435 {
436 uint16_t c0LowerLimit; /**< The sub-counter#0 lower limit value, for reset or fault.
437 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
438 Only for CAT1C devices*/
439 uint16_t c0UpperLimit; /**< The sub-counter#0 upper limit value, for reset or fault.
440 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
441 Only for CAT1C devices*/
442 uint16_t c0WarnLimit; /**< The sub-counter#0 warn limit value, for interrupt.
443 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
444 Only for CAT1C devices*/
445 cy_en_mcwdt_lower_upper_action_t c0LowerAction; /**< The sub-counter#0 action. It can have the following values:
446 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C devices*/
447 cy_en_mcwdt_lower_upper_action_t c0UpperAction; /**< The sub-counter#0 action. It can have the following values:
448 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C devices*/
449 cy_en_mcwdt_warn_action_t c0WarnAction; /**< The sub-counter#0 warn action. It can have the following values:
450 \ref cy_en_mcwdt_warn_action_t. Only for CAT1C devices*/
451 cy_en_mcwdt_enable_t c0AutoService; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
452 Range: FALSE - TRUE. Only for CAT1C devices*/
453 cy_en_mcwdt_enable_t c0SleepDeepPause; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
454 Range: FALSE - TRUE. Only for CAT1C devices*/
455 cy_en_mcwdt_enable_t c0DebugRun; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
456 Range: FALSE - TRUE. Only for CAT1C devices*/
457 uint16_t c1LowerLimit; /**< The sub-counter#0 lower limit value, for reset or fault.
458 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
459 Only for CAT1C devices*/
460 uint16_t c1UpperLimit; /**< The sub-counter#0 upper limit value, for reset or fault.
461 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
462 Only for CAT1C devices*/
463 uint16_t c1WarnLimit; /**< The sub-counter#0 warn limit value, for interrupt.
464 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
465 Only for CAT1C devices*/
466 cy_en_mcwdt_lower_upper_action_t c1LowerAction; /**< The sub-counter#1 action. It can have the following values:
467 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C devices*/
468 cy_en_mcwdt_lower_upper_action_t c1UpperAction; /**< The sub-counter#1 action. It can have the following values:
469 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C devices*/
470 cy_en_mcwdt_warn_action_t c1WarnAction; /**< The sub-counter#1 warn action. It can have the following values:
471 \ref cy_en_mcwdt_warn_action_t. Only for CAT1C devices*/
472 cy_en_mcwdt_enable_t c1AutoService; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
473 Range: FALSE - TRUE. Only for CAT1C devices*/
474 cy_en_mcwdt_enable_t c1SleepDeepPause; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
475 Range: FALSE - TRUE. Only for CAT1C devices*/
476 cy_en_mcwdt_enable_t c1DebugRun; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
477 Range: FALSE - TRUE. Only for CAT1C devices*/
478 uint32_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value. Only for CAT1C devices*/
479 cy_en_mcwdt_cnt2_action_t c2Action; /**< The sub-counter#2 mode. It can have the following values:
480 \ref cy_en_mcwdt_cnt2_action_t. Only for CAT1C devices*/
481 cy_en_mcwdt_enable_t c2SleepDeepPause; /**< The sub-counter#2 Auto Service parameter enabled/disabled.
482 Range: FALSE - TRUE. Only for CAT1C devices*/
483 cy_en_mcwdt_enable_t c2DebugRun; /**< The sub-counter#2 Auto Service parameter enabled/disabled. Only for CAT1C devices **/
484
485 cy_en_mcwdt_select_core_t coreSelect; /**< Selecting the the core. The DeepSleep of the core pauses this MCWDT counter Only for CAT1C devices **/
486 } cy_stc_mcwdt_config_t;
487 #endif
488
489
490 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_IP_MXS22SRSS)
491 /**
492 * \note
493 * Below structure variables are available for CAT1A, CAT1B and CAT1D devices.
494 **/
495 typedef struct
496 {
497 uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
498 Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
499 c0ClearOnMatch = 1. For CAT1A, CAT1B and CAT1D devices */
500 uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
501 Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
502 c1ClearOnMatch = 1. For CAT1A, CAT1B and CAT1D devices */
503 uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
504 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET.
505 For CAT1A, CAT1B and CAT1D devices */
506 uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
507 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET.
508 For CAT1A, CAT1B and CAT1D devices */
509 uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
510 Range: 0 - 31. For CAT1A, CAT1B and CAT1D devices */
511 uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
512 and \ref CY_MCWDT_MODE_INT. For CAT1A, CAT1B and CAT1D devices */
513 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
514 uint16_t c0LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
515 Range: 0 - 65535. Only for CAT1B devices */
516 uint16_t c1LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
517 Range: 0 - 65535. Only for CAT1B devices */
518 uint16_t c0LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
519 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset.
520 Only for CAT1B devices */
521 uint16_t c1LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
522 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset.
523 Only for CAT1B devices */
524 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
525
526 /**
527 * \note
528 * This parameter is available for devices having MXS40SSRSS IP.
529 **/
530
531 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
532 bool c0c1carryoutconfig; /**< Carryout behaviour that applies when counter 0 and 1 are cascaded
533 false: carry out on counter 0 match, true: carry out on counter 0 roll-over.
534 Only for CAT1B devices */
535 bool c0c1matchconfig; /**< Matching behaviour that applies when counter 0 and 1 are cascaded
536 false: Match based on counter 1 alone, true: Match based on counter 1 and 0 simultaneously.
537 Only for CAT1B devices */
538 bool c1c2carryoutconfig; /**< Carryout behaviour that applies when counter 1 and 2 are cascaded
539 false: carry out on counter 1 match, true: carry out on counter 1 roll-over.
540 Only for CAT1B devices */
541 bool c1c2matchconfig; /**< Matching behaviour that applies when counter 1 and 2 are cascaded
542 false: Match based on counter 1 alone, true: Match based on counter 2 and 1 simultaneously.
543 Only for CAT1B devices */
544 #endif /* CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
545
546 bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. For CAT1A, CAT1B and CAT1D devices */
547 bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. For CAT1A, CAT1B and CAT1D devices */
548 bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. For CAT1A, CAT1B and CAT1D devices */
549 bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. For CAT1A, CAT1B and CAT1D devices */
550 } cy_stc_mcwdt_config_t;
551 #endif
552 /** \} group_mcwdt_data_structures */
553
554
555 /** \cond PARAM_CHECK_MACROS */
556
557 /** Parameter check macros */
558 #define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
559
560 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
561 #define CY_MCWDT_IS_LOWER_LIMIT_VALID(counter) ((CY_MCWDT_LOWER_LIMIT0 == (counter)) || \
562 (CY_MCWDT_LOWER_LIMIT1 == (counter)))
563
564 #define CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode) ((CY_MCWDT_LOWER_LIMIT_MODE_NOTHING == (mode)) || \
565 (CY_MCWDT_LOWER_LIMIT_MODE_INT == (mode)) || \
566 (CY_MCWDT_LOWER_LIMIT_MODE_RESET == (mode)))
567 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
568
569 #define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
570 (CY_MCWDT_COUNTER1 == (counter)) || \
571 (CY_MCWDT_COUNTER2 == (counter)))
572
573 #define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
574 (CY_MCWDT_MODE_INT == (mode)) || \
575 (CY_MCWDT_MODE_RESET == (mode)) || \
576 (CY_MCWDT_MODE_INT_RESET == (mode)))
577
578 #define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
579
580
581 #define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
582 (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
583 (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
584 (CY_MCWDT_CASCADE_BOTH == (cascade)))
585
586 #define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
587
588 #define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
589
590 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
591 #define CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
592 (CY_MCWDT_CASCADE_C1C2 == (cascade)))
593 #endif
594
595 /** \endcond */
596
597
598 /*******************************************************************************
599 * Function Prototypes
600 *******************************************************************************/
601
602 /**
603 * \addtogroup group_mcwdt_functions
604 * \{
605 */
606 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config);
607 void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
608 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
609 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
610 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
611 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
612 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
613 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
614 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) || defined (CY_IP_MXS22SRSS)
615 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode);
616 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
617 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
618 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
619 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade);
620 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base);
621 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs);
622 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
623 uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
624 #endif
625 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
626 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base);
627 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
628 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
629 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base);
630 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
631 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
632 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
633 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
634 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
635 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
636 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
637 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs);
638 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
639 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode);
640 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base);
641 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
642
643 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
644 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool carryoutconfig);
645 __STATIC_INLINE bool Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
646
647 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool matchconfig);
648 __STATIC_INLINE bool Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
649 #endif /* CY_IP_MXS40SSRSS,CY_IP_MXS22SRSS */
650
651 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
652 void Cy_MCWDT_CpuSelectForDpSlpPauseAction(MCWDT_Type *base, cy_en_mcwdt_select_core_t core);
653 void Cy_MCWDT_SetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action);
654 void Cy_MCWDT_SetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action);
655 void Cy_MCWDT_SetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_warn_action_t action);
656 void Cy_MCWDT_SetSubCounter2Action(MCWDT_Type *base, cy_en_mcwdt_cnt2_action_t action);
657 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
658 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
659 cy_en_mcwdt_warn_action_t Cy_MCWDT_GetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
660 cy_en_mcwdt_cnt2_action_t Cy_MCWDT_GetSubCounter2Action(MCWDT_Type *base);
661 void Cy_MCWDT_SetAutoService(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
662 uint32_t Cy_MCWDT_GetAutoService(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
663 uint32_t Cy_MCWDT_GetSleepDeepPause(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
664 void Cy_MCWDT_SetSleepDeepPause(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
665 void Cy_MCWDT_SetDebugRun(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
666 uint32_t Cy_MCWDT_GetDebugRun(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
667 void Cy_MCWDT_SetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
668 void Cy_MCWDT_SetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
669 void Cy_MCWDT_SetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
670 uint16_t Cy_MCWDT_GetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
671 uint16_t Cy_MCWDT_GetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
672 void Cy_MCWDT_WaitForCounterReset(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
673 void Cy_MCWDT_ClearWatchdog(MCWDT_Type *base, uint32_t counters);
674 uint16_t Cy_MCWDT_GetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
675
676 #endif
677
678
679 /*******************************************************************************
680 * Function Name: Cy_MCWDT_Enable
681 ****************************************************************************//**
682 *
683 * Enables all specified counters.
684 *
685 * \param base
686 * The base pointer to a structure that describes registers.
687 *
688 * \param counters
689 * OR of all counters to enable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
690 * CY_MCWDT_CTR2 macros.
691 *
692 * \param waitUs
693 * The function waits for some delay in microseconds before returning,
694 * because the counter begins counting after two lf_clk cycles pass.
695 * The recommended value is 93 us.
696 * \note
697 * Setting this parameter to a zero means No wait. In this case, it is
698 * the user's responsibility to check whether the selected counters were enabled
699 * immediately after the function call. This can be done by the
700 * Cy_MCWDT_GetEnabledStatus() API.
701 *
702 *******************************************************************************/
Cy_MCWDT_Enable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)703 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
704 {
705 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
706
707 if (0UL != (counters & CY_MCWDT_CTR0))
708 {
709 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0) |= MCWDT_CTR_CTL_ENABLE_Msk;
710 }
711 if (0UL != (counters & CY_MCWDT_CTR1))
712 {
713 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1) |= MCWDT_CTR_CTL_ENABLE_Msk;
714 }
715 if (0UL != (counters & CY_MCWDT_CTR2))
716 {
717 MCWDT_CTR2_CTL(base) |= MCWDT_CTR2_CTL_ENABLE_Msk;
718 }
719
720 #else
721 uint32_t enableCounters;
722
723 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
724
725 /* Extract particular counters for enable */
726 enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
727 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
728 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
729
730 MCWDT_CTL(base) |= enableCounters;
731 #endif
732
733 Cy_SysLib_DelayUs(waitUs);
734 }
735
736
737 /*******************************************************************************
738 * Function Name: Cy_MCWDT_Disable
739 ****************************************************************************//**
740 *
741 * Disables all specified counters.
742 *
743 * \param base
744 * The base pointer to a structure describing registers.
745 *
746 * \param counters
747 * OR of all counters to disable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
748 * CY_MCWDT_CTR2 macros.
749 *
750 * \param waitUs
751 * The function waits for some delay in microseconds before returning,
752 * because the counter stops counting after two lf_clk cycles pass.
753 * The recommended value is 93 us.
754 * \note
755 * Setting this parameter to a zero means No wait. In this case, it is
756 * the user's responsibility to check whether the selected counters were disabled
757 * immediately after the function call. This can be done by the
758 * Cy_MCWDT_GetEnabledStatus() API.
759 *
760 *******************************************************************************/
Cy_MCWDT_Disable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)761 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
762 {
763 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
764
765 if (0UL != (counters & CY_MCWDT_CTR0))
766 {
767 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0) &= (uint32_t) ~MCWDT_CTR_CTL_ENABLE_Msk;
768 }
769 if (0UL != (counters & CY_MCWDT_CTR1))
770 {
771 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1) &= (uint32_t) ~MCWDT_CTR_CTL_ENABLE_Msk;
772 }
773 if (0UL != (counters & CY_MCWDT_CTR2))
774 {
775 MCWDT_CTR2_CTL(base) &= (uint32_t) ~MCWDT_CTR2_CTL_ENABLE_Msk;
776 }
777 #else
778 uint32_t disableCounters;
779
780 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
781
782 /* Extract particular counters for disable */
783 disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
784 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
785 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
786
787 MCWDT_CTL(base) &= ~disableCounters;
788 #endif
789
790 Cy_SysLib_DelayUs(waitUs);
791 }
792
793
794 /*******************************************************************************
795 * Function Name: Cy_MCWDT_GetEnabledStatus
796 ****************************************************************************//**
797 *
798 * Reports the enabled status of the specified counter.
799 *
800 * \param base
801 * The base pointer to a structure that describes registers.
802 *
803 * \param counter
804 * The number of the MCWDT counter. The valid range is [0-2].
805 *
806 * \return
807 * The status of the MCWDT counter: 0 = disabled, 1 = enabled.
808 *
809 *******************************************************************************/
Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)810 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
811 {
812 uint32_t status = 0u;
813
814 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
815
816 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
817 switch (counter)
818 {
819 case CY_MCWDT_COUNTER0:
820 status = _FLD2VAL(MCWDT_CTR_CTL_ENABLE, MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0));
821 break;
822 case CY_MCWDT_COUNTER1:
823 status = _FLD2VAL(MCWDT_CTR_CTL_ENABLE, MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1));
824 break;
825 case CY_MCWDT_COUNTER2:
826 status = _FLD2VAL(MCWDT_CTR2_CTL_ENABLE, MCWDT_CTR2_CTL(base));
827 break;
828 default:
829 CY_ASSERT(0u != 0u);
830 break;
831 }
832 #else
833 switch (counter)
834 {
835 case CY_MCWDT_COUNTER0:
836 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0, MCWDT_CTL(base));
837 break;
838 case CY_MCWDT_COUNTER1:
839 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1, MCWDT_CTL(base));
840 break;
841 case CY_MCWDT_COUNTER2:
842 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2, MCWDT_CTL(base));
843 break;
844
845 default:
846 CY_ASSERT(0u != 0u);
847 break;
848 }
849 #endif
850
851 return (status);
852 }
853
854
855 /*******************************************************************************
856 * Function Name: Cy_MCWDT_Lock
857 ****************************************************************************//**
858 *
859 * Locks out configuration changes to all MCWDT registers.
860 *
861 * \param base
862 * The base pointer to a structure that describes registers.
863 *
864 *******************************************************************************/
Cy_MCWDT_Lock(MCWDT_STRUCT_Type * base)865 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base)
866 {
867 uint32_t interruptState;
868
869 interruptState = Cy_SysLib_EnterCriticalSection();
870 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
871 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, CY_MCWDT_LOCK_SET01);
872 #else
873 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_SET01);
874 #endif
875
876 Cy_SysLib_ExitCriticalSection(interruptState);
877 }
878
879
880 /*******************************************************************************
881 * Function Name: Cy_MCWDT_Unlock
882 ****************************************************************************//**
883 *
884 * Unlocks the MCWDT configuration registers.
885 *
886 * \param base
887 * The base pointer to a structure that describes registers.
888 *
889 *******************************************************************************/
Cy_MCWDT_Unlock(MCWDT_STRUCT_Type * base)890 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base)
891 {
892 uint32_t interruptState;
893
894 interruptState = Cy_SysLib_EnterCriticalSection();
895 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
896 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
897 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
898 #else
899 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
900 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
901 #endif
902 Cy_SysLib_ExitCriticalSection(interruptState);
903 }
904
905
906 /*******************************************************************************
907 * Function Name: Cy_MCWDT_GetLockStatus
908 ****************************************************************************//**
909 *
910 * Reports the locked/unlocked state of the MCWDT.
911 *
912 * \param base
913 * The base pointer to a structure that describes registers.
914 *
915 * \return
916 * The state of the MCWDT counter: 0 = unlocked, 1 = locked.
917 *
918 *******************************************************************************/
Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const * base)919 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
920 {
921 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
922 return ((0UL !=_FLD2VAL(MCWDT_LOCK_MCWDT_LOCK, MCWDT_LOCK(base))) ? 1UL : 0UL);
923 #else
924 return ((0UL != (MCWDT_LOCK(base) & MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk)) ? 1UL : 0UL);
925 #endif
926 }
927
928
929 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) || defined (CY_IP_MXS22SRSS)
930
931 /*******************************************************************************
932 * Function Name: Cy_MCWDT_SetMode
933 ****************************************************************************//**
934 *
935 * Sets the mode of the specified counter.
936 *
937 * \param base
938 * The base pointer to a structure that describes registers.
939 *
940 * \param counter
941 * The number of the WDT counter. The valid range is [0-2].
942 *
943 * \param mode
944 * The mode of operation for the counter. See enum typedef cy_en_mcwdtmode_t.
945 *
946 * \note
947 * The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
948 *
949 * \note
950 * This API must not be called while the counters are running.
951 * Prior to calling this API, the counter must be disabled.
952 *
953 * \note
954 * This API is available for CAT1A, CAT1B and CAT1D devices.
955 *
956 *******************************************************************************/
Cy_MCWDT_SetMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdtmode_t mode)957 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode)
958 {
959 uint32_t mask, shift;
960
961 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
962 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
963
964 shift = CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter);
965 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
966 mask = mask << shift;
967
968 MCWDT_CONFIG(base) = (MCWDT_CONFIG(base) & ~mask) | ((uint32_t) mode << shift);
969 }
970
971
972 /*******************************************************************************
973 * Function Name: Cy_MCWDT_GetMode
974 ****************************************************************************//**
975 *
976 * Reports the mode of the specified counter.
977 *
978 * \param base
979 * The base pointer to a structure that describes registers.
980 *
981 * \param counter
982 * The number of the WDT counter. The valid range is [0-2].
983 *
984 * \return
985 * The current mode of the counter. See enum typedef cy_en_mcwdtmode_t.
986 *
987 * \note
988 * This API is available for CAT1A, CAT1B and CAT1D devices.
989 *
990 *******************************************************************************/
Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)991 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
992 {
993 uint32_t mode, mask;
994
995 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
996
997 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
998 mode = (MCWDT_CONFIG(base) >> (CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter))) & mask;
999
1000 return ((cy_en_mcwdtmode_t) mode);
1001 }
1002
1003
1004 /*******************************************************************************
1005 * Function Name: Cy_MCWDT_SetClearOnMatch
1006 ****************************************************************************//**
1007 *
1008 * Sets the Clear on match option for the specified counter.
1009 *
1010 * \param base
1011 * The base pointer to a structure that describes registers.
1012 *
1013 * \param counter
1014 * The number of the WDT counter. The valid range is [0-1].
1015 *
1016 * \note
1017 * The match values are not supported by Counter 2.
1018 *
1019 * \param enable
1020 * Set 0 to disable; 1 to enable.
1021 *
1022 * \note
1023 * This API must not be called while the counters are running.
1024 * Prior to calling this API, the counter must be disabled.
1025 *
1026 * \note
1027 * This API is available for CAT1A, CAT1B and CAT1D devices.
1028 *
1029 *******************************************************************************/
Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)1030 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
1031 {
1032 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1033 CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
1034
1035 if (CY_MCWDT_COUNTER0 == counter)
1036 {
1037 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
1038 }
1039 else
1040 {
1041 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable);
1042 }
1043 }
1044
1045
1046 /*******************************************************************************
1047 * Function Name: Cy_MCWDT_GetClearOnMatch
1048 ****************************************************************************//**
1049 *
1050 * Reports the Clear on match setting for the specified counter.
1051 *
1052 * \param base
1053 * The base pointer to a structure that describes registers.
1054 *
1055 * \param counter
1056 * The number of the WDT counter. The valid range is [0-1].
1057 *
1058 * \return
1059 * The Clear on match status: 1 = enabled, 0 = disabled.
1060 *
1061 * \note
1062 * The match value is not supported by Counter 2.
1063 *
1064 * \note
1065 * This API is available for CAT1A, CAT1B and CAT1D devices.
1066 *
1067 *******************************************************************************/
Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1068 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1069 {
1070 uint32_t getClear;
1071
1072 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1073
1074 if (CY_MCWDT_COUNTER0 == counter)
1075 {
1076 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, MCWDT_CONFIG(base));
1077 }
1078 else
1079 {
1080 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, MCWDT_CONFIG(base));
1081 }
1082
1083 return (getClear);
1084 }
1085
1086
1087 /*******************************************************************************
1088 * Function Name: Cy_MCWDT_SetCascade
1089 ****************************************************************************//**
1090 *
1091 * Sets all the counter cascade options.
1092 *
1093 * \param base
1094 * The base pointer to a structure that describes registers.
1095 *
1096 * \param cascade
1097 * Sets or clears each of the cascade options.
1098 *
1099 * \note
1100 * This API must not be called when the counters are running.
1101 * Prior to calling this API, the counter must be disabled.
1102 *
1103 * \note
1104 * This API is available for CAT1A, CAT1B and CAT1D devices.
1105 *
1106 *******************************************************************************/
Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t cascade)1107 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
1108 {
1109 CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
1110
1111 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
1112 (uint32_t) cascade);
1113 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
1114 ((uint32_t) cascade >> 1u));
1115 }
1116
1117 /*******************************************************************************
1118 * Function Name: Cy_MCWDT_GetCascade
1119 ****************************************************************************//**
1120 *
1121 * Reports all the counter cascade option settings.
1122 *
1123 * \param base
1124 * The base pointer to a structure that describes registers.
1125 *
1126 * \return
1127 * The current cascade option values.
1128 *
1129 * \note
1130 * This API is available for CAT1A, CAT1B and CAT1D devices.
1131 *
1132 *******************************************************************************/
Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const * base)1133 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base)
1134 {
1135 uint32_t cascade;
1136
1137 cascade = (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, MCWDT_CONFIG(base)) << 1u) |
1138 _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, MCWDT_CONFIG(base));
1139
1140 return ((cy_en_mcwdtcascade_t) cascade);
1141 }
1142
1143 /*******************************************************************************
1144 * Function Name: Cy_MCWDT_SetMatch
1145 ****************************************************************************//**
1146 *
1147 * Sets the match comparison value for the specified counter (0 or 1).
1148 *
1149 * \param base
1150 * The base pointer to a structure that describes registers.
1151 *
1152 * \param counter
1153 * The number of the WDT counter. The valid range is [0-1].
1154 *
1155 * \param match
1156 * The value to match against the counter.
1157 * The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
1158 * and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
1159 *
1160 * \note
1161 * The match value is not supported by Counter 2.
1162 *
1163 * \note
1164 * Action on match is taken on the next increment after the counter value
1165 * equal to match value.
1166 *
1167 * \param waitUs
1168 * The function waits for some delay in microseconds before returning,
1169 * because the match affects after two lf_clk cycles pass. The recommended
1170 * value is 93 us.
1171 * \note
1172 * Setting this parameter to a zero means No wait. This must be taken
1173 * into account when changing the match values on the running counters.
1174 *
1175 * \note
1176 * This API is available for CAT1A, CAT1B and CAT1D devices.
1177 *
1178 *******************************************************************************/
Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t match,uint16_t waitUs)1179 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
1180 {
1181 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1182 CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? \
1183 ((MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) : \
1184 ((MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U), \
1185 match));
1186
1187 MCWDT_MATCH(base) = (counter == CY_MCWDT_COUNTER0) ?
1188 _CLR_SET_FLD32U(MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
1189 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
1190 _CLR_SET_FLD32U(MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1,
1191 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk));
1192
1193 Cy_SysLib_DelayUs(waitUs);
1194 }
1195
1196
1197 /*******************************************************************************
1198 * Function Name: Cy_MCWDT_GetMatch
1199 ****************************************************************************//**
1200 *
1201 * Reports the match comparison value for the specified counter (0 or 1).
1202 *
1203 * \param base
1204 * The base pointer to a structure that describes registers.
1205 *
1206 * \param counter
1207 * The number of the WDT counter. The valid range is [0-1].
1208 *
1209 * \note
1210 * The match values are not supported by Counter 2.
1211 *
1212 * \return
1213 * A 16-bit match value.
1214 *
1215 * \note
1216 * This API is available for CAT1A, CAT1B and CAT1D devices.
1217 *
1218 *******************************************************************************/
Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1219 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1220 {
1221 uint32_t match;
1222
1223 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1224
1225 match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, MCWDT_MATCH(base)) :
1226 _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, MCWDT_MATCH(base));
1227
1228 return (match);
1229 }
1230 #endif /* (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) || defined (CY_IP_MXS22SRSS) */
1231
1232 /*******************************************************************************
1233 * Function Name: Cy_MCWDT_SetToggleBit
1234 ****************************************************************************//**
1235 *
1236 * Sets a bit in Counter 2 to monitor for a toggle.
1237 *
1238 * \param base
1239 * The base pointer to a structure that describes registers.
1240 *
1241 * \param bit
1242 * The Counter 2 bit is set to monitor for a toggle. The valid range [0-31].
1243 *
1244 * \note
1245 * This API must not be called when counters are running.
1246 * Prior to calling this API, the counter must be disabled.
1247 *
1248 *******************************************************************************/
Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type * base,uint32_t bit)1249 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
1250 {
1251 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
1252 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
1253 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_BITS, bit);
1254 #else
1255 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
1256 #endif
1257 }
1258
1259
1260 /*******************************************************************************
1261 * Function Name: Cy_MCWDT_GetToggleBit
1262 ****************************************************************************//**
1263 *
1264 * Reports which bit in Counter 2 is monitored for a toggle.
1265 *
1266 * \param base
1267 * The base pointer to a structure that describes registers.
1268 *
1269 * \return
1270 * The bit that is monitored (range 0 to 31).
1271 *
1272 *******************************************************************************/
Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const * base)1273 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base)
1274 {
1275 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
1276 return (uint32_t)(_FLD2VAL(MCWDT_CTR2_CONFIG_BITS, MCWDT_CTR2_CONFIG(base)));
1277 #else
1278 return (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, MCWDT_CONFIG(base)));
1279 #endif
1280 }
1281
1282
1283 /*******************************************************************************
1284 * Function Name: Cy_MCWDT_GetCount
1285 ****************************************************************************//**
1286 *
1287 * Reports the current counter value of the specified counter.
1288 *
1289 * \param base
1290 * The base pointer to a structure that describes registers.
1291 *
1292 * \param counter
1293 * The number of the WDT counter. The valid range is [0-2].
1294 *
1295 * \return
1296 * A live counter value. Counters 0 and 1 are 16-bit counters and Counter 2 is
1297 * a 32-bit counter.
1298 *
1299 *******************************************************************************/
Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1300 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1301 {
1302 uint32_t countVal = 0u;
1303
1304 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1305
1306 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
1307 switch (counter)
1308 {
1309 case CY_MCWDT_COUNTER0:
1310 countVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_CNT_CNT, MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER0)));
1311 break;
1312 case CY_MCWDT_COUNTER1:
1313 countVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_CNT_CNT, MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER1)));
1314 break;
1315 case CY_MCWDT_COUNTER2:
1316 countVal = (_FLD2VAL(MCWDT_CTR2_CNT_CNT2, MCWDT_CTR2_CNT(base)));
1317 break;
1318 default:
1319 CY_ASSERT(0u != 0u);
1320 break;
1321 }
1322
1323 #else
1324
1325 switch (counter)
1326 {
1327 case CY_MCWDT_COUNTER0:
1328 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0, MCWDT_CNTLOW(base));
1329 break;
1330 case CY_MCWDT_COUNTER1:
1331 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1, MCWDT_CNTLOW(base));
1332 break;
1333 case CY_MCWDT_COUNTER2:
1334 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2, MCWDT_CNTHIGH(base));
1335 break;
1336 default:
1337 CY_ASSERT(0u != 0u);
1338 break;
1339 }
1340 #endif
1341
1342 return (countVal);
1343 }
1344
1345
1346 /*******************************************************************************
1347 * Function Name: Cy_MCWDT_ResetCounters
1348 ****************************************************************************//**
1349 *
1350 * Resets all specified counters.
1351 *
1352 * \param base
1353 * The base pointer to a structure that describes registers.
1354 *
1355 * \param counters
1356 * OR of all counters to reset. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1357 * CY_MCWDT_CTR2 macros.
1358 *
1359 * \param waitUs
1360 * The function waits for some delay in microseconds before returning, because
1361 * a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
1362 * \note This function resets the counters two times to prevent the case when
1363 * the Counter 1 is not reset when the counters are cascaded. The delay waitUs
1364 * must be greater than 100 us when the counters are cascaded.
1365 * The total delay is greater than 2*waitUs because the function has
1366 * the delay after the first reset.
1367 * \note
1368 * Setting this parameter to a zero means No wait. In this case, it is the
1369 * user's responsibility to check whether the selected counters were reset
1370 * immediately after the function call. This can be done by the
1371 * Cy_MCWDT_GetCount() API.
1372 *
1373 * \note
1374 * For CAT1C devices, only CY_MCWDT_CTR0 and CY_MCWDT_CTR1 can be Reset.
1375 *
1376 *******************************************************************************/
Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)1377 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
1378 {
1379 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3))
1380 if (0UL != (counters & CY_MCWDT_CTR0))
1381 {
1382 MCWDT_SERVICE(base) |= MCWDT_SERVICE_CTR0_SERVICE_Msk;
1383 }
1384 if (0UL != (counters & CY_MCWDT_CTR1))
1385 {
1386 MCWDT_SERVICE(base) |= MCWDT_SERVICE_CTR1_SERVICE_Msk;
1387 }
1388
1389 #else
1390
1391 uint32_t resetCounters;
1392
1393 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1394
1395 /* Extract particular counters for reset */
1396 resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
1397 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
1398 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
1399
1400 MCWDT_CTL(base) |= resetCounters;
1401
1402 Cy_SysLib_DelayUs(waitUs);
1403
1404 MCWDT_CTL(base) |= resetCounters;
1405 #endif
1406
1407 Cy_SysLib_DelayUs(waitUs);
1408 }
1409
1410
1411 /*******************************************************************************
1412 * Function Name: Cy_MCWDT_GetInterruptStatus
1413 ****************************************************************************//**
1414 *
1415 * Reports the state of all MCWDT interrupts.
1416 *
1417 * \param base
1418 * The base pointer to a structure that describes registers.
1419 *
1420 * \return
1421 * The OR'd state of the interrupts. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1422 * CY_MCWDT_CTR2 macros.
1423 *
1424 *******************************************************************************/
Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const * base)1425 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base)
1426 {
1427 return (MCWDT_INTR(base));
1428 }
1429
1430
1431 /*******************************************************************************
1432 * Function Name: Cy_MCWDT_ClearInterrupt
1433 ****************************************************************************//**
1434 *
1435 * Clears all specified MCWDT interrupts.
1436 *
1437 * All the WDT interrupts must be cleared by the firmware; otherwise
1438 * interrupts are generated continuously.
1439 *
1440 * \param base
1441 * The base pointer to a structure describes registers.
1442 *
1443 * \param counters
1444 * OR of all interrupt sources to clear. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1445 * CY_MCWDT_CTR2 macros.
1446 *
1447 *******************************************************************************/
Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1448 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1449 {
1450 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1451
1452 MCWDT_INTR(base) = counters;
1453 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1454 (void) MCWDT_INTR(base);
1455 }
1456
1457
1458 /*******************************************************************************
1459 * Function Name: Cy_MCWDT_SetInterrupt
1460 ****************************************************************************//**
1461 *
1462 * Sets MCWDT interrupt sources in the interrupt request register.
1463 *
1464 * \param base
1465 * The base pointer to a structure that describes registers.
1466 *
1467 * \param counters
1468 * OR of all interrupt sources to set. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1469 * CY_MCWDT_CTR2 macros.
1470 *
1471 *******************************************************************************/
Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1472 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1473 {
1474 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1475
1476 MCWDT_INTR_SET(base) = counters;
1477 }
1478
1479
1480 /*******************************************************************************
1481 * Function Name: Cy_MCWDT_GetInterruptMask
1482 ****************************************************************************//**
1483 *
1484 * Returns the CWDT interrupt mask register. This register specifies which bits
1485 * from the MCWDT interrupt request register will trigger an interrupt event.
1486 *
1487 * \param base
1488 * The base pointer to a structure that describes registers.
1489 *
1490 * \return
1491 * The OR'd state of the interrupt masks. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1492 * CY_MCWDT_CTR2 macros.
1493 *
1494 *******************************************************************************/
Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const * base)1495 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base)
1496 {
1497 return (MCWDT_INTR_MASK(base));
1498 }
1499
1500
1501 /*******************************************************************************
1502 * Function Name: Cy_MCWDT_SetInterruptMask
1503 ****************************************************************************//**
1504 *
1505 * Writes MCWDT interrupt mask register. This register configures which bits
1506 * from MCWDT interrupt request register will trigger an interrupt event.
1507 *
1508 * \param base
1509 * The base pointer to a structure that describes registers.
1510 *
1511 * \param counters
1512 * OR of all interrupt masks to set. See \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1513 * CY_MCWDT_CTR2 macros.
1514 *
1515 *******************************************************************************/
Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type * base,uint32_t counters)1516 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
1517 {
1518 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1519
1520 MCWDT_INTR_MASK(base) = counters;
1521 }
1522
1523
1524 /*******************************************************************************
1525 * Function Name: Cy_MCWDT_GetInterruptStatusMasked
1526 ****************************************************************************//**
1527 *
1528 * Returns the MCWDT interrupt masked request register. This register contains
1529 * the logical AND of corresponding bits from the MCWDT interrupt request and
1530 * mask registers.
1531 * In the interrupt service routine, this function identifies which of the
1532 * enabled MCWDT interrupt sources caused an interrupt event.
1533 *
1534 * \param base
1535 * The base pointer to a structure that describes registers.
1536 *
1537 * \return
1538 * The current status of enabled MCWDT interrupt sources. See
1539 * the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and CY_MCWDT_CTR2 macros.
1540 *
1541 *******************************************************************************/
Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const * base)1542 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base)
1543 {
1544 return (MCWDT_INTR_MASKED(base));
1545 }
1546
1547 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
1548 /*******************************************************************************
1549 * Function Name: Cy_MCWDT_SetLowerLimit
1550 ****************************************************************************//**
1551 *
1552 * Sets the lower limit value for the specified counter (0 or 1).
1553 *
1554 * \param base
1555 * The base pointer to a structure that describes registers.
1556 *
1557 * \param counter
1558 * The number of the WDT counter. The valid range is [0-1].
1559 *
1560 * \param lowerLimit
1561 * The value to be written in the lower limit register
1562 * The valid range is [0-65535] for c0
1563 * and [1-65535] for c1.
1564 *
1565 * \note
1566 * The lower limit mode is not supported by Counter 2.
1567 *
1568 * \param waitUs
1569 * The function waits for some delay in microseconds before returning,
1570 * because the lower limit register write affects after two lf_clk cycles pass.
1571 * The recommended value is 93 us.
1572 * \note
1573 * Setting this parameter to a zero means No wait. This must be taken
1574 * into account when changing the lower limit register values.
1575 *
1576 * \note
1577 * This API is available for CAT1B devices.
1578 *
1579 *******************************************************************************/
Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,uint32_t lowerLimit,uint16_t waitUs)1580 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs)
1581 {
1582 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1583
1584 MCWDT_LOWER_LIMIT(base) = (counter == CY_MCWDT_LOWER_LIMIT0) ?
1585 _CLR_SET_FLD32U(MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0,
1586 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk)) :
1587 _CLR_SET_FLD32U(MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1,
1588 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk));
1589
1590 Cy_SysLib_DelayUs(waitUs);
1591 }
1592
1593 /*******************************************************************************
1594 * Function Name: Cy_MCWDT_GetLowerLimit
1595 ****************************************************************************//**
1596 *
1597 * Reports the Lower Limit value of the specified counter.
1598 *
1599 * \param base
1600 * The base pointer to a structure that describes registers.
1601 *
1602 * \param counter
1603 * The number of the WDT counter. The valid range is [0-1].
1604 *
1605 * \return
1606 * A Lower Limit value. Counters 0 and 1 are 16-bit counters.
1607 *
1608 * \note
1609 * This API is available for CAT1B devices.
1610 *
1611 *******************************************************************************/
Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1612 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1613 {
1614 uint32_t countVal = 0u;
1615
1616 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1617
1618 switch (counter)
1619 {
1620 case CY_MCWDT_LOWER_LIMIT0:
1621 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0, MCWDT_LOWER_LIMIT(base));
1622 break;
1623 case CY_MCWDT_LOWER_LIMIT1:
1624 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1, MCWDT_LOWER_LIMIT(base));
1625 break;
1626 default:
1627 CY_ASSERT(0u != 0u);
1628 break;
1629 }
1630
1631 return (countVal);
1632 }
1633
1634 /*******************************************************************************
1635 * Function Name: Cy_MCWDT_SetLowerLimitMode
1636 ****************************************************************************//**
1637 *
1638 * Sets the lower limit mode option for the specified counter.
1639 *
1640 * \param base
1641 * The base pointer to a structure that describes registers.
1642 *
1643 * \param counter
1644 * The number of the WDT counter. The valid range is [0-1].
1645 *
1646 * \note
1647 * The lower limit mode is not supported by Counter 2.
1648 *
1649 * \param mode
1650 * Set 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset
1651 *
1652 * \note
1653 * This API must not be called while the counters are running.
1654 * Prior to calling this API, the counter must be disabled.
1655 * This API is available for CAT1B devices.
1656 *
1657 *******************************************************************************/
Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,cy_en_mcwdtlowerlimitmode_t mode)1658 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode)
1659 {
1660 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1661 CY_ASSERT_L2(CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode));
1662
1663 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1664 {
1665 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, mode);
1666 }
1667 else
1668 {
1669 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, mode);
1670 }
1671 }
1672
1673 /*******************************************************************************
1674 * Function Name: Cy_MCWDT_GetLowerLimitMode
1675 ****************************************************************************//**
1676 *
1677 * Reports the lower limit mode of the specified counter.
1678 *
1679 * \param base
1680 * The base pointer to a structure that describes registers.
1681 *
1682 * \param counter
1683 * The number of the WDT counter. The valid range is [0-1].
1684 *
1685 * \return
1686 * The current lower limit mode of the counter. See enum typedef cy_en_mcwdtlowerlimitmode_t.
1687 *
1688 * \note
1689 * This API is available for CAT1B devices.
1690 *
1691 *******************************************************************************/
Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1692 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1693 {
1694 uint32_t getLowerLimitMode;
1695
1696 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1697
1698 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1699 {
1700 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, MCWDT_CONFIG(base));
1701 }
1702 else
1703 {
1704 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, MCWDT_CONFIG(base));
1705 }
1706
1707 return (cy_en_mcwdtlowerlimitmode_t)getLowerLimitMode;
1708
1709 }
1710
1711 /*******************************************************************************
1712 * Function Name: Cy_MCWDT_GetLowerLimitCascaded
1713 ****************************************************************************//**
1714 *
1715 * Gets lower limit registers cascaded value.
1716 *
1717 * \param base
1718 * The base pointer to a structure that describes registers.
1719 *
1720 * \note
1721 * The lower limit mode is not supported by Counter 2.
1722 *
1723 * \return
1724 * A 32-bit lower limit register value.
1725 *
1726 * \note
1727 * This API is available for CAT1B devices.
1728 *
1729 *******************************************************************************/
Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const * base)1730 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base)
1731 {
1732 return (uint32_t)(MCWDT_LOWER_LIMIT(base));
1733 }
1734 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS ,CY_IP_MXS22SRSS*/
1735
1736 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1737
1738 /*******************************************************************************
1739 * Function Name: Cy_MCWDT_SetCascadeCarryOutRollOver
1740 ****************************************************************************//**
1741 *
1742 * Enables the Rollover mode for carryout.
1743 *
1744 * \param base
1745 * The base pointer to a structure that describes registers.
1746 *
1747 * \param counter
1748 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1749 *
1750 * \param carryoutconfig
1751 * For CY_MCWDT_CASCADE_C0C1:
1752 * FALSE: carry out on counter 0 match
1753 * TRUE: carry out on counter 0 rollover.
1754 * For CY_MCWDT_CASCADE_C1C2:
1755 * FALSE: carry out on counter 1 match
1756 * TRUE: carry out on counter 1 rollover.
1757 *
1758 * \note
1759 * This API is available for CAT1B devices.
1760 *
1761 *******************************************************************************/
Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,bool carryoutconfig)1762 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool carryoutconfig)
1763 {
1764 CY_ASSERT_L3(CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(counter));
1765
1766 if (CY_MCWDT_CASCADE_C0C1 == counter)
1767 {
1768 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, carryoutconfig);
1769 }
1770 else
1771 {
1772 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, carryoutconfig);
1773 }
1774 }
1775
1776 /*******************************************************************************
1777 * Function Name: Cy_MCWDT_GetCascadeCarryOutModeRollOver
1778 ****************************************************************************//**
1779 *
1780 * Checks if Rollover mode enabled for carryout or not.
1781 *
1782 * \param base
1783 * The base pointer to a structure that describes registers.
1784 *
1785 * \param counter
1786 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1787 *
1788 * \return
1789 * True : Rollover Enabled
1790 * False : Rollover Disabled
1791 *
1792 * \note
1793 * This API is available for CAT1B devices.
1794 *
1795 *******************************************************************************/
Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1796 __STATIC_INLINE bool Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1797 {
1798 bool countVal = false;
1799
1800 CY_ASSERT_L3(CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(counter));
1801
1802 switch (counter)
1803 {
1804 case CY_MCWDT_CASCADE_C0C1:
1805 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, MCWDT_CONFIG(base));
1806 break;
1807 case CY_MCWDT_CASCADE_C1C2:
1808 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, MCWDT_CONFIG(base));
1809 break;
1810 default:
1811 CY_ASSERT(0u != 0u);
1812 break;
1813 }
1814
1815 return (countVal);
1816 }
1817
1818 /*******************************************************************************
1819 * Function Name: Cy_MCWDT_SetCascadeMatchCombined
1820 ****************************************************************************//**
1821 *
1822 * Sets the match to combined cascade counters.
1823 *
1824 * \param base
1825 * The base pointer to a structure that describes registers.
1826 *
1827 * \param counter
1828 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1829 *
1830 * \param matchconfig
1831 * For CY_MCWDT_CASCADE_C0C1:
1832 * FALSE: Match based on counter 1 alone
1833 * TRUE: Match based on counter 1 and counter 0 matching simultaneously
1834 * For CY_MCWDT_CASCADE_C1C2:
1835 * FALSE: Match based on counter 2 alone
1836 * TRUE: Match based on counter 2 and counter 1 matching simultaneously
1837 *
1838 * \note
1839 * This API is available for CAT1B devices.
1840 *
1841 *******************************************************************************/
Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,bool matchconfig)1842 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool matchconfig)
1843 {
1844 if (CY_MCWDT_CASCADE_C0C1 == counter)
1845 {
1846 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, matchconfig);
1847 }
1848 else
1849 {
1850 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, matchconfig);
1851 }
1852 }
1853
1854 /*******************************************************************************
1855 * Function Name: Cy_MCWDT_GetCascadeMatchModeCombined
1856 ****************************************************************************//**
1857 *
1858 * Reports if match is enabled with combined cascade counters or not.
1859 *
1860 * \param base
1861 * The base pointer to a structure that describes registers.
1862 *
1863 * \param counter
1864 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1865 *
1866 * \return
1867 * True : Combined match is enabled
1868 * False : Combined match is disabled.
1869 *
1870 * \note
1871 * This API is available for CAT1B devices.
1872 *
1873 *******************************************************************************/
Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1874 __STATIC_INLINE bool Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1875 {
1876 bool countVal = false;
1877
1878 switch (counter)
1879 {
1880 case CY_MCWDT_CASCADE_C0C1:
1881 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, MCWDT_CONFIG(base));
1882 break;
1883 case CY_MCWDT_CASCADE_C1C2:
1884 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, MCWDT_CONFIG(base));
1885 break;
1886 default:
1887 CY_ASSERT(0u != 0u);
1888 break;
1889 }
1890
1891 return (countVal);
1892 }
1893
1894 #endif /* CY_IP_MXS40SSRSS,CY_IP_MXS22SRSS */
1895
1896
1897 /** \} group_mcwdt_functions */
1898
1899 #endif /* CY_IP_MXS40SRSS_MCWDT, CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
1900
1901 #if defined(__cplusplus)
1902 }
1903 #endif
1904
1905 #endif /* CY_MCWDT_H */
1906
1907 /** \} group_mcwdt */
1908
1909 /* [] END OF FILE */
1910
