1 /***************************************************************************/ /** 2 * @file rsi_qspi_proto.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 // Include Files 31 32 #include "rsi_ccp_common.h" 33 #include "base_types.h" 34 35 #ifndef QSPI_PROTO_H 36 #define QSPI_PROTO_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 // GPIO register bit position related defines 43 #define GPIO_0_TO_5 0 44 #define GPIO_6_TO_11 1 45 #define GPIO_46_TO_51 2 46 #define GPIO_52_TO_57 3 47 #define GPIO_58_TO_63 4 48 // NWP OCTA/DUAL combinations 49 #define GPIO_0_AND_58 5 50 #define GPIO_6_AND_58 6 51 #define GPIO_46_AND_58 7 52 // M4 OCTA/DUAL combinations 53 #define GPIO_0_AND_52 8 54 #define GPIO_6_AND_52 9 55 #define GPIO_46_AND_52 10 56 #define NOT_USING 11 // Not applicable 57 #define GPIO_58_AND_52 12 58 #define GPIO_DDR_PADS 13 59 60 #define M4SS_PAD_CONFIG_REG(x) *(volatile uint32_t *)(0x46004000 + 4 * (x)) // REN enable bit(this should be enable) 61 #define M4_DDR_PAD_CONFIG(x) *(volatile uint32_t *)(0x46006000 + ((x)*4)) 62 // Pad config(P2 P1) 63 // 00 - Hi-Z, 01 - Pullup, 10 - PullDown, 11 - Repeater 64 #define PAD_CONFIG_P2 BIT(7) 65 #define PAD_CONFIG_P1 BIT(6) 66 67 #define PADSELECTION \ 68 (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS 69 // Note BIT(0) to BIT(7) are reserved for channel no 70 #define DEFAULT_DESC_MODE BIT(8) 71 #define USE_UDMA_MODE BIT(9) 72 73 typedef enum qspi_mode_e { NONE = 0, READ_MODE, WRITE_MODE } qspi_mode_t; 74 75 // Structure to qspi standalone encrypt/decrypt configs 76 typedef struct qspi_standalone_config_s { 77 uint8_t aes_mode; // AES mode 78 bool encrypt; // 0 = Encrypt, 1 = Decrypt 79 bool kh_enable; // 1 = Pick the key from keyholder, 0 = pass the key 80 uint32_t *iv; // flash offset where data stored 81 uint32_t *key1; // Pass key1 if kh_enable = 0 82 uint32_t *key2; // Pass key1 if kh_enable = 0 and 32 byte key 83 uint32_t key_len; // Key len i.e 16 or 32 bytes 84 uint32_t flip_data; // writing 1 to this Flips the 32-bit endian for data in standalone mode 85 } qspi_standalone_config_t; 86 87 extern qspi_mode_t qspi_mode_g; 88 89 typedef struct qspi_reg_s qspi_reg_t; 90 // This structure members are used to configure qspi 91 typedef struct spi_config_1_s { 92 // QSPI operation modes, all modes are single, dual or quad 93 94 unsigned int inst_mode : 2; // instruction will be sent in this mode 95 unsigned int addr_mode : 2; // addr will be sent in this mode 96 unsigned int data_mode : 2; // data will be sent/received in this mode 97 unsigned int dummy_mode : 2; // dummy bytes will be sent/received in this mode 98 unsigned int extra_byte_mode : 2; // extra bytes will be sent in this mode 99 // SPI mode 100 #define SINGLE_MODE 0 101 // dual mode 102 #define DUAL_MODE 1 103 // quad mode 104 #define QUAD_MODE 2 105 #define OCTA_MODE 3 106 107 unsigned int prefetch_en : 1; // prefetch enable 108 // prefetch will be enabled 109 #define EN_PREFETCH 1 110 // prefetch will be disabled 111 #define DIS_PREFETCH 0 112 113 unsigned int dummy_W_or_R : 1; // dummy writes or read select 114 // dummy's are read 115 #define DUMMY_READS 0 116 // dummy's are written 117 #define DUMMY_WRITES 1 118 119 unsigned int extra_byte_en : 1; // Enable extra byte 120 // Extra byte will be enabled 121 #define EN_EXTRA_BYTE 122 // Extra byte will be disabled 123 #define DIS_EXTRA_BYTE 124 125 unsigned int d3d2_data : 2; // Data on D3 and D2 line in SPI or DUAL mode 126 127 unsigned int continuous : 1; // continuous mode select 128 // continuous mode is selected 129 #define CONTINUOUS 1 130 // discontinuous mode is selected 131 #define DIS_CONTINUOUS 0 132 133 unsigned int read_cmd : 8; // read cmd to be used 134 135 unsigned int flash_type : 4; // flash defines 136 // sst spi flash 137 #define FREAD_QUAD_O 0x6B 138 139 #define FREAD_QUAD_O_EB 0xEB 140 141 // WINBOND + MACRONIX specific cmds 142 143 // fast read dual IO 144 #define FREAD_DUAL_IO 0xBB 145 // fast read quad IO 146 #define FREAD_QUAD_IO 0xEB 147 #define SST_SPI_FLASH 0 148 // sst dual flash 149 #define SST_DUAL_FLASH 1 150 // sst quad flash 151 #define SST_QUAD_FLASH 2 152 // Winbond quad flash 153 #define WBOND_QUAD_FLASH 3 154 // Atmel quad flash 155 #define AT_QUAD_FLASH 4 156 // macronix quad flash 157 #define MX_QUAD_FLASH 5 158 // cFeon quad flash 159 #define EON_QUAD_FLASH 6 160 // Micron quad flash 161 #define MICRON_QUAD_FLASH 7 162 // Giga Device flash 163 #define GIGA_DEVICE_FLASH 8 164 // macronix octa flash 165 #define MX_OCTA_FLASH 9 166 // Adesto octa flash 167 #define ADESTO_OCTA_FLASH 10 168 169 #if defined(SLI_SI917) || defined(SLI_SI915) 170 // Adesto quad flash 171 #define ADESTO_QUAD_FLASH 11 172 //ISSI flash 173 #define ISSI_FLASH 12 174 175 //XMC fash 176 #define XMC_FLASH 13 177 178 #endif 179 unsigned int no_of_dummy_bytes : 4; // no_of_dummy_bytes to be used for read operations 180 } spi_config_1_t; 181 182 // This structure members are used to configure qspi 183 typedef struct spi_config_2_s { 184 185 unsigned int auto_mode : 1; // mode select 186 // Auto mode selection 187 #define EN_AUTO_MODE 1 188 // Manual mode selection 189 #define EN_MANUAL_MODE 0 190 191 unsigned int cs_no : 2; // QSPI chip_select 192 // cs-0 193 #define CHIP_ZERO 0 194 // cs-1 195 #define CHIP_ONE 1 196 // cs-2 197 #define CHIP_TWO 2 198 // cs-3 199 #define CHIP_THREE 3 200 201 unsigned int reserved1 : 1; // Jump Enable 202 // Enables jump 203 #define EN_JUMP 1 204 // Disables jump 205 #define DIS_JUMP 0 206 207 unsigned int neg_edge_sampling : 1; // For High speed mode, sample at neg edge 208 // enables neg edge sampling 209 #define NEG_EDGE_SAMPLING 1 210 // enables pos edge sampling 211 #define POS_EDGE_SAMPLING 0 212 213 unsigned int qspi_clk_en : 1; // qspi clk select 214 // full time clk will be provided 215 #define QSPI_FULL_TIME_CLK 1 216 // dynamic clk gating will be enabled 217 #define QSPI_DYNAMIC_CLK 0 218 219 unsigned int protection : 2; // flash protection select 220 // enable write protection 221 #define EN_WR_PROT 2 222 // remove write protection 223 #define REM_WR_PROT 1 224 // no change to wr protection 225 #define DNT_REM_WR_PROT 0 226 227 unsigned int dma_mode : 1; // dma mode enable 228 // use dma only in manaul mode 229 #define DMA_MODE 1 230 // dma will not be used 231 #define NO_DMA 0 232 233 unsigned int swap_en : 1; // swap enable for w/r 234 // swap will be enabled 235 #define SWAP 1 236 // swap will be disabled 237 #define NO_SWAP 0 238 239 unsigned int full_duplex : 2; // full duplex mode select 240 // do nothing for full duplex 241 #define IGNORE_FULL_DUPLEX 2 242 // enable full duplex 243 #define EN_FULL_DUPLEX 1 244 // disable full duplex 245 #define DIS_FULL_DUPLEX 0 246 247 unsigned int wrap_len_in_bytes : 3; // wrap len to be used 248 // wrap is diabled 249 #define NO_WRAP 7 250 // 8 byte wrap will be used 251 #define SST_8BYTE_WRAP 0 252 // 16 byte wrap will be used 253 #define SST_16BYTE_WRAP 1 254 // 32 byte wrap will be used 255 #define SST_32BYTE_WRAP 2 256 // 64 byte wrap will be used 257 #define SST_64BYTE_WRAP 3 258 259 // 16 byte wrap will be used 260 #define MICRON_16BYTE_WRAP 0 261 // 32 byte wrap will be used 262 #define MICRON_32BYTE_WRAP 1 263 // 64 byte wrap will be used 264 #define MICRON_64BYTE_WRAP 2 265 266 unsigned int addr_width_valid : 1; 267 // mode 3 clk will be used 268 // mode 0 clk will be used 269 270 unsigned int addr_width : 3; // addr width to used 271 // 32 bit addr is configured 272 #define _32BIT_ADDR 4 273 // 24 bit addr is configured 274 #define _24BIT_ADDR 3 275 // 16 bit addr is configured 276 #define _16BIT_ADDR 2 277 // 9 bit addr is configured 278 #define _9BIT_ADDR 1 279 // 8 bit addr is configured 280 #define _8BIT_ADDR 0 281 282 #define MANUAL_DUMMY_BYTE_OR_BIT_MODE BIT(25) 283 #define DUMMY_BYTE_OR_BIT_MODE BIT(0) 284 unsigned int dummy_cycles_for_controller : 2; 285 286 unsigned int reserved2 : 6; 287 // uint32 jump_inst : 8; // Instruction to be used in case of jump 288 289 unsigned int pinset_valid : 1; 290 291 unsigned int flash_pinset : 4; // width of memory protection reg for sst flashes 292 293 } spi_config_2_t; 294 295 // This structure members are used to configure qspi 296 typedef struct spi_config_3_s { 297 #define CONTINUE_FETCH_EN BIT(12) 298 #define WORD_SWAP_EN 20 299 unsigned int en_word_swap : 1; 300 unsigned int _16bit_cmd_valid : 1; 301 unsigned int _16bit_rd_cmd_msb : 8; 302 unsigned int xip_mode : 1; 303 unsigned int no_of_dummy_bytes_wrap : 4; // no_of_dummy_bytes to be used for wrap operations 304 #ifdef CHIP_9118 305 unsigned int ddr_mode_en : 1; 306 #else 307 unsigned int reserved : 1; 308 #endif 309 unsigned int wr_cmd : 8; 310 unsigned int wr_inst_mode : 2; 311 unsigned int wr_addr_mode : 2; 312 unsigned int wr_data_mode : 2; 313 unsigned int dummys_4_jump : 2; // no_of_dummy_bytes in case of jump instruction 314 } spi_config_3_t; 315 316 typedef struct spi_config_4_s { 317 unsigned int _16bit_wr_cmd_msb : 8; 318 unsigned int high_perf_mode_en : 1; //used for high performance mode not ddr 319 unsigned int qspi_loop_back_mode_en : 1; 320 #ifdef CHIP_9118 321 unsigned int qspi_manual_ddr_phasse : 1; 322 unsigned int ddr_data_mode : 1; 323 unsigned int ddr_inst_mode : 1; 324 unsigned int ddr_addr_mode : 1; 325 unsigned int ddr_dummy_mode : 1; 326 unsigned int ddr_extra_byte : 1; 327 #else 328 unsigned int reserved : 1; 329 unsigned int reserved1 : 1; 330 unsigned int reserved2 : 1; 331 unsigned int reserved3 : 1; 332 unsigned int reserved4 : 1; 333 unsigned int reserved5 : 1; 334 #endif 335 unsigned int dual_flash_mode : 1; 336 unsigned int secondary_csn : 1; 337 unsigned int polarity_mode : 1; 338 unsigned int valid_prot_bits : 4; 339 unsigned int no_of_ms_dummy_bytes : 4; 340 #ifdef CHIP_9118 341 unsigned int ddr_dll_en : 1; 342 #else 343 unsigned int reserved6 : 1; 344 #endif 345 unsigned int continue_fetch_en : 1; 346 unsigned int dma_write : 1; 347 unsigned int prot_top_bottom : 1; 348 unsigned int auto_csn_based_addr_en : 1; 349 } spi_config_4_t; 350 typedef struct spi_config_5_s { 351 unsigned int block_erase_cmd : 16; 352 unsigned int busy_bit_pos : 3; 353 unsigned int d7_d4_data : 4; 354 unsigned int dummy_bytes_for_rdsr : 4; 355 unsigned int reset_type : 5; 356 } spi_config_5_t; 357 358 typedef struct spi_config_6_s { 359 unsigned int chip_erase_cmd : 16; 360 unsigned int sector_erase_cmd : 16; 361 } spi_config_6_t; 362 363 typedef struct spi_config_7_s { 364 unsigned int status_reg_write_cmd : 16; 365 unsigned int status_reg_read_cmd : 16; 366 } spi_config_7_t; 367 368 // This structure has two daughter structures to configure qspi 369 typedef struct spi_config_s { 370 spi_config_1_t spi_config_1; // daughter structure 1 371 spi_config_2_t spi_config_2; // daughter structure 2 372 spi_config_3_t spi_config_3; // daughter structure 3 373 spi_config_4_t spi_config_4; // daughter structure 4 374 spi_config_5_t spi_config_5; // daughter structure 5 375 spi_config_6_t spi_config_6; // daughter structure 5 376 spi_config_7_t spi_config_7; // daughter structure 5 377 } spi_config_t; 378 379 typedef const struct qspi_func_s qspi_func_t; 380 381 struct qspi_func_s { 382 383 void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); 384 385 void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); 386 387 uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 388 389 void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, 390 uint32_t flash_type, 391 spi_config_t *spi_config, 392 uint32_t cs_no); 393 394 void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, 395 uint32_t write_value, 396 spi_config_t *spi_config, 397 uint32_t wr_reg_delay_ms); 398 399 uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); 400 401 void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, 402 uint32_t reg_write_cmd, 403 uint32_t reg_write_value, 404 uint32_t cs_no, 405 uint32_t wr_reg_delay_ms); 406 407 void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, 408 uint32_t data_mode, 409 uint32_t cs_no, 410 uint32_t ddr_en, 411 uint32_t flash_type); 412 413 void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); 414 415 void (*qspi_manual_read)(qspi_reg_t *qspi_reg, 416 spi_config_t *spi_config, 417 uint32_t addr, 418 uint8_t *data, 419 uint32_t hsize, 420 uint32_t len_in_bytes, 421 uint32_t dma_flags, 422 void *udmaHandle, 423 void *rpdmaHandle); 424 425 void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); 426 427 void (*qspi_auto_read)(uint32_t cs_no, 428 uint32_t addr, 429 uint8_t *data, 430 uint32_t hsize, 431 uint32_t len_in_bytes, 432 spi_config_t *spi_config, 433 uint32_t dma_flags); 434 435 void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 436 437 void (*qspi_spi_init)(qspi_reg_t *qspi_reg, 438 spi_config_t *spi_config, 439 uint32_t RSI_QSPI_FlashInit_req, 440 uint32_t wr_reg_delay_ms, 441 uint8_t fifo_thrsld); 442 443 void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, 444 spi_config_t *spi_config, 445 uint32_t erase_cmd, 446 uint32_t blk_sec_addr, 447 uint32_t dis_hw_ctrl, 448 uint32_t wr_reg_delay_ms); 449 450 uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, 451 spi_config_t *spi_config, 452 uint32_t write_cmd, 453 uint32_t addr, 454 uint8_t *data, 455 uint32_t len_in_bytes, 456 uint16_t page_size, 457 uint32_t hsize, 458 uint32_t dis_hw_ctrl, 459 uint32_t wr_reg_delay_ms, 460 uint32_t check_en, 461 uint32_t dma_flags, 462 void *udmaHandle, 463 void *rpdmaHandle); 464 465 void (*qspi_spi_read)(qspi_reg_t *qspi_reg, 466 spi_config_t *spi_config, 467 uint32_t addr, 468 uint8_t *data, 469 uint32_t hsize, 470 uint32_t len_in_bytes, 471 uint32_t dma_flags, 472 void *udmaHandle, 473 void *rpdmaHandle); 474 void (*RSI_QSPI_ConfigureQspiRead)(spi_config_t *spi_config, qspi_func_t *qspi_func); 475 476 void (*RSI_QSPI_ConfigureQspiWrite)(spi_config_t *spi_config, qspi_func_t *qspi_func); 477 void (*qspi_usleep)(uint32_t delay_us); // function ptr for halting processor for delay (us) specified 478 479 void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, 480 uint32_t protect, 481 uint32_t cs_no, 482 uint32_t num_prot_bytes, 483 uint32_t wr_reg_delay_ms); 484 485 #if defined(SLI_SI917) || defined(SLI_SI915) 486 #if defined(SLI_SI917B0) || defined(SLI_SI915) 487 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, 488 uint8_t mode, 489 uint32_t *key1, 490 uint32_t *key2, 491 uint32_t key_len, 492 uint32_t kh_enable); 493 #else 494 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); 495 #endif 496 #else 497 void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); 498 #endif 499 void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); 500 void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); 501 void (*qspi_status_control_reg_write)(spi_config_t *spi_config, 502 qspi_reg_t *qspi_reg, 503 uint16_t write_command, 504 uint32_t addr, 505 uint16_t write_value, 506 uint32_t cs_no, 507 uint32_t wr_reg_delay_ms); 508 void (*qspi_flash_protection)(spi_config_t *spi_config, 509 qspi_reg_t *qspi_reg, 510 uint32_t protection, 511 uint32_t wr_reg_delay_ms); 512 513 void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); 514 515 void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); 516 517 void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); 518 }; 519 520 // SPI API LIST 521 522 uint32_t qspi_flash_reg_read(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); 523 524 void qspi_status_reg_write(qspi_reg_t *qspi_reg, 525 uint32_t write_value, 526 spi_config_t *spi_config, 527 uint32_t wr_reg_delay_ms); 528 529 void qspi_enable_status_reg_write(qspi_reg_t *qspi_reg, uint32_t flash_type, spi_config_t *spi_config, uint32_t cs_no); 530 531 uint32_t qspi_wait_flash_status_Idle(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 532 533 void qspi_spi_init(qspi_reg_t *qspi_reg, 534 spi_config_t *spi_config, 535 uint32_t flash_init_req, 536 uint32_t wr_reg_delay_ms, 537 uint8_t fifo_thrsld); 538 #define FLASH_INIT_REQ 1 539 #define SKIP_FLASH_INIT 0 540 541 void qspi_spi_erase(qspi_reg_t *qspi_reg, 542 spi_config_t *spi_config, 543 uint32_t erase_cmd, 544 uint32_t blk_sec_addr, 545 uint32_t dis_hw_ctrl, 546 uint32_t wr_reg_delay_ms); 547 // chip erase cmd 548 #define CHIP_ERASE 0xC7 549 // block erase cmd 550 #define BLOCK_ERASE 0xD8 551 // sector erase cmd 552 #define SECTOR_ERASE 0x20 553 554 // disable hw ctrl 555 #define DIS_HW_CTRL 1 556 // donot disable hw ctrl 557 #define DNT_DIS_HW_CTRL 0 558 559 // 32bit hsize 560 #define _32BIT 3 561 // 24bit hsize is not supported, so reserved 562 // reserved 2 563 // 16bit hsize 564 #define _16BIT 1 565 // 8bit hsize 566 #define _8BIT 0 567 568 uint32_t qspi_spi_write(qspi_reg_t *qspi_reg, 569 spi_config_t *spi_config, 570 uint32_t write_cmd, 571 uint32_t addr, 572 uint8_t *data, 573 uint32_t len_in_bytes, 574 uint16_t page_size, 575 uint32_t hsize, 576 uint32_t dis_hw_ctrl, 577 uint32_t wr_reg_delay_ms, 578 uint32_t check_en, 579 uint32_t dma_flags, 580 void *udmaHandle, 581 void *rpdmaHandle); 582 583 void qspi_spi_read(qspi_reg_t *qspi_reg, 584 spi_config_t *spi_config, 585 uint32_t addr, 586 uint8_t *data, 587 uint32_t hsize, 588 uint32_t len_in_bytes, 589 uint32_t dma_flags, 590 void *udmaHandle, 591 void *rpdmaHandle); 592 593 uint32_t RSI_QSPI_Aes_Encrypt_Decrypt_Standalone(qspi_reg_t *qspi_reg, 594 qspi_standalone_config_t *configs, 595 uint32_t *in_data, 596 uint32_t *out_data, 597 uint32_t data_length); 598 599 // ROM API Fuctions 600 601 void qspi_write_block_protect(qspi_reg_t *qspi_reg, 602 uint32_t protect, 603 uint32_t cs_no, 604 uint32_t num_prot_bytes, 605 uint32_t wr_reg_delay_ms); 606 void qspi_usleep(uint32_t delay_us); // function ptr for halting processor for delay (us) specified 607 void qspi_auto_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config); 608 void qspi_set_flash_mode(qspi_reg_t *qspi_reg, 609 uint32_t data_mode, 610 uint32_t cs_no, 611 uint32_t ddr_en, 612 uint32_t flash_type); 613 614 void qspi_write_to_flash(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); 615 616 void qspi_switch_qspi2(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); 617 618 void qspi_flash_reg_write(qspi_reg_t *qspi_reg, 619 uint32_t reg_write_cmd, 620 uint32_t reg_write_value, 621 uint32_t cs_no, 622 uint32_t wr_reg_delay_ms); 623 624 void qspi_config_qflash4_read(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); 625 626 void qspi_manual_read(qspi_reg_t *qspi_reg, 627 spi_config_t *spi_config, 628 uint32_t addr, 629 uint8_t *data, 630 uint32_t hsize, 631 uint32_t len_in_bytes, 632 uint32_t dma_flags, 633 void *udmaHandle, 634 void *rpdmaHandle); 635 636 void qspi_auto_read(uint32_t cs_no, 637 uint32_t addr, 638 uint8_t *data, 639 uint32_t hsize, 640 uint32_t len_in_bytes, 641 spi_config_t *spi_config, 642 uint32_t dma_flags); 643 644 void qspi_flash_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); 645 646 #if defined(SLI_SI917) || defined(SLI_SI915) 647 #if defined(SLI_SI917B0) || defined(SLI_SI915) 648 void qspi_qspiload_key(qspi_reg_t *qspi_reg, 649 uint8_t mode, 650 uint32_t *key1, 651 uint32_t *key2, 652 uint32_t key_len, 653 uint32_t kh_enable); 654 #else 655 void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); 656 #endif 657 #else 658 void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); 659 #endif 660 661 void qspi_qspiload_nonce(qspi_reg_t *qspi_reg, uint32_t *nonce); 662 663 void qspi_seg_sec_en(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); 664 void qspi_status_control_reg_write(spi_config_t *spi_config, 665 qspi_reg_t *qspi_reg, 666 uint16_t write_command, 667 uint32_t addr, 668 uint16_t write_value, 669 uint32_t cs_no, 670 uint32_t wr_reg_delay_ms); 671 void qspi_flash_protection(spi_config_t *spi_config, 672 qspi_reg_t *qspi_reg, 673 uint32_t protection, 674 uint32_t wr_reg_delay_ms); 675 676 void RSI_QSPI_ResetFlash(qspi_reg_t *qspi_reg, uint32_t cs_no); 677 678 void RSI_QSPI_UpdateOperatingMode_and_ResetType(qspi_reg_t *qspi_reg, uint32_t operating_mode); 679 680 extern spi_config_t spi_default_config; 681 682 #ifdef __cplusplus 683 } 684 #endif 685 686 #endif // QSPI_PROTO_H 687
