1 /* 2 * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include "soc/soc.h" 10 #include "soc/sensitive_reg.h" 11 #include "esp32c3/rom/cache.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 typedef union { 18 struct { 19 uint32_t cat0 : 2; 20 uint32_t cat1 : 2; 21 uint32_t cat2 : 2; 22 uint32_t res0 : 8; 23 uint32_t splitaddr : 8; 24 uint32_t res1 : 10; 25 }; 26 uint32_t val; 27 } constrain_reg_fields_t; 28 29 #ifndef I_D_SRAM_SEGMENT_SIZE 30 #define I_D_SRAM_SEGMENT_SIZE 0x20000 31 #endif 32 33 #define I_D_SPLIT_LINE_SHIFT 0x9 34 #define I_D_FAULT_ADDR_SHIFT 0x2 35 36 #define DRAM_SRAM_START 0x3FC7C000 37 38 #ifndef MAP_DRAM_TO_IRAM 39 #define MAP_DRAM_TO_IRAM(addr) (addr - DRAM_SRAM_START + SOC_IRAM_LOW) 40 #endif 41 42 #ifndef MAP_IRAM_TO_DRAM 43 #define MAP_IRAM_TO_DRAM(addr) (addr - SOC_IRAM_LOW + DRAM_SRAM_START) 44 #endif 45 46 //IRAM0 47 48 //16kB (ICACHE) 49 #define IRAM0_SRAM_LEVEL_0_LOW SOC_IRAM_LOW //0x40370000 50 #define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + CACHE_MEMORY_IBANK_SIZE - 0x1) //0x4037FFFF 51 52 //128kB (LEVEL 1) 53 #define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000 54 #define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF 55 56 //128kB (LEVEL 2) 57 #define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000 58 #define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF 59 60 //128kB (LEVEL 3) 61 #define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000 62 #define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF 63 64 //permission bits 65 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 66 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 67 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F 0x4 68 69 //DRAM0 70 71 //16kB ICACHE not available from DRAM0 72 73 //128kB (LEVEL 1) 74 #define DRAM0_SRAM_LEVEL_1_LOW SOC_DRAM_LOW //0x3FC80000 75 #define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF 76 77 //128kB (LEVEL 2) 78 #define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000 79 #define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF 80 81 //128kB (LEVEL 3) 82 #define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000 83 #define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF 84 85 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R 0x1 86 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W 0x2 87 88 //RTC FAST 89 90 //permission bits 91 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W 0x1 92 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R 0x2 93 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F 0x4 94 95 #define AREA_LOW 0 96 #define AREA_HIGH 1 97 98 #ifdef __cplusplus 99 } 100 #endif 101
