1 /*
2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8 #include <common/debug.h>
9 #include <drivers/delay_timer.h>
10 #include <lib/mmio.h>
11
12 #include "socfpga_f2sdram_manager.h"
13 #include "socfpga_mailbox.h"
14 #include "socfpga_reset_manager.h"
15 #include "socfpga_system_manager.h"
16
17
deassert_peripheral_reset(void)18 void deassert_peripheral_reset(void)
19 {
20 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
21 RSTMGR_FIELD(PER1, WATCHDOG0) |
22 RSTMGR_FIELD(PER1, WATCHDOG1) |
23 RSTMGR_FIELD(PER1, WATCHDOG2) |
24 RSTMGR_FIELD(PER1, WATCHDOG3) |
25 RSTMGR_FIELD(PER1, L4SYSTIMER0) |
26 RSTMGR_FIELD(PER1, L4SYSTIMER1) |
27 RSTMGR_FIELD(PER1, SPTIMER0) |
28 RSTMGR_FIELD(PER1, SPTIMER1) |
29 RSTMGR_FIELD(PER1, I2C0) |
30 RSTMGR_FIELD(PER1, I2C1) |
31 RSTMGR_FIELD(PER1, I2C2) |
32 RSTMGR_FIELD(PER1, I2C3) |
33 RSTMGR_FIELD(PER1, I2C4) |
34 RSTMGR_FIELD(PER1, UART0) |
35 RSTMGR_FIELD(PER1, UART1) |
36 RSTMGR_FIELD(PER1, GPIO0) |
37 RSTMGR_FIELD(PER1, GPIO1));
38
39 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
40 RSTMGR_FIELD(PER0, EMAC0OCP) |
41 RSTMGR_FIELD(PER0, EMAC1OCP) |
42 RSTMGR_FIELD(PER0, EMAC2OCP) |
43 RSTMGR_FIELD(PER0, USB0OCP) |
44 RSTMGR_FIELD(PER0, USB1OCP) |
45 RSTMGR_FIELD(PER0, NANDOCP) |
46 RSTMGR_FIELD(PER0, SDMMCOCP) |
47 RSTMGR_FIELD(PER0, DMAOCP));
48
49 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
50 RSTMGR_FIELD(PER0, EMAC0) |
51 RSTMGR_FIELD(PER0, EMAC1) |
52 RSTMGR_FIELD(PER0, EMAC2) |
53 RSTMGR_FIELD(PER0, USB0) |
54 RSTMGR_FIELD(PER0, USB1) |
55 RSTMGR_FIELD(PER0, NAND) |
56 RSTMGR_FIELD(PER0, SDMMC) |
57 RSTMGR_FIELD(PER0, DMA) |
58 RSTMGR_FIELD(PER0, SPIM0) |
59 RSTMGR_FIELD(PER0, SPIM1) |
60 RSTMGR_FIELD(PER0, SPIS0) |
61 RSTMGR_FIELD(PER0, SPIS1) |
62 RSTMGR_FIELD(PER0, EMACPTP) |
63 RSTMGR_FIELD(PER0, DMAIF0) |
64 RSTMGR_FIELD(PER0, DMAIF1) |
65 RSTMGR_FIELD(PER0, DMAIF2) |
66 RSTMGR_FIELD(PER0, DMAIF3) |
67 RSTMGR_FIELD(PER0, DMAIF4) |
68 RSTMGR_FIELD(PER0, DMAIF5) |
69 RSTMGR_FIELD(PER0, DMAIF6) |
70 RSTMGR_FIELD(PER0, DMAIF7));
71
72 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
73 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
74 RSTMGR_FIELD(BRG, MPFE));
75 #endif
76 }
77
config_hps_hs_before_warm_reset(void)78 void config_hps_hs_before_warm_reset(void)
79 {
80 uint32_t or_mask = 0;
81
82 or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN;
83 or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
84 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
85 or_mask |= RSTMGR_HDSKEN_L2FLUSHEN;
86 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
87 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
88
89 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
90 }
91
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match)92 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
93 {
94 int time_out = 300;
95
96 while (time_out--) {
97 if ((mmio_read_32(addr) & mask) == match) {
98 return 0;
99 }
100 udelay(1000);
101 }
102 return -ETIMEDOUT;
103 }
104
socfpga_s2f_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * noc_mask)105 static void socfpga_s2f_bridge_mask(uint32_t mask,
106 uint32_t *brg_mask,
107 uint32_t *noc_mask)
108 {
109 *brg_mask = 0;
110 *noc_mask = 0;
111
112 if ((mask & SOC2FPGA_MASK) != 0U) {
113 *brg_mask |= RSTMGR_FIELD(BRG, SOC2FPGA);
114 *noc_mask |= IDLE_DATA_SOC2FPGA;
115 }
116
117 if ((mask & LWHPS2FPGA_MASK) != 0U) {
118 *brg_mask |= RSTMGR_FIELD(BRG, LWHPS2FPGA);
119 *noc_mask |= IDLE_DATA_LWSOC2FPGA;
120 }
121 }
122
socfpga_f2s_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * f2s_idlereq,uint32_t * f2s_force_drain,uint32_t * f2s_en,uint32_t * f2s_idleack,uint32_t * f2s_respempty)123 static void socfpga_f2s_bridge_mask(uint32_t mask,
124 uint32_t *brg_mask,
125 uint32_t *f2s_idlereq,
126 uint32_t *f2s_force_drain,
127 uint32_t *f2s_en,
128 uint32_t *f2s_idleack,
129 uint32_t *f2s_respempty)
130 {
131 *brg_mask = 0;
132 *f2s_idlereq = 0;
133 *f2s_force_drain = 0;
134 *f2s_en = 0;
135 *f2s_idleack = 0;
136 *f2s_respempty = 0;
137
138 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
139 if ((mask & FPGA2SOC_MASK) != 0U) {
140 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
141 }
142 if ((mask & F2SDRAM0_MASK) != 0U) {
143 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
144 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
145 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
146 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
147 *f2s_idleack |= FLAGINTSTATUS_F2SDRAM0_IDLEACK;
148 *f2s_respempty |= FLAGINTSTATUS_F2SDRAM0_RESPEMPTY;
149 }
150 if ((mask & F2SDRAM1_MASK) != 0U) {
151 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
152 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
153 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
154 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
155 *f2s_idleack |= FLAGINTSTATUS_F2SDRAM1_IDLEACK;
156 *f2s_respempty |= FLAGINTSTATUS_F2SDRAM1_RESPEMPTY;
157 }
158 if ((mask & F2SDRAM2_MASK) != 0U) {
159 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
160 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
161 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
162 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
163 *f2s_idleack |= FLAGINTSTATUS_F2SDRAM2_IDLEACK;
164 *f2s_respempty |= FLAGINTSTATUS_F2SDRAM2_RESPEMPTY;
165 }
166 #else
167 if ((mask & FPGA2SOC_MASK) != 0U) {
168 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
169 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
170 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
171 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
172 *f2s_idleack |= FLAGINTSTATUS_F2SDRAM0_IDLEACK;
173 *f2s_respempty |= FLAGINTSTATUS_F2SDRAM0_RESPEMPTY;
174 }
175 #endif
176 }
177
socfpga_bridges_enable(uint32_t mask)178 int socfpga_bridges_enable(uint32_t mask)
179 {
180 int ret = 0;
181 uint32_t brg_mask = 0;
182 uint32_t noc_mask = 0;
183 uint32_t f2s_idlereq = 0;
184 uint32_t f2s_force_drain = 0;
185 uint32_t f2s_en = 0;
186 uint32_t f2s_idleack = 0;
187 uint32_t f2s_respempty = 0;
188
189 /* Enable s2f bridge */
190 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
191 if (brg_mask != 0U) {
192 /* Clear idle request */
193 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR),
194 noc_mask);
195
196 /* De-assert all bridges */
197 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
198
199 /* Wait until idle ack becomes 0 */
200 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
201 noc_mask, 0);
202 if (ret < 0) {
203 ERROR("S2F bridge enable: "
204 "Timeout waiting for idle ack\n");
205 }
206 }
207
208 /* Enable f2s bridge */
209 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
210 &f2s_force_drain, &f2s_en,
211 &f2s_idleack, &f2s_respempty);
212 if (brg_mask != 0U) {
213 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
214
215 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
216 f2s_idlereq);
217
218 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(
219 SIDEBANDMGR_FLAGINSTATUS0), f2s_idleack, 0);
220 if (ret < 0) {
221 ERROR("F2S bridge enable: "
222 "Timeout waiting for idle ack");
223 }
224
225 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
226 f2s_force_drain);
227 udelay(5);
228
229 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
230 f2s_en);
231 udelay(5);
232 }
233
234 return ret;
235 }
236
socfpga_bridges_disable(uint32_t mask)237 int socfpga_bridges_disable(uint32_t mask)
238 {
239 int ret = 0;
240 int timeout = 300;
241 uint32_t brg_mask = 0;
242 uint32_t noc_mask = 0;
243 uint32_t f2s_idlereq = 0;
244 uint32_t f2s_force_drain = 0;
245 uint32_t f2s_en = 0;
246 uint32_t f2s_idleack = 0;
247 uint32_t f2s_respempty = 0;
248
249 /* Disable s2f bridge */
250 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
251 if (brg_mask != 0U) {
252 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET),
253 noc_mask);
254
255 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
256
257 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
258 noc_mask, noc_mask);
259 if (ret < 0) {
260 ERROR("S2F Bridge disable: "
261 "Timeout waiting for idle ack\n");
262 }
263
264 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
265 noc_mask, noc_mask);
266 if (ret < 0) {
267 ERROR("S2F Bridge disable: "
268 "Timeout waiting for idle status\n");
269 }
270
271 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
272
273 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0);
274 }
275
276 /* Disable f2s bridge */
277 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
278 &f2s_force_drain, &f2s_en,
279 &f2s_idleack, &f2s_respempty);
280 if (brg_mask != 0U) {
281 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
282 RSTMGR_HDSKEN_FPGAHSEN);
283
284 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
285 RSTMGR_HDSKREQ_FPGAHSREQ);
286
287 poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
288 RSTMGR_HDSKACK_FPGAHSACK_MASK,
289 RSTMGR_HDSKACK_FPGAHSACK_MASK);
290
291 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
292 f2s_en);
293 udelay(5);
294
295 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
296 f2s_force_drain);
297 udelay(5);
298
299 do {
300 /* Read response queue status to ensure it is empty */
301 uint32_t idle_status;
302
303 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
304 SIDEBANDMGR_FLAGINSTATUS0));
305 if ((idle_status & f2s_respempty) != 0U) {
306 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
307 SIDEBANDMGR_FLAGINSTATUS0));
308 if ((idle_status & f2s_respempty) != 0U) {
309 break;
310 }
311 }
312 udelay(1000);
313 } while (timeout-- > 0);
314
315 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
316 /* Software must never write a 0x1 to FPGA2SOC_MASK bit */
317 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
318 brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC));
319 #else
320 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
321 brg_mask);
322 #endif
323 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
324 RSTMGR_HDSKEQ_FPGAHSREQ);
325
326 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
327 f2s_idlereq);
328 }
329
330 return ret;
331 }
332
