1 /* 2 * Copyright (c) 2020, Seagate Technology LLC 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ 8 #define ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ 9 10 #define LPC11U6X_I2C_CONTROL_AA (1 << 2) 11 #define LPC11U6X_I2C_CONTROL_SI (1 << 3) 12 #define LPC11U6X_I2C_CONTROL_STOP (1 << 4) 13 #define LPC11U6X_I2C_CONTROL_START (1 << 5) 14 #define LPC11U6X_I2C_CONTROL_I2C_EN (1 << 6) 15 16 /* I2C controller states */ 17 #define LPC11U6X_I2C_MASTER_TX_START 0x08 18 #define LPC11U6X_I2C_MASTER_TX_RESTART 0x10 19 #define LPC11U6X_I2C_MASTER_TX_ADR_ACK 0x18 20 #define LPC11U6X_I2C_MASTER_TX_ADR_NACK 0x20 21 #define LPC11U6X_I2C_MASTER_TX_DAT_ACK 0x28 22 #define LPC11U6X_I2C_MASTER_TX_DAT_NACK 0x30 23 #define LPC11U6X_I2C_MASTER_TX_ARB_LOST 0x38 24 25 #define LPC11U6X_I2C_MASTER_RX_ADR_ACK 0x40 26 #define LPC11U6X_I2C_MASTER_RX_ADR_NACK 0x48 27 #define LPC11U6X_I2C_MASTER_RX_DAT_ACK 0x50 28 #define LPC11U6X_I2C_MASTER_RX_DAT_NACK 0x58 29 30 #define LPC11U6X_I2C_SLAVE_RX_ADR_ACK 0x60 31 #define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_ADR_ACK 0x68 32 #define LPC11U6X_I2C_SLAVE_RX_GC_ACK 0x70 33 #define LPC11U6X_I2C_SLAVE_RX_ARB_LOST_GC_ACK 0x78 34 #define LPC11U6X_I2C_SLAVE_RX_DAT_ACK 0x80 35 #define LPC11U6X_I2C_SLAVE_RX_DAT_NACK 0x88 36 #define LPC11U6X_I2C_SLAVE_RX_GC_DAT_ACK 0x90 37 #define LPC11U6X_I2C_SLAVE_RX_GC_DAT_NACK 0x98 38 #define LPC11U6X_I2C_SLAVE_RX_STOP 0xA0 39 40 #define LPC11U6X_I2C_SLAVE_TX_ADR_ACK 0xA8 41 #define LPC11U6X_I2C_SLAVE_TX_ARB_LOST_ADR_ACK 0xB0 42 #define LPC11U6X_I2C_SLAVE_TX_DAT_ACK 0xB8 43 #define LPC11U6X_I2C_SLAVE_TX_DAT_NACK 0xC0 44 #define LPC11U6X_I2C_SLAVE_TX_LAST_BYTE 0xC8 45 46 /* Transfer Status */ 47 #define LPC11U6X_I2C_STATUS_BUSY 0x01 48 #define LPC11U6X_I2C_STATUS_OK 0x02 49 #define LPC11U6X_I2C_STATUS_FAIL 0x03 50 #define LPC11U6X_I2C_STATUS_INACTIVE 0x04 51 52 struct lpc11u6x_i2c_regs { 53 volatile uint32_t con_set; /* Control set */ 54 volatile const uint32_t stat; /* Status */ 55 volatile uint32_t dat; /* Data */ 56 volatile uint32_t addr0; /* Slave address 0 */ 57 volatile uint32_t sclh; /* SCL Duty Cycle */ 58 volatile uint32_t scll; /* SCL Duty Cycle */ 59 volatile uint32_t con_clr; /* Control clear */ 60 volatile uint32_t mm_ctrl; /* Monitor mode control */ 61 volatile uint32_t addr[3]; /* Slave address {1,2,3} */ 62 volatile const uint32_t data_buffer; /* Data buffer */ 63 volatile uint32_t mask[4]; /* Slave address mask */ 64 }; 65 66 struct lpc11u6x_i2c_config { 67 struct lpc11u6x_i2c_regs *base; 68 char *clock_drv; 69 char *scl_pinmux_drv; 70 char *sda_pinmux_drv; 71 void (*irq_config_func)(const struct device *dev); 72 uint32_t clkid; 73 uint32_t scl_flags; 74 uint32_t sda_flags; 75 uint8_t scl_pin; 76 uint8_t sda_pin; 77 }; 78 79 struct lpc11u6x_i2c_current_transfer { 80 struct i2c_msg *msgs; 81 uint8_t *curr_buf; 82 uint8_t curr_len; 83 uint8_t nr_msgs; 84 uint8_t addr; 85 uint8_t status; 86 }; 87 88 struct lpc11u6x_i2c_data { 89 struct lpc11u6x_i2c_current_transfer transfer; 90 struct i2c_slave_config *slave; 91 struct k_sem completion; 92 struct k_mutex mutex; 93 }; 94 95 #endif /* ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_ */ 96
