1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef R_GPT_H 8 #define R_GPT_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup GPT 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_timer_api.h" 20 21 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 22 FSP_HEADER 23 24 /*********************************************************************************************************************** 25 * Macro definitions 26 **********************************************************************************************************************/ 27 28 /*********************************************************************************************************************** 29 * Typedef definitions 30 **********************************************************************************************************************/ 31 32 /** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ 33 typedef enum e_gpt_io_pin 34 { 35 GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA 36 GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB 37 GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB 38 GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 39 GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 40 GPT_IO_PIN_ONE_SHOT_LEADING_EDGE = 4, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected. 41 GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE = 8, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected. 42 } gpt_io_pin_t; 43 44 /** Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet(). */ 45 typedef enum e_gpt_buffer_force_push 46 { 47 GPT_BUFFER_FORCE_PUSH = 64, ///< Used in @ref R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected. 48 } gpt_buffer_force_push; 49 50 /** Level of GPT pin */ 51 typedef enum e_gpt_pin_level 52 { 53 GPT_PIN_LEVEL_LOW = 0, ///< Pin level low 54 GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high 55 } gpt_pin_level_t; 56 57 /** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent 58 * a bitmask. Multiple sources can be ORed together. */ 59 typedef enum e_gpt_source 60 { 61 /** No active event sources. */ 62 GPT_SOURCE_NONE = 0U, 63 64 /** Action performed on GTETRGA rising edge. **/ 65 GPT_SOURCE_GTETRGA_RISING = (1U << 0), 66 67 /** Action performed on GTETRGA falling edge. **/ 68 GPT_SOURCE_GTETRGA_FALLING = (1U << 1), 69 70 /** Action performed on GTETRGB rising edge. **/ 71 GPT_SOURCE_GTETRGB_RISING = (1U << 2), 72 73 /** Action performed on GTETRGB falling edge. **/ 74 GPT_SOURCE_GTETRGB_FALLING = (1U << 3), 75 76 /** Action performed on GTETRGC rising edge. **/ 77 GPT_SOURCE_GTETRGC_RISING = (1U << 4), 78 79 /** Action performed on GTETRGC falling edge. **/ 80 GPT_SOURCE_GTETRGC_FALLING = (1U << 5), 81 82 /** Action performed on GTETRGB rising edge. **/ 83 GPT_SOURCE_GTETRGD_RISING = (1U << 6), 84 85 /** Action performed on GTETRGB falling edge. **/ 86 GPT_SOURCE_GTETRGD_FALLING = (1U << 7), 87 88 /** Action performed when GTIOCA input rises while GTIOCB is low. **/ 89 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), 90 91 /** Action performed when GTIOCA input rises while GTIOCB is high. **/ 92 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), 93 94 /** Action performed when GTIOCA input falls while GTIOCB is low. **/ 95 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), 96 97 /** Action performed when GTIOCA input falls while GTIOCB is high. **/ 98 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), 99 100 /** Action performed when GTIOCB input rises while GTIOCA is low. **/ 101 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), 102 103 /** Action performed when GTIOCB input rises while GTIOCA is high. **/ 104 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), 105 106 /** Action performed when GTIOCB input falls while GTIOCA is low. **/ 107 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), 108 109 /** Action performed when GTIOCB input falls while GTIOCA is high. **/ 110 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), 111 112 /** Action performed on ELC GPTA event. **/ 113 GPT_SOURCE_GPT_A = (1U << 16), 114 115 /** Action performed on ELC GPTB event. **/ 116 GPT_SOURCE_GPT_B = (1U << 17), 117 118 /** Action performed on ELC GPTC event. **/ 119 GPT_SOURCE_GPT_C = (1U << 18), 120 121 /** Action performed on ELC GPTD event. **/ 122 GPT_SOURCE_GPT_D = (1U << 19), 123 124 /** Action performed on ELC GPTE event. **/ 125 GPT_SOURCE_GPT_E = (1U << 20), 126 127 /** Action performed on ELC GPTF event. **/ 128 GPT_SOURCE_GPT_F = (1U << 21), 129 130 /** Action performed on ELC GPTG event. **/ 131 GPT_SOURCE_GPT_G = (1U << 22), 132 133 /** Action performed on ELC GPTH event. **/ 134 GPT_SOURCE_GPT_H = (1U << 23), 135 } gpt_source_t; 136 137 /** Configurations for output pins. */ 138 typedef struct s_gpt_output_pin 139 { 140 bool output_enabled; ///< Set to true to enable output, false to disable output 141 gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t 142 } gpt_output_pin_t; 143 144 /** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */ 145 typedef struct s_gpt_gtior_setting 146 { 147 union 148 { 149 uint32_t gtior; 150 struct 151 { 152 /* Settings for GTIOCxA pin. */ 153 uint32_t gtioa : 5; ///< GTIOCA Pin Function Select. 154 uint32_t : 1; // Reserved 155 uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop. 156 uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count. 157 uint32_t oae : 1; ///< GTIOCA Pin Output Enable 158 uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting. 159 uint32_t : 2; /// Reserved 160 uint32_t nfaen : 1; /// Noise Filter A Enable. 161 uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select. 162 163 /* Settings for GTIOCxB pin. */ 164 uint32_t gtiob : 5; ///< GTIOCB Pin Function Select. 165 uint32_t : 1; // Reserved 166 uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop. 167 uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count. 168 uint32_t obe : 1; ///< GTIOCB Pin Output Enable 169 uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting. 170 uint32_t : 2; /// Reserved 171 uint32_t nfben : 1; /// Noise Filter B Enable. 172 uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select. 173 } gtior_b; 174 }; 175 } gpt_gtior_setting_t; 176 177 /** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. 178 * The noise filter samples the external signal at intervals of the PCLK divided by one of the values. 179 * When 3 consecutive samples are at the same level (high or low), then that level is passed on as 180 * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. 181 */ 182 typedef enum e_gpt_capture_filter 183 { 184 GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering 185 GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling 186 GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4 187 GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16 188 GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling 189 } gpt_capture_filter_t; 190 191 /** Trigger options to start A/D conversion. */ 192 typedef enum e_gpt_adc_trigger 193 { 194 GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request 195 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 196 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 197 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 198 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 199 } gpt_adc_trigger_t; 200 201 /** POEG channel to link to this channel. */ 202 typedef enum e_gpt_poeg_link 203 { 204 GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) 205 GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) 206 GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) 207 GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) 208 } gpt_poeg_link_t; 209 210 /** Select trigger to send output disable request to POEG. */ 211 typedef enum e_gpt_output_disable 212 { 213 GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request 214 GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs 215 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time 216 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time 217 } gpt_output_disable_t; 218 219 /** Disable level options for GTIOC pins. */ 220 typedef enum e_gpt_gtioc_disable 221 { 222 GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable 223 GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled 224 GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled 225 GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled 226 } gpt_gtioc_disable_t; 227 228 /** Trigger options to start A/D conversion. */ 229 typedef enum e_gpt_adc_compare_match 230 { 231 GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A 232 GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B 233 } gpt_adc_compare_match_t; 234 235 /** Interrupt skipping modes */ 236 typedef enum e_gpt_interrupt_skip_source 237 { 238 GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts 239 GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts 240 241 /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 242 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest 243 * interrupt. */ 244 GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, 245 246 /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 247 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough 248 * interrupt. */ 249 GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, 250 } gpt_interrupt_skip_source_t; 251 252 /** Number of interrupts to skip between events */ 253 typedef enum e_gpt_interrupt_skip_count 254 { 255 GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts 256 GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt 257 GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts 258 GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts 259 GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts 260 GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts 261 GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts 262 GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts 263 } gpt_interrupt_skip_count_t; 264 265 /** ADC events to skip during interrupt skipping */ 266 typedef enum e_gpt_interrupt_skip_adc 267 { 268 GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events 269 GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events 270 GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events 271 GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events 272 } gpt_interrupt_skip_adc_t; 273 274 /** Delay setting for the PWM Delay Generation Circuit (PDG). */ 275 typedef enum e_gpt_pwm_output_delay_setting 276 { 277 GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied. 278 GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied. 279 GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied. 280 GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied. 281 GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied. 282 GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied. 283 GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied. 284 GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied. 285 GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied. 286 GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied. 287 GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied. 288 GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied. 289 GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied. 290 GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied. 291 GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied. 292 GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied. 293 GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied. 294 GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied. 295 GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied. 296 GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied. 297 GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied. 298 GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied. 299 GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied. 300 GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied. 301 GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied. 302 GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied. 303 GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied. 304 GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied. 305 GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied. 306 GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied. 307 GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied. 308 GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied. 309 GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit. 310 } gpt_pwm_output_delay_setting_t; 311 312 /** Select which PWM Output Delay setting to apply. */ 313 typedef enum e_gpt_pwm_output_delay_edge 314 { 315 GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge. 316 GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge. 317 } gpt_pwm_output_delay_edge_t; 318 319 /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ 320 typedef struct st_gpt_instance_ctrl 321 { 322 uint32_t open; // Whether or not channel is open 323 const timer_cfg_t * p_cfg; // Pointer to initial configurations 324 R_GPT0_Type * p_reg; // Base register for this channel 325 uint32_t channel_mask; // Channel bitmask 326 timer_variant_t variant; // Timer variant 327 328 void (* p_callback)(timer_callback_args_t *); // Pointer to callback 329 timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory 330 void const * p_context; // Pointer to context to be passed into callback function 331 } gpt_instance_ctrl_t; 332 333 /** GPT extension for advanced PWM features. */ 334 typedef struct st_gpt_extended_pwm_cfg 335 { 336 uint8_t trough_ipl; ///< Trough interrupt priority 337 IRQn_Type trough_irq; ///< Trough interrupt 338 gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel 339 gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG 340 gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion 341 uint32_t dead_time_count_up; ///< Set a dead time value for counting up 342 uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only) 343 uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A 344 uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B 345 gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping 346 gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events 347 gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled 348 gpt_gtioc_disable_t gtioca_disable_setting; ///< Select how to configure GTIOCA when output is disabled 349 gpt_gtioc_disable_t gtiocb_disable_setting; ///< Select how to configure GTIOCB when output is disabled 350 } gpt_extended_pwm_cfg_t; 351 352 /** GPT extension configures the output pins for GPT. */ 353 typedef struct st_gpt_extended_cfg 354 { 355 gpt_output_pin_t gtioca; ///< Configuration for GPT I/O pin A 356 gpt_output_pin_t gtiocb; ///< Configuration for GPT I/O pin B 357 gpt_source_t start_source; ///< Event sources that trigger the timer to start 358 gpt_source_t stop_source; ///< Event sources that trigger the timer to stop 359 gpt_source_t clear_source; ///< Event sources that trigger the timer to clear 360 gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA 361 gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB 362 363 /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source 364 * and count_down_source, then the timer count source is PCLK. */ 365 gpt_source_t count_up_source; 366 367 /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source 368 * and count_down_source, then the timer count source is PCLK. */ 369 gpt_source_t count_down_source; 370 371 /* Debounce filter for GTIOCxA input signal pin. */ 372 gpt_capture_filter_t capture_filter_gtioca; 373 374 /* Debounce filter for GTIOCxB input signal pin. */ 375 gpt_capture_filter_t capture_filter_gtiocb; 376 377 uint8_t capture_a_ipl; ///< Capture A interrupt priority 378 uint8_t capture_b_ipl; ///< Capture B interrupt priority 379 IRQn_Type capture_a_irq; ///< Capture A interrupt 380 IRQn_Type capture_b_irq; ///< Capture B interrupt 381 382 uint32_t compare_match_value[2]; ///< Storing compare match value for channels 383 uint8_t compare_match_status; ///< Storing the compare match register status 384 385 gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional 386 gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. 387 } gpt_extended_cfg_t; 388 389 /********************************************************************************************************************** 390 * Exported global variables 391 **********************************************************************************************************************/ 392 393 /** @cond INC_HEADER_DEFS_SEC */ 394 /** Filled in Interface API structure for this Instance. */ 395 extern const timer_api_t g_timer_on_gpt; 396 397 /** @endcond */ 398 399 /*********************************************************************************************************************** 400 * Public APIs 401 **********************************************************************************************************************/ 402 fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); 403 fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); 404 fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); 405 fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); 406 fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); 407 fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); 408 fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); 409 fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); 410 fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); 411 fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); 412 fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); 413 fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 414 fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 415 fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, 416 gpt_adc_compare_match_t which_compare_match, 417 uint32_t compare_match_value); 418 fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl, 419 gpt_pwm_output_delay_edge_t edge, 420 gpt_pwm_output_delay_setting_t delay_setting, 421 uint32_t const pin); 422 fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, 423 void ( * p_callback)(timer_callback_args_t *), 424 void const * const p_context, 425 timer_callback_args_t * const p_callback_memory); 426 fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); 427 fsp_err_t R_GPT_PwmOutputDelayInitialize(void); 428 fsp_err_t R_GPT_CompareMatchSet(timer_ctrl_t * const p_ctrl, 429 uint32_t const compare_match_value, 430 timer_compare_match_t const match_channel); 431 432 /*******************************************************************************************************************//** 433 * @} (end defgroup GPT) 434 **********************************************************************************************************************/ 435 436 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 437 FSP_FOOTER 438 439 #endif 440
