1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <lib/mtk_init/mtk_init.h> 10 #include <mtk_dcm.h> 11 #include <mtk_dcm_utils.h> 12 dcm_armcore(bool mode)13static void dcm_armcore(bool mode) 14 { 15 dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 16 dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 17 dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 18 } 19 dcm_mcusys(bool on)20static void dcm_mcusys(bool on) 21 { 22 dcm_mp_cpusys_top_adb_dcm(on); 23 dcm_mp_cpusys_top_apb_dcm(on); 24 dcm_mp_cpusys_top_cpubiu_dcm(on); 25 dcm_mp_cpusys_top_misc_dcm(on); 26 dcm_mp_cpusys_top_mp0_qdcm(on); 27 28 /* CPCCFG_REG */ 29 dcm_cpccfg_reg_emi_wfifo(on); 30 dcm_mp_cpusys_top_last_cor_idle_dcm(on); 31 } 32 dcm_stall(bool on)33static void dcm_stall(bool on) 34 { 35 dcm_mp_cpusys_top_core_stall_dcm(on); 36 dcm_mp_cpusys_top_fcm_stall_dcm(on); 37 } 38 check_dcm_state(void)39static bool check_dcm_state(void) 40 { 41 bool ret = true; 42 43 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 44 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 45 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 46 47 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 48 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 49 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 50 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 51 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 52 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 53 ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 54 55 ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 56 ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 57 58 return ret; 59 } 60 dcm_check_state(uintptr_t addr,unsigned int mask,unsigned int compare)61bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare) 62 { 63 return ((mmio_read_32(addr) & mask) == compare); 64 } 65 dcm_set_init(void)66int dcm_set_init(void) 67 { 68 int ret; 69 70 dcm_armcore(true); 71 dcm_mcusys(true); 72 dcm_stall(true); 73 74 if (check_dcm_state() == false) { 75 ERROR("Failed to set default dcm on!!\n"); 76 ret = -1; 77 } else { 78 INFO("%s, dcm pass\n", __func__); 79 ret = 0; 80 } 81 82 return ret; 83 } 84 MTK_PLAT_SETUP_0_INIT(dcm_set_init); 85
