1 /*
2 * Copyright 2017-2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_PXP_H_
10 #define FSL_PXP_H_
11
12 #include "fsl_common.h"
13
14 /* Compatibility macro map. */
15 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
16 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
17 #endif
18
19 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
20 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
21 #endif
22
23 #if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
24 #define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
25 #endif
26
27 #if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
28 #define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
29 #endif
30
31 #if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
32 #define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
33 #endif
34
35 /*!
36 * @addtogroup pxp_driver
37 * @{
38 */
39
40 /*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44 /* PXP global LUT table is 16K. */
45 #define PXP_LUT_TABLE_BYTE (16UL * 1024UL)
46 /* Intenral memory for LUT, the size is 256 bytes. */
47 #define PXP_INTERNAL_RAM_LUT_BYTE (256)
48
49 /*! @name Driver version */
50 /*! @{ */
51 #define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 6, 1))
52 /*! @} */
53
54 /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
55 #if defined(PXP_CTRL_ROT_POS_MASK)
56 #define PXP_SHARE_ROTATE 1
57 #else
58 #define PXP_SHARE_ROTATE 0
59 #endif
60
61 /* This macto indicates whether PXP needs mux the process path. */
62 #if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)
63 #define PXP_USE_PATH 1
64 #else
65 #define PXP_USE_PATH 0
66 #endif
67
68 #if PXP_USE_PATH
69 #define PXP_PATH(mux, sel) (((mux) << 8U) | (sel))
70 #define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U)
71 #define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U)
72 #endif /* PXP_USE_PATH */
73
74 #define PXP_COMBINE_BYTE_TO_WORD(dataAddr) \
75 (((uint32_t)(*(uint8_t *)(dataAddr))) | (((uint32_t)(*(uint8_t *)((dataAddr) + 1U))) << 8U) | (((uint32_t)(*(uint8_t *)((dataAddr) + 2U))) << 16U) | \
76 (((uint32_t)(*(uint8_t *)((dataAddr) + 3U))) << 24U));
77
78 /*! @brief PXP interrupts to enable. */
79 enum _pxp_interrupt_enable
80 {
81 kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. bit 1 */
82 kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set by @ref
83 PXP_SetNextCommand has been loaded. bit 2 */
84 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
85 kPXP_LutDmaLoadInterruptEnable =
86 PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. bit 3 */
87 #endif
88 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
89 kPXP_CompressDoneInterruptEnable =
90 PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U, /*!< Compress done interrupt enable. bit 15 */
91 kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK
92 << 16U, /*!< Input fetch channel 0 completed. bit 16 */
93 kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK
94 << 16U, /*!< Input fetch channel 1 completed. bit 17 */
95 kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK
96 << 16U, /*!< Input store channel 0 completed. bit 18 */
97 kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK
98 << 16U, /*!< Input store channel 1 completed. bit 19 */
99 kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK
100 << 16U, /*!< Dither fetch channel 0 completed. bit 20 */
101 kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK
102 << 16U, /*!< Dither fetch channel 1 completed. bit 21 */
103 kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK
104 << 16U, /*!< Dither store channle 0 completed. bit 22 */
105 kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK
106 << 16U, /*!< Dither store channle 1 completed. bit 23 */
107 kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK
108 << 16U, /*!< WFE-A store channel 0 completed. bit 24 */
109 kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK
110 << 16U, /*!< WFE-A store channel 1 completed. bit 25 */
111 kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK
112 << 16U, /*!< WFE-B store channel 0 completed. bit 26 */
113 kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK
114 << 16U, /*!< WFE-B store channel 1 completed. bit 27 */
115 kPXP_InputStoreInterruptEnable = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U, /*!< Input store completed. bit 28 */
116 kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK
117 << 16U, /*!< Dither store completed. bit 29 */
118 kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U, /*!< WFE-A store completed. bit 30 */
119 kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U, /*!< WFE-B store completed. bit 31 */
120 #endif /* FSL_FEATURE_PXP_V3 */
121 };
122
123 /*!
124 * @brief PXP status flags.
125 *
126 * @note These enumerations are meant to be OR'd together to form a bit mask.
127 */
128 enum _pxp_flags
129 {
130 kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. bit 0 */
131 kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error and processing
132 has been terminated. bit 1*/
133 kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error and processing has
134 been terminated. bit 2 */
135 kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand has been loaded,
136 could set new command. bit 3 */
137 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
138 kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. bit 8 */
139 #endif
140 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
141 kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error and processing
142 has been terminated. bit 9 */
143 kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error and processing has
144 been terminated. bit 10 */
145 #endif
146 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
147 kPXP_CompressDoneFlag = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U, /*!< Compress done. bit 15 */
148 kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK
149 << 16U, /*!< Input fetch channel 0 completed. bit 16 */
150 kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK
151 << 16U, /*!< Input fetch channel 1 completed. bit 17 */
152 kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK
153 << 16U, /*!< Input store channel 0 completed. bit 18 */
154 kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK
155 << 16U, /*!< Input store channel 1 completed. bit 19 */
156 kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK
157 << 16U, /*!< Dither fetch channel 0 completed. bit 20 */
158 kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK
159 << 16U, /*!< Dither fetch channel 1 completed. bit 21 */
160 kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK
161 << 16U, /*!< Dither store channel 0 completed. bit 22 */
162 kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK
163 << 16U, /*!< Dither store channel 1 completed. bit 23 */
164 kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK
165 << 16U, /*!< WFE-A store channel 0 completed. bit 24 */
166 kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK
167 << 16U, /*!< WFE-A store channel 1 completed. bit 25 */
168 kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK
169 << 16U, /*!< WFE-B store channel 0 completed. bit 26 */
170 kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK
171 << 16U, /*!< WFE-B store channel 1 completed. bit 27 */
172 kPXP_InputStoreCompleteFlag = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U, /*!< Input store completed. bit 28 */
173 kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U, /*!< Dither store completed. bit 29 */
174 kPXP_WfeaStoreCompleteFlag = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U, /*!< WFE-A store completed. bit 30 */
175 kPXP_WfebStoreCompleteFlag = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U, /*!< WFE-B store completed. bit 31 */
176 #endif /* FSL_FEATURE_PXP_V3 */
177 };
178
179 #if PXP_USE_PATH
180 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
181 typedef enum _pxp_path
182 {
183 kPXP_Mux0SelectProcessSurfaceEngine = PXP_PATH(0U, 0U), /*!< MUX0 select Process Surface engine. */
184 kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U), /*!< MUX0 select input Fetch engine channel 0. */
185 kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U), /*!< MUX0 select input Fetch engine channel 1. */
186 kPXP_Mux0SelectNone = PXP_PATH(0U, 3U), /*!< MUX0 select no output. */
187 kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U), /*!< MUX1 select input Fetch engine channel 0. */
188 kPXP_Mux1SelectRotation1Engine = PXP_PATH(1U, 1U), /*!< MUX1 select Rotation1 engine output. */
189 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */
190 kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U), /*!< MUX2 select input Fetch engine channel 1. */
191 kPXP_Mux2SelectRotation1Engine = PXP_PATH(2U, 1U), /*!< MUX2 select Rotation1 engine output. */
192 kPXP_Mux2SelectNone = PXP_PATH(2U, 2U), /*!< MUX2 select no output. */
193 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of CSC1 engine. */
194 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of Rotation1 engine. */
195 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */
196 kPXP_Mux5SelectMux1 = PXP_PATH(5U, 0U), /*!< MUX5 select output of MUX1. */
197 kPXP_Mux5SelectAlphaBlending1 = PXP_PATH(5U, 1U), /*!< MUX5 select output of alpha blending / color key 1. */
198 kPXP_Mux5SelectNone = PXP_PATH(5U, 2U), /*!< MUX5 select no output. */
199 kPXP_Mux6SelectAlphaBlending1 = PXP_PATH(6U, 0U), /*!< MUX6 select output of alpha blending / color key 1. */
200 kPXP_Mux6SelectAlphaBlending0 = PXP_PATH(6U, 1U), /*!< MUX6 select output of alpha blending / color key 0. */
201 kPXP_Mux6SelectNone = PXP_PATH(6U, 2U), /*!< MUX6 select no output. */
202 kPXP_Mux7SelectMux5 = PXP_PATH(7U, 0U), /*!< MUX7 select output of MUX5. */
203 kPXP_Mux7SelectCsc2Engine = PXP_PATH(7U, 1U), /*!< MUX7 select output of CSC2 engine. */
204 kPXP_Mux7SelectNone = PXP_PATH(7U, 2U), /*!< MUX7 select no output. */
205 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */
206 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */
207 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */
208 kPXP_Mux9SelectMux7 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX7. */
209 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */
210 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */
211 kPXP_Mux10SelectMux7 = PXP_PATH(10U, 0U), /*!< MUX10 select output of MUX7. */
212 kPXP_Mux10SelectLut = PXP_PATH(10U, 1U), /*!< MUX10 select output of LUT. */
213 kPXP_Mux10SelectNone = PXP_PATH(10U, 2U), /*!< MUX10 select no output. */
214 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */
215 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */
216 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */
217 kPXP_Mux12SelectMux10 = PXP_PATH(12U, 0U), /*!< MUX12 select output of MUX10. */
218 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */
219 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */
220 kPXP_Mux13SelectNone = PXP_PATH(13U, 0U), /*!< MUX13 select no output. */
221 kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U), /*!< MUX13 select input Fetch engine channel 1. */
222 kPXP_Mux14SelectRotation0Engine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Rotation0 engine. */
223 kPXP_Mux14SelectMux11 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX11. */
224 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */
225 kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U), /*!< MUX15 select input Fetch engine channel 0. */
226 kPXP_Mux15SelectMux10 = PXP_PATH(15U, 1U), /*!< MUX15 select output of MUX10. */
227 kPXP_Mux15SelectNone = PXP_PATH(15U, 2U), /*!< MUX15 select no output. */
228 kPXP_Mux16SelectAluA = PXP_PATH(16U, 0U), /*!< MUX16 select output of ALU A. */
229 kPXP_Mux16SelectOutput = PXP_PATH(16U, 1U), /*!< MUX16 select output of legacy output. */
230 kPXP_Mux16SelectAluB = PXP_PATH(16U, 2U), /*!< MUX16 select output of ALU B. */
231 kPXP_Mux16SelectNone = PXP_PATH(16U, 3U), /*!< MUX16 select no output. */
232 kPXP_Mux17SelectAluA = PXP_PATH(17U, 0U), /*!< MUX17 select output of ALU A. */
233 kPXP_Mux17SelectAluB = PXP_PATH(17U, 1U), /*!< MUX17 select output of ALU B. */
234 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */
235 } pxp_path_t;
236 #else
237 typedef enum _pxp_path
238 {
239 kPXP_Mux0SelectFetchDataArray = PXP_PATH(0U, 0U), /*!< MUX0 select Fetch Data Array. */
240 kPXP_Mux0SelectAlu = PXP_PATH(0U, 1U), /*!< MUX0 select output of ALU. */
241 kPXP_Mux0SelectNone = PXP_PATH(0U, 2U), /*!< MUX0 select no output. */
242 kPXP_Mux1SelectLut = PXP_PATH(1U, 0U), /*!< MUX1 select output of LUT. */
243 kPXP_Mux1SelectMux0 = PXP_PATH(1U, 1U), /*!< MUX1 select output of MUX0. */
244 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */
245 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of Rotation1 engine. */
246 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of CSC1 engine. */
247 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */
248 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */
249 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */
250 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */
251 kPXP_Mux9SelectMux0 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX0. */
252 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */
253 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */
254 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */
255 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */
256 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */
257 kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U), /*!< MUX12 select output of Rotation0 engine. */
258 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */
259 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */
260 kPXP_Mux14SelectDitherEngine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Dither engine. */
261 kPXP_Mux14SelectMux12 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX12. */
262 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */
263 kPXP_Mux16SelectOutputBuffer = PXP_PATH(16U, 0U), /*!< MUX16 select output of output buffer. */
264 kPXP_Mux16SelectStoreEngine = PXP_PATH(16U, 1U), /*!< MUX16 select output of store engine. */
265 kPXP_Mux16SelectNone = PXP_PATH(16U, 2U), /*!< MUX16 select no output. */
266 kPXP_Mux17SelectOutputBuffer = PXP_PATH(17U, 0U), /*!< MUX17 select output of output buffer. */
267 kPXP_Mux17SelectStoreEngine = PXP_PATH(17U, 1U), /*!< MUX17 select output of store engine. */
268 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */
269 } pxp_path_t;
270 #endif /* FSL_FEATURE_PXP_V3 */
271 #endif /* PXP_USE_PATH */
272
273 /*! @brief PXP output flip mode. */
274 typedef enum _pxp_flip_mode
275 {
276 kPXP_FlipDisable = 0U, /*!< Flip disable. */
277 kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */
278 kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */
279 kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */
280 } pxp_flip_mode_t;
281
282 /*! @brief PXP rotate mode. */
283 typedef enum _pxp_rotate_position
284 {
285 kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */
286 kPXP_RotateProcessSurface, /*!< Rotate the process surface. */
287 } pxp_rotate_position_t;
288
289 /*! @brief PXP rotate degree. */
290 typedef enum _pxp_rotate_degree
291 {
292 kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */
293 kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */
294 kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */
295 kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */
296 } pxp_rotate_degree_t;
297
298 /*! @brief PXP interlaced output mode. */
299 typedef enum _pxp_interlaced_output_mode
300 {
301 kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */
302 kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */
303 kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */
304 kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */
305 } pxp_interlaced_output_mode_t;
306
307 /*! @brief PXP output buffer format. */
308 typedef enum _pxp_output_pixel_format
309 {
310 kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
311 kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
312 kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */
313 kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
314 kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
315 kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
316 kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
317 kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
318 kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
319 kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
320 kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
321 kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
322 kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
323 kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
324 kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
325 kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
326 kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
327 } pxp_output_pixel_format_t;
328
329 /*! @brief PXP output buffer configuration. */
330 typedef struct _pxp_output_buffer_config
331 {
332 pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */
333 pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */
334 uint32_t buffer0Addr; /*!< Output buffer 0 address. */
335 uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or
336 field 1 in output interlaced mode. */
337 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
338 uint16_t width; /*!< Pixels per line. */
339 uint16_t height; /*!< How many lines in output buffer. */
340 } pxp_output_buffer_config_t;
341
342 /*! @brief PXP process surface buffer pixel format. */
343 typedef enum _pxp_ps_pixel_format
344 {
345 #if (!(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)) && \
346 (!(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3))
347 kPXP_PsPixelFormatARGB8888 = 0x4, /*!< 32-bit pixels with alpha(when participates in blend with
348 alpha surface uses pixel format that has alpha value) or without alpha (unpacked 24-bit format) */
349 kPXP_PsPixelFormatARGB1555 = 0xC, /*!< 16-bit pixels with alpha(when participates in blend with
350 alpha surface uses pixel format that has alpha value) or without alpha. */
351 kPXP_PsPixelFormatARGB4444 = 0xD, /*!< 16-bit pixels with alpha(when participates in blend with
352 alpha surface uses pixel format that has alpha value) or without alpha. */
353 #else
354 kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
355 kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
356 kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
357 #endif
358 kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
359 kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
360 kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
361 kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
362 kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
363 kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
364 kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
365 kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
366 kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
367 kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
368 kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */
369 kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */
370 #if !(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)
371 #if !(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
372 kPXP_PsPixelFormatRGBA8888 = 0x24, /*!< 32-bit pixels with alpha at low 8-bit */
373 kPXP_PsPixelFormatRGBA5551 = 0x2C, /*!< 16-bit pixels with alpha at low 1-bit. */
374 kPXP_PsPixelFormatRGBA4444 = 0x2D, /*!< 16-bit pixels with alpha at low 4-bit. */
375 #endif
376 #endif
377 } pxp_ps_pixel_format_t;
378
379 /*! @brief PXP process surface buffer YUV format. */
380 typedef enum _pxp_ps_yuv_format
381 {
382 kPXP_PsYUVFormatYUV = 0U, /*!< YUV format. */
383 kPXP_PsYUVFormatYCbCr, /*!< YCbCr format. */
384 } pxp_ps_yuv_format_t;
385
386 /*! @brief PXP process surface buffer configuration. */
387 typedef struct _pxp_ps_buffer_config
388 {
389 pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */
390 bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */
391 uint32_t bufferAddr; /*!< Input buffer address for the first panel. */
392 uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */
393 uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */
394 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
395 } pxp_ps_buffer_config_t;
396
397 /*! @brief PXP alpha surface buffer pixel format. */
398 typedef enum _pxp_as_pixel_format
399 {
400 kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
401 kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
402 kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
403 kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
404 kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
405 kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
406 kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
407 #if !(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)
408 #if !(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
409 kPXP_AsPixelFormatRGBA8888 = 0x1, /*!< 32-bit pixels with alpha at low 8-bit. */
410 kPXP_AsPixelFormatRGBA5551 = 0xA, /*!< 16-bit pixels with alpha at low 1-bit. */
411 kPXP_AsPixelFormatRGBA4444 = 0xB, /*!< 16-bit pixels with alpha at low 4-bit. */
412 #endif
413 #endif
414 } pxp_as_pixel_format_t;
415
416 /*! @brief PXP alphs surface buffer configuration. */
417 typedef struct _pxp_as_buffer_config
418 {
419 pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */
420 uint32_t bufferAddr; /*!< Input buffer address. */
421 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
422 } pxp_as_buffer_config_t;
423
424 /*!
425 * @brief PXP alpha mode during blending.
426 */
427 typedef enum _pxp_alpha_mode
428 {
429 kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
430 kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
431 kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
432 alpha value will be used for blend, for example, pixel alpha set
433 set to 200, user defined alpha set to 100, then the reault alpha
434 is 200 * 100 / 255. */
435 kPXP_AlphaRop /*!< Raster operation. */
436 } pxp_alpha_mode_t;
437
438 /*!
439 * @brief PXP ROP mode during blending.
440 *
441 * Explanation:
442 * - AS: Alpha surface
443 * - PS: Process surface
444 * - nAS: Alpha surface NOT value
445 * - nPS: Process surface NOT value
446 */
447 typedef enum _pxp_rop_mode
448 {
449 kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */
450 kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
451 kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
452 kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */
453 kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
454 kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
455 kPXP_RopNotCopyAs = 0x6, /*!< nAS. */
456 kPXP_RopNot = 0x7, /*!< nPS. */
457 kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
458 kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
459 kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */
460 kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */
461 } pxp_rop_mode_t;
462
463 /*!
464 * @brief PXP alpha surface blending configuration.
465 */
466 typedef struct _pxp_as_blend_config
467 {
468 uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref
469 kPXP_AlphaRop. */
470 bool invertAlpha; /*!< Set true to invert the alpha. */
471 pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */
472 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */
473 } pxp_as_blend_config_t;
474
475 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
476 /*!
477 * @brief PXP secondary alpha surface blending engine configuration.
478 */
479 typedef struct _pxp_as_blend_secondary_config
480 {
481 bool invertAlpha; /*!< Set true to invert the alpha. */
482 bool ropEnable; /*!< Enable rop mode. */
483 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when ropEnable is true. */
484 } pxp_as_blend_secondary_config_t;
485 #endif /* FSL_FEATURE_PXP_V3 */
486
487 /*! @brief PXP process block size. */
488 typedef enum _pxp_block_size
489 {
490 kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */
491 kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */
492 } pxp_block_size_t;
493
494 /*! @brief PXP CSC1 mode. */
495 typedef enum _pxp_csc1_mode
496 {
497 kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */
498 kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */
499 } pxp_csc1_mode_t;
500
501 /*! @brief PXP CSC2 mode. */
502 typedef enum _pxp_csc2_mode
503 {
504 kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */
505 kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */
506 kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */
507 kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */
508 } pxp_csc2_mode_t;
509
510 /*!
511 * @brief PXP CSC2 configuration.
512 *
513 * Converting from YUV/YCbCr color spaces to the RGB color space uses the
514 * following equation structure:
515 *
516 * R = A1(Y+D1) + A2(U+D2) + A3(V+D3)
517 * G = B1(Y+D1) + B2(U+D2) + B3(V+D3)
518 * B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
519 *
520 * Converting from the RGB color space to YUV/YCbCr color spaces uses the
521 * following equation structure:
522 *
523 * Y = A1*R + A2*G + A3*B + D1
524 * U = B1*R + B2*G + B3*B + D2
525 * V = C1*R + C2*G + C3*B + D3
526 */
527 typedef struct _pxp_csc2_config
528 {
529 pxp_csc2_mode_t mode; /*!< Convertion mode. */
530 float A1; /*!< A1. */
531 float A2; /*!< A2. */
532 float A3; /*!< A3. */
533 float B1; /*!< B1. */
534 float B2; /*!< B2. */
535 float B3; /*!< B3. */
536 float C1; /*!< C1. */
537 float C2; /*!< C2. */
538 float C3; /*!< C3. */
539 int16_t D1; /*!< D1. */
540 int16_t D2; /*!< D2. */
541 int16_t D3; /*!< D3. */
542 } pxp_csc2_config_t;
543
544 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
545 /*! @brief PXP LUT lookup mode. */
546 typedef enum _pxp_lut_lookup_mode
547 {
548 kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT
549 for indirect cached 128KB lookup. */
550 kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT.
551 Only third data path byte is tranformed. */
552 kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT
553 selected by @ref PXP_Select8kLutBank. */
554 kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */
555 } pxp_lut_lookup_mode_t;
556
557 /*! @brief PXP LUT output mode. */
558 typedef enum _pxp_lut_out_mode
559 {
560 kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */
561 kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */
562 kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */
563 } pxp_lut_out_mode_t;
564
565 /*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */
566 typedef enum _pxp_lut_8k_bank
567 {
568 kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */
569 kPXP_Lut8kBank1, /*!< The second 8K bank used. */
570 } pxp_lut_8k_bank_t;
571
572 /*! @brief PXP LUT configuration. */
573 typedef struct _pxp_lut_config
574 {
575 pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */
576 pxp_lut_out_mode_t outMode; /*!< Out mode. */
577 uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */
578 } pxp_lut_config_t;
579 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
580
581 /*! @brief PXP internal memory. */
582 typedef enum _pxp_ram
583 {
584 kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */
585 kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */
586 kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */
587 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
588 kPXP_RamDither0Err0 = 1U, /*!< Dither 0 ERR0 memory. */
589 kPXP_RamDither0Err1 = 2U, /*!< Dither 0 ERR1 memory. */
590 kPXP_RamAluA = 5U, /*!< ALU A instr memory. */
591 kPXP_RamAluB = 6U, /*!< ALU B instr memory. */
592 kPXP_WfeAFetch = 7U, /*!< WFE-A fetch memory. */
593 kPXP_WfeBFetch = 8U, /*!< WFE-B fetch memory. */
594 #endif /* FSL_FEATURE_PXP_V3 */
595 } pxp_ram_t;
596
597 /*! @brief PXP dither mode. */
598 enum _pxp_dither_mode
599 {
600 kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */
601 kPXP_DitherFloydSteinberg = 1U, /*!< Floyd-Steinberg. For dither engine 0 only. */
602 kPXP_DitherAtkinson = 2U, /*!< Atkinson. For dither engine 0 only. */
603 kPXP_DitherOrdered = 3U, /*!< Ordered dither. */
604 kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */
605 kPXP_DitherSierra = 5U, /*!< Sierra. For dither engine 0 only. */
606 };
607
608 /*! @brief PXP dither LUT mode. */
609 enum _pxp_dither_lut_mode
610 {
611 kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */
612 kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode
613 or Atkinson mode, which are not supported by current PXP module. */
614 kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */
615 };
616
617 /*! @brief PXP dither matrix size. */
618 enum _pxp_dither_matrix_size
619 {
620 kPXP_DitherMatrix4 = 0, /*!< The dither index matrix is 4x4. */
621 kPXP_DitherMatrix8, /*!< The dither index matrix is 8x8. */
622 kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */
623 };
624
625 /*! @brief PXP dither final LUT data. */
626 typedef struct _pxp_dither_final_lut_data
627 {
628 uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */
629 uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */
630 uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */
631 uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */
632 } pxp_dither_final_lut_data_t;
633
634 /*! @brief PXP dither configuration. */
635 typedef struct _pxp_dither_config
636 {
637 uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */
638 uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */
639 uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */
640 uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */
641 uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */
642 uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */
643 uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */
644 uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref
645 kPXP_DitherLutOff
646 if any dither engine uses @ref kPXP_DitherOrdered mode. */
647 uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref
648 _pxp_dither_matrix_size. */
649 uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref
650 _pxp_dither_matrix_size. */
651 uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref
652 _pxp_dither_matrix_size. */
653 uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */
654 uint32_t : 8;
655 } pxp_dither_config_t;
656
657 /*!
658 * @brief Porter Duff factor mode.
659 * @anchor pxp_porter_duff_factor_mode
660 */
661 enum
662 {
663 kPXP_PorterDuffFactorOne = 0U, /*!< Use 1. */
664 kPXP_PorterDuffFactorZero, /*!< Use 0. */
665 kPXP_PorterDuffFactorStraight, /*!< Use straight alpha. */
666 kPXP_PorterDuffFactorInversed, /*!< Use inversed alpha. */
667 };
668
669 /*!
670 * @brief Porter Duff global alpha mode.
671 * @anchor pxp_porter_duff_global_alpha_mode
672 */
673 enum
674 {
675 kPXP_PorterDuffGlobalAlpha = 0U, /*!< Use global alpha. */
676 kPXP_PorterDuffLocalAlpha, /*!< Use local alpha in each pixel. */
677 kPXP_PorterDuffScaledAlpha, /*!< Use global alpha * local alpha. */
678 };
679
680 /*!
681 * @brief Porter Duff alpha mode.
682 * @anchor pxp_porter_duff_alpha_mode
683 */
684 enum
685 {
686 kPXP_PorterDuffAlphaStraight = 0U, /*!< Use straight alpha, s0_alpha' = s0_alpha. */
687 kPXP_PorterDuffAlphaInversed /*!< Use inversed alpha, s0_alpha' = 0xFF - s0_alpha. */
688 };
689
690 /*!
691 * @brief Porter Duff color mode.
692 * @anchor pxp_porter_duff_color_mode
693 */
694 enum
695 {
696 kPXP_PorterDuffColorStraight = 0, /*!< @deprecated Use kPXP_PorterDuffColorNoAlpha. */
697 kPXP_PorterDuffColorInversed = 1, /*!< @deprecated Use kPXP_PorterDuffColorWithAlpha. */
698 kPXP_PorterDuffColorNoAlpha = 0, /*!< s0_pixel' = s0_pixel. */
699 kPXP_PorterDuffColorWithAlpha = 1, /*!< s0_pixel' = s0_pixel * s0_alpha". */
700 };
701
702 /*! @brief PXP Porter Duff configuration. */
703 typedef struct
704 {
705 uint32_t enable : 1; /*!< Enable or disable Porter Duff. */
706 uint32_t srcFactorMode : 2; /*!< Source layer (or AS, s1) factor mode, see @ref pxp_porter_duff_factor_mode. */
707 uint32_t dstGlobalAlphaMode : 2; /*!< Destination layer (or PS, s0) global alpha mode, see
708 @ref pxp_porter_duff_global_alpha_mode. */
709 uint32_t dstAlphaMode : 1; /*!< Destination layer (or PS, s0) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
710 uint32_t dstColorMode : 1; /*!< Destination layer (or PS, s0) color mode, see @ref pxp_porter_duff_color_mode. */
711 uint32_t : 1;
712 uint32_t dstFactorMode : 2; /*!< Destination layer (or PS, s0) factor mode, see @ref pxp_porter_duff_factor_mode. */
713 uint32_t srcGlobalAlphaMode : 2; /*!< Source layer (or AS, s1) global alpha mode, see
714 @ref pxp_porter_duff_global_alpha_mode. */
715 uint32_t srcAlphaMode : 1; /*!< Source layer (or AS, s1) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
716 uint32_t srcColorMode : 1; /*!< Source layer (or AS, s1) color mode, see @ref pxp_porter_duff_color_mode. */
717 uint32_t : 2;
718 uint32_t dstGlobalAlpha : 8; /*!< Destination layer (or PS, s0) global alpha value, 0~255. */
719 uint32_t srcGlobalAlpha : 8; /*!< Source layer (or AS, s1) global alpha value, 0~255. */
720 } pxp_porter_duff_config_t;
721
722 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
723 typedef enum _pxp_porter_duff_blend_mode
724 {
725 kPXP_PorterDuffSrc = 0, /*!< Source Only */
726 kPXP_PorterDuffAtop, /*!< Source Atop */
727 kPXP_PorterDuffOver, /*!< Source Over */
728 kPXP_PorterDuffIn, /*!< Source In. */
729 kPXP_PorterDuffOut, /*!< Source Out. */
730 kPXP_PorterDuffDst, /*!< Destination Only. */
731 kPXP_PorterDuffDstAtop, /*!< Destination Atop. */
732 kPXP_PorterDuffDstOver, /*!< Destination Over. */
733 kPXP_PorterDuffDstIn, /*!< Destination In. */
734 kPXP_PorterDuffDstOut, /*!< Destination Out. */
735 kPXP_PorterDuffXor, /*!< XOR. */
736 kPXP_PorterDuffClear, /*!< Clear. */
737 kPXP_PorterDuffMax,
738 } pxp_porter_duff_blend_mode_t;
739
740 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
741 typedef struct _pxp_pic_copy_config
742 {
743 uint32_t srcPicBaseAddr; /*!< Source picture base address. */
744 uint16_t srcPitchBytes; /*!< Pitch of the source buffer. */
745 uint16_t srcOffsetX; /*!< Copy position in source picture. */
746 uint16_t srcOffsetY; /*!< Copy position in source picture. */
747 uint32_t destPicBaseAddr; /*!< Destination picture base address. */
748 uint16_t destPitchBytes; /*!< Pitch of the destination buffer. */
749 uint16_t destOffsetX; /*!< Copy position in destination picture. */
750 uint16_t destOffsetY; /*!< Copy position in destination picture. */
751 uint16_t width; /*!< Pixel number each line to copy. */
752 uint16_t height; /*!< Lines to copy. */
753 pxp_as_pixel_format_t pixelFormat; /*!< Buffer pixel format. */
754 } pxp_pic_copy_config_t;
755
756 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
757
758 /*!
759 * @brief PXP process engine enumeration
760 */
761 typedef enum _pxp_process_engine_name
762 {
763 kPXP_PsAsOutEngine = PXP_CTRL_ENABLE_PS_AS_OUT_MASK,
764 kPXP_DitherEngine = PXP_CTRL_ENABLE_DITHER_MASK,
765 kPXP_WfeaEngine = PXP_CTRL_ENABLE_WFE_A_MASK,
766 kPXP_WfebEngine = PXP_CTRL_ENABLE_WFE_B_MASK,
767 kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK,
768 kPXP_Alpha1Engine = PXP_CTRL_ENABLE_ALPHA_B_MASK,
769 kPXP_Csc2Engine = PXP_CTRL_ENABLE_CSC2_MASK,
770 kPXP_LutEngine = PXP_CTRL_ENABLE_LUT_MASK,
771 kPXP_Rotate0Engine = PXP_CTRL_ENABLE_ROTATE0_MASK,
772 kPXP_Rotate1Engine = PXP_CTRL_ENABLE_ROTATE1_MASK,
773 } pxp_process_engine_name_t;
774
775 /* Fetch engine configuration. */
776 /*!
777 * @brief PXP fetch engine enumeration
778 *
779 * There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine,
780 * whose registers are reserved from developer.
781 */
782 typedef enum _pxp_fetch_engine_name
783 {
784 kPXP_FetchInput,
785 kPXP_FetchDither,
786 } pxp_fetch_engine_name_t;
787
788 /*! @brief PXP fetch engine interface mode with the upstream store engine. */
789 typedef enum _pxp_fetch_interface_mode
790 {
791 kPXP_FetchModeNormal = 0U,
792 kPXP_FetchModeHandshake = 0x1U,
793 kPXP_FetchModeBypass = 0x2U,
794 } pxp_fetch_interface_mode_t;
795
796 /*! @brief PXP fetch/store engine burst length for scanline mode. */
797 typedef enum _pxp_scanline_burst
798 {
799 kPXP_Scanline8bytes,
800 kPXP_Scanline16bytes,
801 kPXP_Scanline32bytes,
802 kPXP_Scanline64bytes,
803 } pxp_scanline_burst_t;
804
805 /*! @brief PXP fetch engine block configuration. */
806 typedef struct _pxp_block_format_config
807 {
808 bool
809 enableblock; /*!< Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or
810 flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If
811 LUT processing is in the path between the fetch and store engind, block mode must be enabled. */
812 bool blockSize16; /*!< Enable to use 16*16 block, otherwise it will be 8*8 block. */
813 pxp_scanline_burst_t burstLength; /*!< When using scanline mode, configure this for burst length. */
814 } pxp_block_config_t;
815
816 /*!
817 * @brief PXP fetch/store engine input/output active bits configuration.
818 *
819 * Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input
820 * mode. And expand configuration will have no effect.
821 */
822 typedef enum _pxp_activeBits
823 {
824 kPXP_Active8Bits = 0x0,
825 kPXP_Active16Bits = 0x1,
826 kPXP_Active32Bits = 0x2,
827 kPXP_Active64Bits = 0x3,
828 } pxp_active_bits_t;
829
830 /*! @brief PXP fetch engine output word order when using 2 channels for 64-bit mode. */
831 typedef enum _pxp_fetch_output_word_order
832 {
833 kPXP_FetchOutputChannel1channel0 = 0x0, /*!< In 64bit mode, channel 1 output high byte. */
834 kPXP_FetchOutputChannel0channel1 = 0x1, /*!< In 64bit mode, channel 0 output high byte. */
835 } pxp_fetch_output_word_order_t;
836
837 /*!
838 * @brief PXP fetch engine shift component configuration.
839 *
840 * Fetch engine can divded each word into 4 components and shift them.
841 */
842 typedef struct _pxp_fetch_shift_component
843 {
844 uint8_t offset;
845 uint8_t width;
846 } pxp_fetch_shift_component_t;
847
848 /*!
849 * @brief PXP fetch engine shift configuration.
850 *
851 * Fetch engine can divded each word into 4 components and shift them.
852 * For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16,
853 * OFFSET3=24, WIDTH0/1/2/3=8
854 */
855 typedef struct _pxp_fetch_shift_config
856 {
857 bool shiftBypass; /* Bypass the shift */
858 pxp_fetch_shift_component_t component0;
859 pxp_fetch_shift_component_t component1;
860 pxp_fetch_shift_component_t component2;
861 pxp_fetch_shift_component_t component3;
862 } pxp_fetch_shift_config_t;
863
864 /*! @brief PXP fetch engine input pixel format. */
865 typedef enum _pxp_fetch_pixel_format
866 {
867 kPXP_FetchFormatRGB565 = 0x0,
868 kPXP_FetchFormatRGB555 = 0x1,
869 kPXP_FetchFormatARGB1555 = 0x2,
870 kPXP_FetchFormatRGB444 = 0x3,
871 kPXP_FetchFormatARGB4444 = 0x4,
872 kPXP_FetchFormatYUYVorYVYU = 0x5,
873 kPXP_FetchFormatUYVYorVYUY = 0x6,
874 kPXP_FetchFormatYUV422_2P = 0x7,
875 } pxp_fetch_pixel_format_t;
876
877 /*! @brief PXP fetch engine configuration for one of the channel. */
878 typedef struct _pxp_fetch_engine_config
879 {
880 bool channelEnable; /*!< Enable channel. */
881 /* Address configuration */
882 uint32_t inputBaseAddr0; /*!< The input base address. Used for Y plane input when pixel format is YUV422_2p. */
883 uint32_t inputBaseAddr1; /*!< Must configure this for UV plane when input pixel format is YUV422_2p. */
884 /* Size configuration */
885 uint16_t totalHeight; /*!< Total height for the actual fetch size. */
886 uint16_t totalWidth; /*!< Total width for the actual fetch size. */
887 uint16_t pitchBytes; /*!< Channel input pitch */
888 uint16_t ulcX; /*!< X coordinate of upper left coordinate in pixels of the active area of the total input memory */
889 uint16_t ulcY; /*!< Y coordinate of upper left coordinate in pixels of the active area of the total input memory */
890 uint16_t lrcX; /*!< X coordinate of Lower right coordinate in pixels of the active area of the total input memory */
891 uint16_t lrcY; /*!< Y coordinate of Lower right coordinate in pixels of the active area of the total input memory */
892 uint32_t backGroundColor; /*!< Pixel value of the background color for the space outside the active area. */
893 /* Interface configuration */
894 pxp_fetch_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake */
895 /* Pixel configuration */
896 pxp_active_bits_t activeBits; /*!< Input active bits. */
897 pxp_fetch_pixel_format_t pixelFormat; /*!< Input pixel fetch format */
898 bool expandEnable; /*!< If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at
899 the output. */
900 /* Fetch format configuration */
901 pxp_flip_mode_t flipMode; /*!< Flip the fetched input. */
902 pxp_rotate_degree_t rotateDegree; /*!< Rotate the fetched input. */
903 pxp_block_config_t
904 fetchFormat; /*!< Block mode configuration. Make sure to enable block if rotate or flip mode is enabled. */
905 /* Output configuration. */
906 pxp_fetch_shift_config_t shiftConfig; /*!< Shift operation configuration. */
907 pxp_fetch_output_word_order_t wordOrder; /*!< Output word order when using 2 channels for 64-bit mode. */
908 } pxp_fetch_engine_config_t;
909
910 /* Store engine configuration. */
911
912 /*!
913 * @brief PXP store engine enumeration
914 *
915 * There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine,
916 * whose registers are reserved from developer.
917 */
918 typedef enum _pxp_store_engine_name
919 {
920 kPXP_StoreInput,
921 kPXP_StoreDither,
922 } pxp_store_engine_name_t;
923
924 /*! @brief PXP store engine interface mode with the downstream fetch engine. */
925 typedef enum _pxp_store_interface_mode
926 {
927 kPXP_StoreModeBypass = 0x20U, /*!< Store engine output the input data, after the shift function directly to the
928 downstream Fetch Engine. */
929 kPXP_StoreModeNormal = 0x40U, /*!< Store engine stores the input data to memory. */
930 kPXP_StoreModeHandshake = 0x43U, /*!< Downstream fetch engine fetch data per scanline from memory using buffer
931 sharing with store engine. */
932 kPXP_StoreModeDual = 0x60U, /*!< Store engine outputs data directly to downstream fetch engine(Bypass) but also
933 storing it to memory at the same time. */
934 } pxp_store_interface_mode_t;
935
936 /*! @brief PXP store engine YUV output mode. */
937 typedef enum _pxp_store_yuv_mode
938 {
939 kPXP_StoreYUVDisable = 0U, /*!< Do not output YUV pixel format. */
940 kPXP_StoreYUVPlane1 =
941 0x1U, /*!< Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel
942 component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}. */
943 kPXP_StoreYUVPlane2 =
944 0x2U, /*!< Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel
945 component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}. */
946 } pxp_store_yuv_mode_t;
947
948 /*! @brief Shift configuration for PXP store engine. */
949 typedef struct _pxp_store_shift_config
950 {
951 /* Data/Flag shift */
952 bool shiftBypass; /*!< Bypass the data shift */
953 uint64_t *pDataShiftMask; /*!< Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then
954 shifted according to width. */
955 uint8_t *pDataShiftWidth; /*!< Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for
956 shift width. */
957 uint8_t *pFlagShiftMask; /*!< Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then
958 shifted according to width. */
959 uint8_t *pFlagShiftWidth; /*!< Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for
960 shift width. */
961 } pxp_store_shift_config_t;
962
963 /*! @brief PXP store engine configuration for one of the channel. */
964 typedef struct _pxp_store_engine_config
965 {
966 bool channelEnable; /*!< Enable channel. */
967 /* Address configuration */
968 uint32_t outputBaseAddr0; /*!< The channel 0 output address if using 2 channels. If using 1 channel(must be channel
969 0) and YUV422_2p output format, is for Y plane address. */
970 uint32_t outputBaseAddr1; /*!< The channel 1 output address if using 2 channels. If using 1 channel(must be channel
971 0) and YUV422_2p output format, is for UV plane address. */
972 /* Size configuration */
973 uint16_t totalHeight; /*!< Total height for the actual store size. */
974 uint16_t totalWidth; /*!< Total width for the actual store size. */
975 uint16_t pitchBytes; /*!< Channel input pitch */
976 /* Interface configuration */
977 pxp_store_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use
978 the same mode if both enabled. */
979 /* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When
980 block is disabled, the scanline can only be 1. TODO no need now. */
981 /* Pixel configuration */
982 pxp_active_bits_t activeBits; /*!< Output active bits. */
983 pxp_store_yuv_mode_t yuvMode; /*!< Whether to output YUV pixel format. */
984 /* Fixed data configuration, only apply for channel 0. */
985 bool useFixedData; /*!< Whether to use fixed value for the output data. Can be used to write fixed value to specific
986 memory location for memory initialization. */
987 uint32_t fixedData; /*!< The value of the fixed data. */
988 /* Data packing */
989 bool packInSelect; /*!< When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select
990 high 32 bit, otherwise all 64-bit of data will be selected. */
991 /* Data store format */
992 pxp_block_config_t storeFormat; /*!< The format to store data, block or otherwise. */
993 pxp_store_shift_config_t shiftConfig; /*!< Shift operation configuration. */
994 } pxp_store_engine_config_t;
995
996 /* Pre-dither CFA engine configuration */
997
998 /*! @brief PXP pre-dither CFA engine input pixel format. */
999 typedef enum _pxp_cfa_input_format
1000 {
1001 kPXP_CfaRGB888,
1002 kPXP_CfaRGB444,
1003 } pxp_cfa_input_format_t;
1004
1005 /*! @brief PXP pre-dither CFA engine configuration. */
1006 typedef struct _pxp_cfa_config
1007 {
1008 bool bypass; /*!< Bypass the CFA process */
1009 pxp_cfa_input_format_t pixelInFormat; /*!< The pixel input format for CFA. */
1010 uint8_t arrayWidth; /*!< CFA array vertical size in pixels, min 3 max 15. */
1011 uint8_t arrayHeight; /*!< CFA array horizontal size in pixels, min 3 max 15. */
1012 uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the dither fetch engine
1013 and dither engine. */
1014 uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the dither fetch engine and
1015 dither engine. */
1016 uint32_t *cfaValue; /*!< Pointer to the value for the CFA array. 2-bit per component: 00-R,01-G,10-B,11-W. For a 4x4
1017 array, 32 bits are need. */
1018 } pxp_cfa_config_t;
1019
1020 /* Histogram configuration and status */
1021
1022 /*! @brief PXP histogram mask condition. */
1023 typedef enum _pxp_histogram_mask_condition
1024 {
1025 kPXP_HistogramMaskEqual = 0x0U, /*!< Value that equal to value0 will pass the mask operation. */
1026 kPXP_HistogramMaskNotequal = 0x1U, /*!< Value that not equal to value0 will pass the mask operation. */
1027 kPXP_HistogramMaskIn = 0x2U, /*!< Value that within the range of value0-value1 will pass the mask operation. */
1028 kPXP_HistogramMaskOut = 0x3U, /*!< Value that without the range of value0-value1 will pass the mask operation. */
1029 } pxp_histogram_mask_condition_t;
1030
1031 /*! @brief PXP Histogram configuration. */
1032 typedef struct _pxp_histogram_config
1033 {
1034 bool enable; /*!< Enable histogram process. */
1035 uint8_t *pParamValue; /*!< Pointer to the 62(2+4+8+16+32) byte of param value for 2-level, 4-level.....32-level
1036 parameters. Only low 5-bit of each byte is valid. */
1037 uint8_t lutValueOffset; /*!< The starting bit position of the LUT value. */
1038 uint8_t lutValueWidth; /*!< The bit width of the LUT value, should be no more than 6 bits since only 63 LUTs are
1039 supported. */
1040 /* Mask configuration */
1041 bool enableMask; /*!< Enable mask operation. */
1042 uint8_t maskValue0; /*!< Value 0 for the condition judgement. */
1043 uint8_t maskValue1; /*!< Value 1 for the condition judgement. */
1044 uint8_t maskOffset; /*!< The starting bit position of the field to be checked against mask condition. */
1045 uint8_t maskWidth; /*!< The width of the field to be checked against mask condition. */
1046 pxp_histogram_mask_condition_t condition; /*!< The mask condition. */
1047 /* Size configuration */
1048 uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the output of legacy flow
1049 or the WFE-A/B engine. */
1050 uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the output of legacy flow or
1051 the WFE-A/B engine. */
1052 } pxp_histogram_config_t;
1053
1054 /*! @brief PXP Histogram mask result. */
1055 typedef struct _pxp_histogram_mask_result
1056 {
1057 uint32_t pixelCount; /*!< The total count of the pixels that pass the mask(collided pixels). */
1058 uint32_t minX; /*!< The x offset of the ULC of the minimal histogram that covers all passed pixels. */
1059 uint32_t minY; /*!< The y offset of the ULC of the minimal histogram that covers all passed pixels. */
1060 uint32_t maxX; /*!< The x offset of the LRC of the minimal histogram that covers all passed pixels. */
1061 uint32_t maxY; /*!< The y offset of the LRC of the minimal histogram that covers all passed pixels. */
1062 uint64_t lutlist; /*!< The 64-bit LUT list of collided pixels, if pixel of LUT17 is collided, bit17 in the list is
1063 set. */
1064 } pxp_histogram_mask_result_t;
1065
1066 /*! @brief PXP Histogram operation result flags. */
1067 enum _pxp_histgram_flags
1068 {
1069 kPXP_Histogram2levelMatch = 1 << 0U, /* Bitmap pixels are fully contained within the HIST2 histogram. */
1070 kPXP_Histogram4levelMatch = 1 << 1U, /* Bitmap pixels are fully contained within the HIST4 histogram. */
1071 kPXP_Histogram8levelMatch = 1 << 2U, /* Bitmap pixels are fully contained within the HIST8 histogram. */
1072 kPXP_Histogram16levelMatch = 1 << 3U, /* Bitmap pixels are fully contained within the HIST16 histogram. */
1073 kPXP_Histogram32levelMatch = 1 << 4U, /* Bitmap pixels are fully contained within the HIST32 histogram. */
1074 };
1075
1076 /*! @brief PXP WFE-A engine configuration. */
1077 typedef struct _pxp_wfea_engine_config
1078 {
1079 uint32_t y4Addr; /*!< Address for Y4 buffer. */
1080 uint32_t y4cAddr; /*!< Address for Y4C buffer, {Y4[3:0],3'b000,collision}, 8bpp. */
1081 uint32_t wbAddr; /*!< Address for EPDC working buffer. */
1082 uint16_t updateWidth; /*!< Width of the update area. */
1083 uint16_t updateHeight; /*!< Height of the update area. */
1084 uint16_t updatePitch; /*!< Pitch of the update area. */
1085 uint16_t ulcX; /*!< X coordinate of upper left coordinate of the total input memory */
1086 uint16_t ulcY; /*!< Y coordinate of upper left coordinate of the total input memory */
1087 uint16_t resX; /*!< Horizontal resolution in pixels. */
1088 uint8_t lutNum; /*!< The EPDC LUT number for the update. */
1089 bool fullUpdateEnable; /*!< Enable full update. */
1090 bool alphaEnable; /*!< Enable alpha field, upd is {Y4[3:0],3'b000,alpha} format, otherwise its {Y4[3:0],4'b0000}. */
1091 bool detectionOnly; /*!< Detection only, do not write working buffer. */
1092 } pxp_wfea_engine_config_t;
1093
1094 #endif /* FSL_FEATURE_PXP_V3 */
1095
1096 /*******************************************************************************
1097 * API
1098 ******************************************************************************/
1099
1100 #if defined(__cplusplus)
1101 extern "C" {
1102 #endif
1103
1104 /*!
1105 * @name Initialization and deinitialization
1106 * @{
1107 */
1108
1109 /*!
1110 * @brief Initialize the PXP.
1111 *
1112 * This function enables the PXP peripheral clock, and resets the PXP registers
1113 * to default status.
1114 *
1115 * @param base PXP peripheral base address.
1116 */
1117 void PXP_Init(PXP_Type *base);
1118
1119 /*!
1120 * @brief De-initialize the PXP.
1121 *
1122 * This function disables the PXP peripheral clock.
1123 *
1124 * @param base PXP peripheral base address.
1125 */
1126 void PXP_Deinit(PXP_Type *base);
1127
1128 /*!
1129 * @brief Reset the PXP.
1130 *
1131 * This function resets the PXP peripheral registers to default status.
1132 *
1133 * @param base PXP peripheral base address.
1134 */
1135 void PXP_Reset(PXP_Type *base);
1136
1137 /*!
1138 * @brief Reset the PXP and the control register to initialized state.
1139 *
1140 * @param base PXP peripheral base address.
1141 */
1142 void PXP_ResetControl(PXP_Type *base);
1143 /*! @} */
1144
1145 /*!
1146 * @name Global operations
1147 * @{
1148 */
1149
1150 /*!
1151 * @brief Start process.
1152 *
1153 * Start PXP process using current configuration.
1154 *
1155 * @param base PXP peripheral base address.
1156 */
PXP_Start(PXP_Type * base)1157 static inline void PXP_Start(PXP_Type *base)
1158 {
1159 base->CTRL_SET = PXP_CTRL_ENABLE_MASK;
1160 }
1161
1162 /*!
1163 * @brief Enable or disable LCD hand shake.
1164 *
1165 * @param base PXP peripheral base address.
1166 * @param enable True to enable, false to disable.
1167 */
PXP_EnableLcdHandShake(PXP_Type * base,bool enable)1168 static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)
1169 {
1170 #if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
1171 if (enable)
1172 {
1173 base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
1174 }
1175 else
1176 {
1177 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
1178 }
1179 #else
1180 if (enable)
1181 {
1182 base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
1183 }
1184 else
1185 {
1186 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
1187 }
1188 #endif
1189 }
1190
1191 #if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT)
1192 /*!
1193 * @brief Enable or disable continous run.
1194 *
1195 * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed,
1196 * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts.
1197 *
1198 * If continous run enabled, the PXP will repeat based on the current configuration register
1199 * settings.
1200 *
1201 * @param base PXP peripheral base address.
1202 * @param enable True to enable, false to disable.
1203 */
PXP_EnableContinousRun(PXP_Type * base,bool enable)1204 static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)
1205 {
1206 if (enable)
1207 {
1208 base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK;
1209 }
1210 else
1211 {
1212 base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK;
1213 }
1214 }
1215 #endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */
1216
1217 /*!
1218 * @brief Set the PXP processing block size
1219 *
1220 * This function chooses the pixel block size that PXP using during process.
1221 * Larger block size means better performace, but be careful that when PXP is
1222 * rotating, the output must be divisible by the block size selected.
1223 *
1224 * @param base PXP peripheral base address.
1225 * @param size The pixel block size.
1226 */
PXP_SetProcessBlockSize(PXP_Type * base,pxp_block_size_t size)1227 static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)
1228 {
1229 base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size);
1230 }
1231
1232 #if PXP_USE_PATH
1233 /*!
1234 * @brief Sets the path for one of the MUX
1235 *
1236 * @param base PXP peripheral base address.
1237 * @param path the path configuration for one of the mux.
1238 */
1239 void PXP_SetPath(PXP_Type *base, pxp_path_t path);
1240 #endif /* PXP_USE_PATH */
1241
1242 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1243 /*!
1244 * @brief Enables or disables PXP engines in the process flow.
1245 *
1246 * @param base PXP peripheral base address.
1247 * @param mask The engines to enable. Logical OR of @ref pxp_process_engine_name_t.
1248 * @param enable true to enable, false to disable.
1249 */
PXP_EnableProcessEngine(PXP_Type * base,uint32_t mask,bool enable)1250 static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable)
1251 {
1252 mask &= 0xF3F0000UL;
1253
1254 if (enable)
1255 {
1256 base->CTRL_SET = mask;
1257 }
1258 else
1259 {
1260 base->CTRL_CLR = mask;
1261 }
1262 }
1263 #endif /* FSL_FEATURE_PXP_V3 */
1264
1265 /*! @} */
1266
1267 /*!
1268 * @name Status
1269 * @{
1270 */
1271
1272 /*!
1273 * @brief Gets PXP status flags.
1274 *
1275 * This function gets all PXP status flags. The flags are returned as the logical
1276 * OR value of the enumerators @ref _pxp_flags. To check a specific status,
1277 * compare the return value with enumerators in @ref _pxp_flags.
1278 * For example, to check whether the PXP has completed process, use like this:
1279 * @code
1280 if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP))
1281 {
1282 ...
1283 }
1284 @endcode
1285 *
1286 * @param base PXP peripheral base address.
1287 * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags.
1288 */
PXP_GetStatusFlags(PXP_Type * base)1289 static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)
1290 {
1291 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
1292 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
1293 PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK |
1294 PXP_STAT_AXI_WRITE_ERROR_1_MASK);
1295 #else
1296 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
1297 PXP_STAT_AXI_WRITE_ERROR_0_MASK);
1298 #endif
1299 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1300 status |= (base->IRQ >> 16U | base->IRQ << 16U);
1301 #endif /* FSL_FEATURE_PXP_V3 */
1302 return status;
1303 }
1304
1305 /*!
1306 * @brief Clears status flags with the provided mask.
1307 *
1308 * This function clears PXP status flags with a provided mask.
1309 *
1310 * @param base PXP peripheral base address.
1311 * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags.
1312 */
PXP_ClearStatusFlags(PXP_Type * base,uint32_t statusMask)1313 static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)
1314 {
1315 base->STAT_CLR = statusMask;
1316 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1317 statusMask &= 0xFFFF8000UL;
1318 base->IRQ_CLR = (statusMask >> 16U | statusMask << 16U);
1319 #endif /* FSL_FEATURE_PXP_V3 */
1320 }
1321
1322 /*!
1323 * @brief Gets the AXI ID of the failing bus operation.
1324 *
1325 * @param base PXP peripheral base address.
1326 * @param axiIndex Whitch AXI to get
1327 * - 0: AXI0
1328 * - 1: AXI1
1329 * @return The AXI ID of the failing bus operation.
1330 */
PXP_GetAxiErrorId(PXP_Type * base,uint8_t axiIndex)1331 static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
1332 {
1333 #if defined(PXP_STAT_AXI_ERROR_ID_1_MASK)
1334 if (0U == axiIndex)
1335 {
1336 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT);
1337 }
1338 else
1339 {
1340 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
1341 }
1342 #else
1343 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
1344 #endif
1345 }
1346
1347 /*! @} */
1348
1349 /*!
1350 * @name Interrupts
1351 * @{
1352 */
1353
1354 /*!
1355 * @brief Enables PXP interrupts according to the provided mask.
1356 *
1357 * This function enables the PXP interrupts according to the provided mask. The mask
1358 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
1359 * For example, to enable PXP process complete interrupt and command loaded
1360 * interrupt, do the following.
1361 * @code
1362 PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable);
1363 @endcode
1364 *
1365 * @param base PXP peripheral base address.
1366 * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable.
1367 */
PXP_EnableInterrupts(PXP_Type * base,uint32_t mask)1368 static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)
1369 {
1370 base->CTRL_SET = (mask & 0xEUL);
1371 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1372 mask &= 0xFFFF8000UL;
1373 base->IRQ_MASK_SET = (mask >> 16U | mask << 16U);
1374 #endif /* FSL_FEATURE_PXP_V3 */
1375 }
1376
1377 /*!
1378 * @brief Disables PXP interrupts according to the provided mask.
1379 *
1380 * This function disables the PXP interrupts according to the provided mask. The mask
1381 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
1382 *
1383 * @param base PXP peripheral base address.
1384 * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable.
1385 */
PXP_DisableInterrupts(PXP_Type * base,uint32_t mask)1386 static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)
1387 {
1388 base->CTRL_CLR = (mask & 0xEUL);
1389 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1390 mask &= 0xFFFF8000UL;
1391 base->IRQ_MASK_CLR = (mask >> 16U | mask << 16U);
1392 #endif /* FSL_FEATURE_PXP_V3 */
1393 }
1394
1395 /*! @} */
1396
1397 /*!
1398 * @name Alpha surface
1399 * @{
1400 */
1401
1402 /*!
1403 * @brief Set the alpha surface input buffer configuration.
1404 *
1405 * @param base PXP peripheral base address.
1406 * @param config Pointer to the configuration.
1407 */
1408 void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config);
1409
1410 /*!
1411 * @brief Set the alpha surface blending configuration.
1412 *
1413 * @param base PXP peripheral base address.
1414 * @param config Pointer to the configuration structure.
1415 */
1416 void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config);
1417
1418 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1419 /*!
1420 * @brief Set the alpha surface blending configuration for the secondary engine.
1421 *
1422 * @param base PXP peripheral base address.
1423 * @param config Pointer to the configuration structure.
1424 */
1425 void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config);
1426
1427 /*!
1428 * @brief Set the alpha surface overlay color key.
1429 *
1430 * If a pixel in the current overlay image with a color that falls in the range
1431 * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
1432 * pixel value for that location. If no PS image is present or if the PS image also
1433 * matches its colorkey range, the PS background color is used.
1434 *
1435 * @param base PXP peripheral base address.
1436 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B.
1437 * @param colorKeyLow Color key low range.
1438 * @param colorKeyHigh Color key high range.
1439 *
1440 * @note Colorkey operations are higher priority than alpha or ROP operations
1441 */
1442 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1443
1444 /*!
1445 * @brief Enable or disable the alpha surface color key.
1446 *
1447 * @param base PXP peripheral base address.
1448 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B.
1449 * @param enable True to enable, false to disable.
1450 */
PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type * base,uint32_t num,bool enable)1451 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable)
1452 {
1453 switch (num)
1454 {
1455 case 0:
1456 base->AS_CTRL =
1457 (base->AS_CTRL & ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK) | PXP_AS_CTRL_ENABLE_COLORKEY((uint32_t)enable);
1458 break;
1459
1460 case 1:
1461 base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) |
1462 PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable);
1463 break;
1464
1465 default:
1466 /* Only 2 alpha process engine instances are supported. */
1467 assert(false);
1468 break;
1469 }
1470 }
1471 #else
1472 /*!
1473 * @brief Set the alpha surface overlay color key.
1474 *
1475 * If a pixel in the current overlay image with a color that falls in the range
1476 * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface
1477 * pixel value for that location. If no PS image is present or if the PS image also
1478 * matches its colorkey range, the PS background color is used.
1479 *
1480 * @param base PXP peripheral base address.
1481 * @param colorKeyLow Color key low range.
1482 * @param colorKeyHigh Color key high range.
1483 *
1484 * @note Colorkey operations are higher priority than alpha or ROP operations
1485 */
1486 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1487
1488 /*!
1489 * @brief Enable or disable the alpha surface color key.
1490 *
1491 * @param base PXP peripheral base address.
1492 * @param enable True to enable, false to disable.
1493 */
PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type * base,bool enable)1494 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable)
1495 {
1496 if (enable)
1497 {
1498 base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
1499 }
1500 else
1501 {
1502 base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
1503 }
1504 }
1505 #endif /* FSL_FEATURE_PXP_V3 */
1506
1507 /*!
1508 * @brief Set the alpha surface position in output buffer.
1509 *
1510 * @param base PXP peripheral base address.
1511 * @param upperLeftX X of the upper left corner.
1512 * @param upperLeftY Y of the upper left corner.
1513 * @param lowerRightX X of the lower right corner.
1514 * @param lowerRightY Y of the lower right corner.
1515 */
1516 void PXP_SetAlphaSurfacePosition(
1517 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
1518 /*! @} */
1519
1520 /*!
1521 * @name Process surface
1522 * @{
1523 */
1524 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1525 /*!
1526 * @brief Set the back ground color of PS.
1527 *
1528 * @param base PXP peripheral base address.
1529 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B.
1530 * @param backGroundColor Pixel value of the background color.
1531 */
PXP_SetProcessSurfaceBackGroundColor(PXP_Type * base,uint8_t num,uint32_t backGroundColor)1532 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor)
1533 {
1534 switch (num)
1535 {
1536 case 0:
1537 base->PS_BACKGROUND_0 = backGroundColor;
1538 break;
1539
1540 case 1:
1541 base->PS_BACKGROUND_1 = backGroundColor;
1542 break;
1543
1544 default:
1545 /* Only 2 alpha process engine instances are supported. */
1546 assert(false);
1547 break;
1548 }
1549 }
1550 #else
1551 /*!
1552 * @brief Set the back ground color of PS.
1553 *
1554 * @param base PXP peripheral base address.
1555 * @param backGroundColor Pixel value of the background color.
1556 */
PXP_SetProcessSurfaceBackGroundColor(PXP_Type * base,uint32_t backGroundColor)1557 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor)
1558 {
1559 #if defined(PXP_PS_BACKGROUND_0_COLOR_MASK)
1560 base->PS_BACKGROUND_0 = backGroundColor;
1561 #else
1562 base->PS_BACKGROUND = backGroundColor;
1563 #endif
1564 }
1565 #endif /* FSL_FEATURE_PXP_V3 */
1566
1567 /*!
1568 * @brief Set the process surface input buffer configuration.
1569 *
1570 * @param base PXP peripheral base address.
1571 * @param config Pointer to the configuration.
1572 */
1573 void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config);
1574
1575 /*!
1576 * @brief Set the process surface scaler configuration.
1577 *
1578 * The valid down scale fact is 1/(2^12) ~ 16.
1579 *
1580 * @param base PXP peripheral base address.
1581 * @param inputWidth Input image width.
1582 * @param inputHeight Input image height.
1583 * @param outputWidth Output image width.
1584 * @param outputHeight Output image height.
1585 */
1586 void PXP_SetProcessSurfaceScaler(
1587 PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight);
1588
1589 /*!
1590 * @brief Set the process surface position in output buffer.
1591 *
1592 * @param base PXP peripheral base address.
1593 * @param upperLeftX X of the upper left corner.
1594 * @param upperLeftY Y of the upper left corner.
1595 * @param lowerRightX X of the lower right corner.
1596 * @param lowerRightY Y of the lower right corner.
1597 */
1598 void PXP_SetProcessSurfacePosition(
1599 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
1600
1601 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
1602 /*!
1603 * @brief Set the process surface color key.
1604 *
1605 * If the PS image matches colorkey range, the PS background color is output. Set
1606 * @p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying.
1607 *
1608 * @param base PXP peripheral base address.
1609 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B.
1610 * @param colorKeyLow Color key low range.
1611 * @param colorKeyHigh Color key high range.
1612 */
1613 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1614 #else
1615 /*!
1616 * @brief Set the process surface color key.
1617 *
1618 * If the PS image matches colorkey range, the PS background color is output. Set
1619 * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying.
1620 *
1621 * @param base PXP peripheral base address.
1622 * @param colorKeyLow Color key low range.
1623 * @param colorKeyHigh Color key high range.
1624 */
1625 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
1626 #endif /* FSL_FEATURE_PXP_V3 */
1627
1628 /*!
1629 * @brief Set the process surface input pixel format YUV or YCbCr.
1630 *
1631 * If process surface input pixel format is YUV and CSC1 is not enabled,
1632 * in other words, the process surface output pixel format is also YUV,
1633 * then this function should be called to set whether input pixel format
1634 * is YUV or YCbCr.
1635 *
1636 * @param base PXP peripheral base address.
1637 * @param format The YUV format.
1638 */
PXP_SetProcessSurfaceYUVFormat(PXP_Type * base,pxp_ps_yuv_format_t format)1639 static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)
1640 {
1641 if (kPXP_PsYUVFormatYUV == format)
1642 {
1643 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_YCBCR_MODE_MASK;
1644 }
1645 else
1646 {
1647 base->CSC1_COEF0 |= PXP_CSC1_COEF0_YCBCR_MODE_MASK;
1648 }
1649 }
1650 /*! @} */
1651
1652 /*!
1653 * @name Output buffer
1654 * @{
1655 */
1656
1657 /*!
1658 * @brief Set the PXP outpt buffer configuration.
1659 *
1660 * @param base PXP peripheral base address.
1661 * @param config Pointer to the configuration.
1662 */
1663 void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config);
1664
1665 /*!
1666 * @brief Set the global overwritten alpha value.
1667 *
1668 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
1669 * will be overwritten, otherwise the computed alpha value is used.
1670 *
1671 * @param base PXP peripheral base address.
1672 * @param alpha The alpha value.
1673 */
PXP_SetOverwrittenAlphaValue(PXP_Type * base,uint8_t alpha)1674 static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)
1675 {
1676 base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha);
1677 }
1678
1679 /*!
1680 * @brief Enable or disable the global overwritten alpha value.
1681 *
1682 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
1683 * will be overwritten, otherwise the computed alpha value is used.
1684 *
1685 * @param base PXP peripheral base address.
1686 * @param enable True to enable, false to disable.
1687 */
PXP_EnableOverWrittenAlpha(PXP_Type * base,bool enable)1688 static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)
1689 {
1690 if (enable)
1691 {
1692 base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
1693 }
1694 else
1695 {
1696 base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
1697 }
1698 }
1699
1700 /*!
1701 * @brief Set the rotation configuration.
1702 *
1703 * The PXP could rotate the process surface or the output buffer. There are
1704 * two PXP versions:
1705 * - Version 1: Only has one rotate sub module, the output buffer and process
1706 * surface share the same rotate sub module, which means the process surface
1707 * and output buffer could not be rotate at the same time. When pass in
1708 * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate,
1709 * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not
1710 * use the rotate.
1711 * - Version 2: Has two seperate rotate sub modules, the output buffer and
1712 * process surface could configure the rotation independently.
1713 *
1714 * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is.
1715 * PXP_SHARE_ROTATE=1 means version 1.
1716 *
1717 * @param base PXP peripheral base address.
1718 * @param position Rotate process surface or output buffer.
1719 * @param degree Rotate degree.
1720 * @param flipMode Flip mode.
1721 *
1722 * @note This function is different depends on the macro PXP_SHARE_ROTATE.
1723 */
PXP_SetRotateConfig(PXP_Type * base,pxp_rotate_position_t position,pxp_rotate_degree_t degree,pxp_flip_mode_t flipMode)1724 static inline void PXP_SetRotateConfig(PXP_Type *base,
1725 pxp_rotate_position_t position,
1726 pxp_rotate_degree_t degree,
1727 pxp_flip_mode_t flipMode)
1728 {
1729 #if PXP_SHARE_ROTATE
1730 base->CTRL =
1731 (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
1732 PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
1733 #else
1734 uint32_t ctrl = base->CTRL;
1735
1736 if (kPXP_RotateOutputBuffer == position)
1737 {
1738 ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
1739 ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
1740 }
1741 else
1742 {
1743 ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
1744 ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
1745 }
1746
1747 base->CTRL = ctrl;
1748 #endif
1749 }
1750
1751 /*!
1752 * @brief Build a solid rectangle of given pixel value.
1753 *
1754 * @param base PXP peripheral base address.
1755 * @param outFormat output pixel format.
1756 * @param value The value of the pixel to be filled in the rectangle in ARGB8888 format.
1757 * @param width width of the rectangle.
1758 * @param height height of the rectangle.
1759 * @param pitch output pitch in byte.
1760 * @param outAddr address of the memory to store the rectangle.
1761 */
1762 void PXP_BuildRect(PXP_Type *base,
1763 pxp_output_pixel_format_t outFormat,
1764 uint32_t value,
1765 uint16_t width,
1766 uint16_t height,
1767 uint16_t pitch,
1768 uint32_t outAddr);
1769 /*! @} */
1770
1771 /*!
1772 * @name Command queue
1773 * @{
1774 */
1775
1776 /*!
1777 * @brief Set the next command.
1778 *
1779 * The PXP supports a primitive ability to queue up one operation while the current
1780 * operation is running. Workflow:
1781 *
1782 * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory
1783 * in the order they appear in the register map.
1784 * 2. Call this function sets the new operation to PXP.
1785 * 3. There are two methods to check whether the PXP has loaded the new operation.
1786 * The first method is using @ref PXP_IsNextCommandPending. If there is new operation
1787 * not loaded by the PXP, this function returns true. The second method is checking
1788 * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User
1789 * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded
1790 * signal in interrupt way.
1791 * 4. When command loaded by PXP, a new command could be set using this function.
1792 *
1793 * @code
1794 uint32_t pxp_command1[48];
1795 uint32_t pxp_command2[48];
1796
1797 pxp_command1[0] = ...;
1798 pxp_command1[1] = ...;
1799 ...
1800 pxp_command2[0] = ...;
1801 pxp_command2[1] = ...;
1802 ...
1803
1804 while (PXP_IsNextCommandPending(PXP))
1805 {
1806 }
1807
1808 PXP_SetNextCommand(PXP, pxp_command1);
1809
1810 while (PXP_IsNextCommandPending(PXP))
1811 {
1812 }
1813
1814 PXP_SetNextCommand(PXP, pxp_command2);
1815 @endcode
1816 *
1817 * @param base PXP peripheral base address.
1818 * @param commandAddr Address of the new command.
1819 */
1820 void PXP_SetNextCommand(PXP_Type *base, void *commandAddr);
1821
1822 /*!
1823 * @brief Check whether the next command is pending.
1824 *
1825 * @param base UART peripheral base address.
1826 * @return True is pending, false is not.
1827 */
PXP_IsNextCommandPending(PXP_Type * base)1828 static inline bool PXP_IsNextCommandPending(PXP_Type *base)
1829 {
1830 return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK);
1831 }
1832
1833 /*!
1834 * @brief Cancel command set by @ref PXP_SetNextCommand
1835 *
1836 * @param base UART peripheral base address.
1837 */
PXP_CancelNextCommand(PXP_Type * base)1838 static inline void PXP_CancelNextCommand(PXP_Type *base)
1839 {
1840 /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */
1841 uint32_t regAddr = (uint32_t) & (base->NEXT);
1842 regAddr += 8U;
1843 *(uint32_t *)regAddr = PXP_NEXT_ENABLED_MASK;
1844 }
1845
1846 /*! @} */
1847
1848 /*!
1849 * @name Color space conversion
1850 * @{
1851 */
1852
1853 #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
1854 /*!
1855 * @brief Set the CSC2 configuration.
1856 *
1857 * The CSC2 module receives pixels in any color space and can convert the pixels
1858 * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed
1859 * onto the LUT and rotation engine for further processing
1860 *
1861 * @param base PXP peripheral base address.
1862 * @param config Pointer to the configuration.
1863 */
1864 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config);
1865
1866 /*!
1867 * @brief Enable or disable the CSC2.
1868 *
1869 * @param base PXP peripheral base address.
1870 * @param enable True to enable, false to disable.
1871 */
PXP_EnableCsc2(PXP_Type * base,bool enable)1872 static inline void PXP_EnableCsc2(PXP_Type *base, bool enable)
1873 {
1874 if (enable)
1875 {
1876 base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK;
1877 }
1878 else
1879 {
1880 base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK;
1881 }
1882 }
1883 #endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */
1884
1885 /*!
1886 * @brief Set the CSC1 mode.
1887 *
1888 * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and
1889 * converts the pixels to the RGB888 color space. It could only be used by process
1890 * surface.
1891 *
1892 * @param base PXP peripheral base address.
1893 * @param mode The conversion mode.
1894 */
1895 void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode);
1896
1897 /*!
1898 * @brief Enable or disable the CSC1.
1899 *
1900 * @param base PXP peripheral base address.
1901 * @param enable True to enable, false to disable.
1902 */
PXP_EnableCsc1(PXP_Type * base,bool enable)1903 static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)
1904 {
1905 if (enable)
1906 {
1907 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK;
1908 }
1909 else
1910 {
1911 base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK;
1912 }
1913 }
1914 /*! @} */
1915
1916 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
1917 /*!
1918 * @name LUT operations
1919 * @{
1920 */
1921
1922 /*!
1923 * @brief Set the LUT configuration.
1924 *
1925 * The lookup table (LUT) is used to modify pixels in a manner that is not linear
1926 * and that cannot be achieved by the color space conversion modules. To setup
1927 * the LUT, the complete workflow is:
1928 * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode.
1929 * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP.
1930 * 3. Use @ref PXP_EnableLut to enable the function.
1931 *
1932 * @param base PXP peripheral base address.
1933 * @param config Pointer to the configuration.
1934 */
1935 void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config);
1936
1937 /*!
1938 * @brief Set the look up table to PXP.
1939 *
1940 * If lookup mode is DIRECT mode, this function loads @p bytesNum of values
1941 * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this
1942 * function allows only update part of the PXP LUT.
1943 *
1944 * If lookup mode is CACHE mode, this function sets the new address to @p memAddr
1945 * and invalid the PXP LUT cache.
1946 *
1947 * @param base PXP peripheral base address.
1948 * @param lookupMode Which lookup mode is used. Note that this parameter is only
1949 * used to distinguish DIRECT mode and CACHE mode, it does not change the register
1950 * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig.
1951 * @param bytesNum How many bytes to set. This value must be divisable by 8.
1952 * @param memAddr Address of look up table to set.
1953 * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should
1954 * be 8 bytes aligned.
1955 *
1956 * @retval kStatus_Success Load successfully.
1957 * @retval kStatus_InvalidArgument Failed because of invalid argument.
1958 */
1959 status_t PXP_LoadLutTable(
1960 PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr);
1961
1962 /*!
1963 * @brief Enable or disable the LUT.
1964 *
1965 * @param base PXP peripheral base address.
1966 * @param enable True to enable, false to disable.
1967 */
PXP_EnableLut(PXP_Type * base,bool enable)1968 static inline void PXP_EnableLut(PXP_Type *base, bool enable)
1969 {
1970 if (enable)
1971 {
1972 base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK;
1973 }
1974 else
1975 {
1976 base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK;
1977 }
1978 }
1979
1980 /*!
1981 * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode.
1982 *
1983 * @param base PXP peripheral base address.
1984 * @param bank The bank to select.
1985 */
PXP_Select8kLutBank(PXP_Type * base,pxp_lut_8k_bank_t bank)1986 static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank)
1987 {
1988 base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank);
1989 }
1990 /*! @} */
1991 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
1992
1993 #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
1994 /*!
1995 * @name Dither
1996 * @{
1997 */
1998
1999 /*!
2000 * @brief Write data to the PXP internal memory.
2001 *
2002 * @param base PXP peripheral base address.
2003 * @param ram Which internal memory to write.
2004 * @param bytesNum How many bytes to write.
2005 * @param data Pointer to the data to write.
2006 * @param memStartAddr The start address in the internal memory to write the data.
2007 */
2008 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr);
2009
2010 /*!
2011 * @brief Set the dither final LUT data.
2012 *
2013 * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4]
2014 * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate
2015 * the final output pixel to the next process module.
2016 *
2017 * @param base PXP peripheral base address.
2018 * @param data Pointer to the LUT data to set.
2019 */
2020 void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data);
2021
2022 /*!
2023 * @brief Set the configuration for the dither block.
2024 *
2025 * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call
2026 * @ref PXP_SetInternalRamData to set the LUT data to internal memory.
2027 *
2028 * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set
2029 * the LUT data.
2030 *
2031 * @param base PXP peripheral base address.
2032 * @param config Pointer to the configuration.
2033 *
2034 * @note When using ordered dithering, please set the PXP process block size same
2035 * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize.
2036 */
PXP_SetDitherConfig(PXP_Type * base,const pxp_dither_config_t * config)2037 static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)
2038 {
2039 typedef union
2040 {
2041 pxp_dither_config_t _dither_config;
2042 uint32_t _u32;
2043 } pxp_reg_convert_t;
2044
2045 pxp_reg_convert_t pid;
2046
2047 pid._dither_config = *config;
2048 base->DITHER_CTRL = pid._u32 & 0x00FFFFFFU;
2049 }
2050
2051 /*!
2052 * @brief Enable or disable dither engine in the PXP process path.
2053 *
2054 * After the initialize function @ref PXP_Init, the dither engine is disabled and not
2055 * use in the PXP processing path. This function enables the dither engine and
2056 * routes the dither engine output to the output buffer. When the dither engine
2057 * is enabled using this function, @ref PXP_SetDitherConfig must be called to
2058 * configure dither engine correctly, otherwise there is not output to the output
2059 * buffer.
2060 *
2061 * @param base PXP peripheral base address.
2062 * @param enable Pass in true to enable, false to disable.
2063 */
2064 void PXP_EnableDither(PXP_Type *base, bool enable);
2065
2066 /*! @} */
2067
2068 #endif /* FSL_FEATURE_PXP_HAS_DITHER */
2069
2070 /*!
2071 * @name Porter Duff
2072 * @{
2073 */
2074 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
2075 /*!
2076 * @brief Set the Porter Duff configuration for one of the alpha process engine.
2077 *
2078 * @param base PXP peripheral base address.
2079 * @param num instance number.
2080 * @param config Pointer to the configuration.
2081 */
2082 void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config);
2083 #endif /* FSL_FEATURE_PXP_V3 */
2084
2085 #if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)
2086 /*!
2087 * @brief Set the Porter Duff configuration.
2088 *
2089 * @param base PXP peripheral base address.
2090 * @param config Pointer to the configuration.
2091 */
2092 void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config);
2093 #endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
2094
2095 #if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \
2096 (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
2097
2098 /*!
2099 * @brief Get the Porter Duff configuration.
2100 *
2101 * The FactorMode are selected based on blend mode, the other values are set
2102 * based on input parameters. These values could be modified after calling
2103 * this function. This function is extened @ref PXP_GetPorterDuffConfig.
2104 *
2105 * @param mode The blend mode.
2106 * @param config Pointer to the configuration.
2107 * @param dstGlobalAlphaMode Destination layer (or PS, s0) global alpha mode, see @ref pxp_porter_duff_global_alpha_mode
2108 * @param dstAlphaMode Destination layer (or PS, s0) alpha mode, see @ref pxp_porter_duff_alpha_mode.
2109 * @param dstColorMode Destination layer (or PS, s0) color mode, see @ref pxp_porter_duff_color_mode.
2110 * @param srcGlobalAlphaMode Source layer (or AS, s1) global alpha mode, see @ref pxp_porter_duff_global_alpha_mode
2111 * @param srcAlphaMode Source layer (or AS, s1) alpha mode, see @ref pxp_porter_duff_alpha_mode.
2112 * @param srcColorMode Source layer (or AS, s1) color mode, see @ref pxp_porter_duff_color_mode.
2113 * @param dstGlobalAlpha Destination layer (or PS, s0) global alpha value, 0~255
2114 * @param srcGlobalAlpha Source layer (or AS, s1) global alpha value, 0~255
2115 * @retval kStatus_Success Successfully get the configuratoin.
2116 * @retval kStatus_InvalidArgument The blend mode not supported.
2117 */
2118 status_t PXP_GetPorterDuffConfigExt(pxp_porter_duff_blend_mode_t mode,
2119 pxp_porter_duff_config_t *config,
2120 uint8_t dstGlobalAlphaMode,
2121 uint8_t dstAlphaMode,
2122 uint8_t dstColorMode,
2123 uint8_t srcGlobalAlphaMode,
2124 uint8_t srcAlphaMode,
2125 uint8_t srcColorMode,
2126 uint8_t dstGlobalAlpha,
2127 uint8_t srcGlobalAlpha);
2128
2129 /*!
2130 * @brief Get the Porter Duff configuration by blend mode.
2131 *
2132 * The FactorMode are selected based on blend mode, the AlphaMode are set to
2133 * @ref kPXP_PorterDuffAlphaStraight, the ColorMode are set to
2134 * @ref kPXP_PorterDuffColorWithAlpha, the GlobalAlphaMode are set to
2135 * @ref kPXP_PorterDuffLocalAlpha. These values could be modified after calling
2136 * this function.
2137 *
2138 * @param mode The blend mode.
2139 * @param config Pointer to the configuration.
2140 * @retval kStatus_Success Successfully get the configuratoin.
2141 * @retval kStatus_InvalidArgument The blend mode not supported.
2142 */
PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode,pxp_porter_duff_config_t * config)2143 static inline status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config)
2144 {
2145 return PXP_GetPorterDuffConfigExt(mode, /* Blend mode. */
2146 config, /* Output configuration. */
2147 kPXP_PorterDuffLocalAlpha, /* dstGlobalAlphaMode */
2148 kPXP_PorterDuffAlphaStraight, /* dstAlphaMode */
2149 kPXP_PorterDuffColorWithAlpha, /* dstColorMode */
2150 kPXP_PorterDuffLocalAlpha, /* srcGlobalAlphaMode */
2151 kPXP_PorterDuffAlphaStraight, /* srcAlphaMode */
2152 kPXP_PorterDuffColorWithAlpha, /* srcColorMode */
2153 0U, /* dstGlobalAlpha */
2154 0U /* srcGlobalAlpha */
2155 );
2156 }
2157
2158 /*! @} */
2159 #endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
2160
2161 /*! @} */
2162
2163 /*!
2164 * @name Buffer copy
2165 * @{
2166 */
2167
2168 /*!
2169 * @brief Copy picture from one buffer to another buffer.
2170 *
2171 * This function copies a rectangle from one buffer to another buffer.
2172 *
2173 * @verbatim
2174 Source buffer:
2175 srcPicBaseAddr
2176 +-----------------------------------------------------------+
2177 | |
2178 | (srcOffsetX, srcOffsetY) |
2179 | +-------------------+ |
2180 | | | |
2181 | | | |
2182 | | | height |
2183 | | | |
2184 | | | |
2185 | +-------------------+ |
2186 | width |
2187 | |
2188 | srcPicthBytes |
2189 +-----------------------------------------------------------+
2190
2191 Destination buffer:
2192 destPicBaseAddr
2193 +-------------------------------------------+
2194 | |
2195 | |
2196 | |
2197 | (destOffsetX, destOffsetY) |
2198 | +-------------------+ |
2199 | | | |
2200 | | | |
2201 | | | height |
2202 | | | |
2203 | | | |
2204 | +-------------------+ |
2205 | width |
2206 | |
2207 | |
2208 | |
2209 | destPicthBytes |
2210 +-------------------------------------------+
2211 @endverbatim
2212 *
2213 * @note This function resets the old PXP settings, which means the settings
2214 * like rotate, flip, will be reseted to disabled status.
2215 *
2216 * @param base PXP peripheral base address.
2217 * @param config Pointer to the picture copy configuration structure.
2218 * @retval kStatus_Success Successfully started the copy process.
2219 * @retval kStatus_InvalidArgument Invalid argument.
2220 */
2221 status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *config);
2222
2223 /*!
2224 * @brief Copy continous memory.
2225 *
2226 * @note The copy size should be 512 byte aligned.
2227 * @note This function resets the old PXP settings, which means the settings
2228 * like rotate, flip, will be reseted to disabled status.
2229 *
2230 * @param base PXP peripheral base address.
2231 * @param srcAddr Source memory address.
2232 * @param destAddr Destination memory address.
2233 * @param size How many bytes to copy, should be 512 byte aligned.
2234 * @retval kStatus_Success Successfully started the copy process.
2235 * @retval kStatus_InvalidArgument Invalid argument.
2236 */
2237 status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
2238
2239 /*!
2240 * @brief Copy continous memory.
2241 *
2242 * @note This function resets the old PXP settings, which means the settings
2243 * like rotate, flip, will be reseted to disabled status.
2244 *
2245 * @note Compare with @PXP_StartMemCopy, this function supports size not aligned to
2246 * 512 bytes. This function returns when copy finished, upper layer doesn't need to
2247 * wait @ref kPXP_CompleteFlag.
2248 *
2249 * @param base PXP peripheral base address.
2250 * @param srcAddr Source memory address.
2251 * @param destAddr Destination memory address.
2252 * @param size How many bytes to copy, should be 512 byte aligned.
2253 * @retval kStatus_Success Successfully started the copy process.
2254 * @retval kStatus_InvalidArgument Invalid argument.
2255 */
2256 status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
2257
2258 /*! @} */
2259
2260 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
2261
2262 /*!
2263 * @name Fetch engine
2264 * @{
2265 */
2266 /*!
2267 * @brief Configures one channel of some block's fetch engine.
2268 *
2269 * Fetch engine is 64-bit input and 32-bit output per channel
2270 *
2271 * @param base PXP peripheral base address.
2272 * @param name which block the fetch engine belongs to.
2273 * @param channel channel number.
2274 * @param config pointer to the configuration structure.
2275 * @retval kStatus_Success Successfully configured the engine.
2276 * @retval kStatus_InvalidArgument Invalid argument.
2277 */
2278 status_t PXP_SetFetchEngineConfig(PXP_Type *base,
2279 pxp_fetch_engine_name_t name,
2280 uint8_t channel,
2281 const pxp_fetch_engine_config_t *config);
2282
2283 /*!
2284 * @brief Enables/disables the fetch engine.
2285 *
2286 * @param base PXP peripheral base address.
2287 * @param name which block the fetch engine belongs to.
2288 * @param channel channel number.
2289 * @param enable true to enable, false to disable.
2290 */
PXP_EnableFetchEngine(PXP_Type * base,pxp_fetch_engine_name_t name,uint8_t channel,bool enable)2291 static inline void PXP_EnableFetchEngine(PXP_Type *base, pxp_fetch_engine_name_t name, uint8_t channel, bool enable)
2292 {
2293 if (enable)
2294 {
2295 if (name == kPXP_FetchInput)
2296 {
2297 switch (channel)
2298 {
2299 case 0:
2300 base->INPUT_FETCH_CTRL_CH0_SET = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
2301 break;
2302
2303 case 1:
2304 base->INPUT_FETCH_CTRL_CH1_SET = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
2305 break;
2306
2307 default:
2308 /* Only 2 channels are supported per fetch engine. */
2309 assert(false);
2310 break;
2311 }
2312 }
2313 else
2314 {
2315 switch (channel)
2316 {
2317 case 0:
2318 base->DITHER_FETCH_CTRL_CH0_SET = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
2319 break;
2320
2321 case 1:
2322 base->DITHER_FETCH_CTRL_CH1_SET = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
2323 break;
2324
2325 default:
2326 /* Only 2 channels are supported per fetch engine. */
2327 assert(false);
2328 break;
2329 }
2330 }
2331 }
2332 else
2333 {
2334 if (name == kPXP_FetchInput)
2335 {
2336 switch (channel)
2337 {
2338 case 0:
2339 base->INPUT_FETCH_CTRL_CH0_CLR = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
2340 break;
2341
2342 case 1:
2343 base->INPUT_FETCH_CTRL_CH1_CLR = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
2344 break;
2345
2346 default:
2347 /* Only 2 channels are supported per fetch engine. */
2348 assert(false);
2349 break;
2350 }
2351 }
2352 else
2353 {
2354 switch (channel)
2355 {
2356 case 0:
2357 base->DITHER_FETCH_CTRL_CH0_CLR = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
2358 break;
2359
2360 case 1:
2361 base->DITHER_FETCH_CTRL_CH1_CLR = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
2362 break;
2363
2364 default:
2365 /* Only 2 channels are supported per fetch engine. */
2366 assert(false);
2367 break;
2368 }
2369 }
2370 }
2371 }
2372 /*! @} */
2373
2374 /*!
2375 * @name Store engine
2376 * @{
2377 */
2378
2379 /*!
2380 * @brief Configures one channel of some block's store engine.
2381 *
2382 * Store engine is 32-bit input and 64-bit output per channel.
2383 * @note: If there is only one channel used for data input, channel 0 must be used rather than channel 1.
2384 *
2385 * @param base PXP peripheral base address.
2386 * @param name the store engine belongs to which block.
2387 * @param channel channel number.
2388 * @param config pointer to the configuration structure.
2389 * @retval kStatus_Success Successfully configured the engine.
2390 * @retval kStatus_InvalidArgument Invalid argument.
2391 */
2392 status_t PXP_SetStoreEngineConfig(PXP_Type *base,
2393 pxp_store_engine_name_t name,
2394 uint8_t channel,
2395 const pxp_store_engine_config_t *config);
2396
2397 /*!
2398 * @brief Enables/disables the store engine.
2399 *
2400 * @param base PXP peripheral base address.
2401 * @param name which block the store engine belongs to.
2402 * @param channel channel number.
2403 * @param enable true to enable, false to disable.
2404 */
PXP_EnableStoreEngine(PXP_Type * base,pxp_store_engine_name_t name,uint8_t channel,bool enable)2405 static inline void PXP_EnableStoreEngine(PXP_Type *base, pxp_store_engine_name_t name, uint8_t channel, bool enable)
2406 {
2407 if (enable)
2408 {
2409 if (name == kPXP_StoreInput)
2410 {
2411 switch (channel)
2412 {
2413 case 0:
2414 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
2415 break;
2416
2417 case 1:
2418 base->INPUT_STORE_CTRL_CH1_SET = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
2419 break;
2420
2421 default:
2422 /* Only 2 channels are supported per fetch engine. */
2423 assert(false);
2424 break;
2425 }
2426 }
2427 else
2428 {
2429 switch (channel)
2430 {
2431 case 0:
2432 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
2433 break;
2434
2435 case 1:
2436 base->DITHER_STORE_CTRL_CH1_SET = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
2437 break;
2438
2439 default:
2440 /* Only 2 channels are supported per fetch engine. */
2441 assert(false);
2442 break;
2443 }
2444 }
2445 }
2446 else
2447 {
2448 if (name == kPXP_StoreInput)
2449 {
2450 switch (channel)
2451 {
2452 case 0:
2453 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
2454 break;
2455
2456 case 1:
2457 base->INPUT_STORE_CTRL_CH1_CLR = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
2458 break;
2459
2460 default:
2461 /* Only 2 channels are supported per fetch engine. */
2462 assert(false);
2463 break;
2464 }
2465 }
2466 else
2467 {
2468 switch (channel)
2469 {
2470 case 0:
2471 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
2472 break;
2473
2474 case 1:
2475 base->DITHER_STORE_CTRL_CH1_CLR = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
2476 break;
2477
2478 default:
2479 /* Only 2 channels are supported per fetch engine. */
2480 assert(false);
2481 break;
2482 }
2483 }
2484 }
2485 }
2486
2487 /*!
2488 * @brief Combines the 2 channels of some store engine.
2489 *
2490 * Store engine is 32-bit input and 64-bit output per channel. If both channels of store engine's
2491 * input and 8 bits flag contain valid data, then need set combine to true to support total 64-bit input.
2492 *
2493 * @param base PXP peripheral base address.
2494 * @param name the store engine belongs to which block.
2495 * @param combine true to combine the 2 channels.
2496 */
PXP_CombineStoreEngineChannel(PXP_Type * base,pxp_store_engine_name_t name,bool combine)2497 static inline void PXP_CombineStoreEngineChannel(PXP_Type *base, pxp_store_engine_name_t name, bool combine)
2498 {
2499 if (name == kPXP_StoreInput)
2500 {
2501 if (combine)
2502 {
2503 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2504 }
2505 else
2506 {
2507 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2508 }
2509 }
2510 else
2511 {
2512 if (combine)
2513 {
2514 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2515 }
2516 else
2517 {
2518 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
2519 }
2520 }
2521 }
2522 /*! @} */
2523
2524 /*!
2525 * @name Pre-dither CFA engine
2526 * @{
2527 */
2528 /*!
2529 * @brief Configures the pre-dither CFA engine.
2530 *
2531 * @param base PXP peripheral base address.
2532 * @param config pointer to the configuration structure.
2533 * @retval kStatus_Success Successfully configured the engine.
2534 * @retval kStatus_InvalidArgument Invalid argument.
2535 */
2536 status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config);
2537
2538 /*!
2539 * @brief Enables/disables the CFA block.
2540 *
2541 * @param base PXP peripheral base address.
2542 * @param enable true to enable, false to disable.
2543 */
PXP_EnableCfa(PXP_Type * base,bool enable)2544 static inline void PXP_EnableCfa(PXP_Type *base, bool enable)
2545 {
2546 if (enable)
2547 {
2548 base->CFA_CTRL_CLR = PXP_CFA_CTRL_CFA_BYPASS_MASK;
2549 }
2550 else
2551 {
2552 base->CFA_CTRL_SET = PXP_CFA_CTRL_CFA_BYPASS_MASK;
2553 }
2554 }
2555 /*! @} */
2556
2557 /*!
2558 * @name Histogram engine
2559 * @{
2560 */
2561 /*!
2562 * @brief Configures histogram engine.
2563 *
2564 * @param base PXP peripheral base address.
2565 * @param num instance number.
2566 * @param config pointer to the configuration structure.
2567 * @retval kStatus_Success Successfully configured the engine.
2568 * @retval kStatus_InvalidArgument Invalid argument.
2569 */
2570 status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config);
2571
2572 /*!
2573 * @brief Enables/disables the histogram engine.
2574 *
2575 * @param base PXP peripheral base address.
2576 * @param num instance number.
2577 * @param enable true to enable, false to disable.
2578 */
PXP_EnableHistogram(PXP_Type * base,uint8_t num,bool enable)2579 static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable)
2580 {
2581 switch (num)
2582 {
2583 case 0:
2584 base->HIST_A_CTRL =
2585 (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable);
2586 break;
2587
2588 case 1:
2589 base->HIST_B_CTRL =
2590 (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable);
2591 break;
2592
2593 default:
2594 /* Only 2 instances are supported per fetch engine. */
2595 assert(false);
2596 break;
2597 }
2598 }
2599
2600 /*!
2601 * @brief Gets the results of histogram mask operation.
2602 *
2603 * @param base PXP peripheral base address.
2604 * @param num instance number.
2605 * @param result pointer to the result structure.
2606 */
2607 void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result);
2608
2609 /*!
2610 * @brief Gets the PXP Histogram operation result
2611 *
2612 * @param base PXP peripheral base address.
2613 * @param num instance number.
2614 * @return bit map of the match result in @ref _pxp_histgram_flags ORed together
2615 */
PXP_GetHistogramMatchResult(PXP_Type * base,uint8_t num)2616 static inline uint8_t PXP_GetHistogramMatchResult(PXP_Type *base, uint8_t num)
2617 {
2618 uint8_t result = 0U;
2619 switch (num)
2620 {
2621 case 0:
2622 result = (uint8_t)((base->HIST_A_CTRL & PXP_HIST_A_CTRL_STATUS_MASK) >> PXP_HIST_A_CTRL_STATUS_SHIFT);
2623 break;
2624
2625 case 1:
2626 result = (uint8_t)((base->HIST_B_CTRL & PXP_HIST_B_CTRL_STATUS_MASK) >> PXP_HIST_B_CTRL_STATUS_SHIFT);
2627 break;
2628
2629 default:
2630 /* Only 2 histogram instances are supported. */
2631 assert(false);
2632 break;
2633 }
2634
2635 return result;
2636 }
2637
2638 /*!
2639 * @brief Clears the current histogram operation result.
2640 *
2641 * Clears the current histogram operation result, including mask operation result and from 2-level to 32-level match
2642 * result.
2643 *
2644 * @param base PXP peripheral base address.
2645 * @param num instance number.
2646 */
PXP_ClearHistogramResult(PXP_Type * base,uint8_t num)2647 static inline void PXP_ClearHistogramResult(PXP_Type *base, uint8_t num)
2648 {
2649 switch (num)
2650 {
2651 case 0:
2652 base->HIST_A_CTRL |= PXP_HIST_A_CTRL_CLEAR_MASK;
2653 break;
2654
2655 case 1:
2656 base->HIST_B_CTRL |= PXP_HIST_B_CTRL_CLEAR_MASK;
2657 break;
2658
2659 default:
2660 /* Only 2 histogram instances are supported. */
2661 assert(false);
2662 break;
2663 }
2664 }
2665
2666 /*!
2667 * @brief Gets the results of histogram mask operation.
2668 *
2669 * @param base PXP peripheral base address.
2670 * @param num instance number.
2671 * @param width the width of the updated block
2672 * @param height the height of the updated block
2673 */
PXP_SetHistogramSize(PXP_Type * base,uint8_t num,uint16_t width,uint16_t height)2674 static inline void PXP_SetHistogramSize(PXP_Type *base, uint8_t num, uint16_t width, uint16_t height)
2675 {
2676 switch (num)
2677 {
2678 case 0:
2679 base->HIST_A_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
2680 break;
2681
2682 case 1:
2683 base->HIST_B_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
2684 break;
2685
2686 default:
2687 /* Only 2 histogram instances are supported. */
2688 assert(false);
2689 break;
2690 }
2691 }
2692 /*! @} */
2693
2694 /*!
2695 * @name WFE engine
2696 * @{
2697 */
2698
2699 /*!
2700 * @brief Initializes the WFE-A engine for waveform process.
2701 *
2702 * @param base PXP peripheral base address.
2703 * @param ditherHandshake true to enable handshake mode with upstream dither store engine.
2704 */
2705 void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake);
2706
2707 /*!
2708 * @brief Enables/disables hanshake mode with upstream dither engine.
2709 *
2710 * @param base PXP peripheral base address.
2711 * @param enable true to enable handshake mode with upstream dither store engine.
2712 */
PXP_WfeaEnableDitherHandshake(PXP_Type * base,bool enable)2713 static inline void PXP_WfeaEnableDitherHandshake(PXP_Type *base, bool enable)
2714 {
2715 if (enable)
2716 {
2717 base->WFA_FETCH_CTRL |= PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
2718 }
2719 else
2720 {
2721 base->WFA_FETCH_CTRL &= ~PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
2722 }
2723 }
2724
2725 /*!
2726 * @brief Configure the WFE-A engine
2727 *
2728 * @param base PXP peripheral base address.
2729 * @param config pointer to the configuration structure.
2730 */
2731 void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config);
2732
2733 /*!
2734 * @brief Sets the LUT usage status for waveform engine.
2735 *
2736 * If any EPDC LUT(s) has been occupied, use this API to set its usage for PXP WFE-A.
2737 *
2738 * @param base PXP base pointer
2739 * @param lutStatus the status mask of the LUT(s) to be set, can be a single flag or several flags up to all 64 LUTs.
2740 * If user wants to set LUT17 usage, set bit 17 in the lutStatus.
2741 */
PXP_SetLutUsage(PXP_Type * base,uint64_t lutStatus)2742 static inline void PXP_SetLutUsage(PXP_Type *base, uint64_t lutStatus)
2743 {
2744 base->WFE_A_STG1_8X1_OUT0_0 |= (uint32_t)lutStatus;
2745 base->WFE_A_STG1_8X1_OUT0_1 |= (uint32_t)(lutStatus >> 32U);
2746 }
2747
2748 /*!
2749 * @brief Clears the LUT usage status for waveform engine.
2750 *
2751 * If any EPDC LUT(s) has finished processing and is(are) free, use this API to clear its usage for PXP WFE-A.
2752 *
2753 * @param base PXP base pointer
2754 * @param lutStatus the status mask of the LUT(s) to be cleared, can be a single flag or several flags up to all 64
2755 * LUTs. If user wants to clear LUT17, set bit 17.
2756 */
PXP_ClearLutUsage(PXP_Type * base,uint64_t lutStatus)2757 static inline void PXP_ClearLutUsage(PXP_Type *base, uint64_t lutStatus)
2758 {
2759 base->WFE_A_STG1_8X1_OUT0_0 &= ~(uint32_t)lutStatus;
2760 base->WFE_A_STG1_8X1_OUT0_1 &= ~(uint32_t)(lutStatus >> 32U);
2761 }
2762
2763 /*!
2764 * @brief Gets the occupied LUT list.
2765 *
2766 * @param base PXP base pointer
2767 * @return lutStatus the status mask of the LUT(s) that is(are) occupied
2768 */
PXP_GetLutUsage(PXP_Type * base)2769 static inline uint64_t PXP_GetLutUsage(PXP_Type *base)
2770 {
2771 return ((uint64_t)base->WFE_A_STG1_8X1_OUT0_0 | (uint64_t)base->WFE_A_STG1_8X1_OUT0_1 << 32U);
2772 }
2773
2774 /*! @} */
2775
2776 #endif /* FSL_FEATURE_PXP_V3 */
2777
2778 #if defined(__cplusplus)
2779 }
2780 #endif
2781
2782 /*! @}*/
2783
2784 #endif /* FSL_PXP_H_ */
2785
