1 /* 2 * Copyright (c) 2021 ARM Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 18 /** 19 * \file systimer_armv8-m_reg_map.h 20 * 21 * \brief Register map for Armv8-M System Timer 22 */ 23 24 #ifndef __SYSTIMER_ARMV8_M_REG_MAP_H__ 25 #define __SYSTIMER_ARMV8_M_REG_MAP_H__ 26 27 #include <stdint.h> 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /** 34 * \brief CNTBase Register map structure 35 */ 36 struct cnt_base_reg_map_t { 37 volatile const uint32_t cntpct_low; 38 /*!< Offset: 0x000 (RO) Current Physical Counter Value [31:0] */ 39 volatile const uint32_t cntpct_high; 40 /*!< Offset: 0x004 (RO) Current Physical Counter Value [63:32] */ 41 volatile const uint32_t reserved0[2]; 42 /*!< Offset: 0x008-0x0C Reserved */ 43 volatile uint32_t cntfrq; 44 /*!< Offset: 0x010 (R/W) Counter Frequency register in Hz */ 45 volatile const uint32_t reserved1[3]; 46 /*!< Offset: 0x014-0x01C Reserved */ 47 volatile uint32_t cntp_cval_low; 48 /*!< Offset: 0x020 (R/W) Timer Compare Value register [31:0] */ 49 volatile uint32_t cntp_cval_high; 50 /*!< Offset: 0x024 (R/W) Timer Compare Value register [63:32] */ 51 volatile uint32_t cntp_tval; 52 /*!< Offset: 0x028 (R/W) Timer Value register */ 53 volatile uint32_t cntp_ctl; 54 /*!< Offset: 0x02C (R/W) Timer Control register */ 55 volatile const uint32_t reserved2[4]; 56 /*!< Offset: 0x030-0x03C Reserved */ 57 volatile const uint32_t cntp_aival_low; 58 /*!< Offset: 0x040 (RO) Auto Increment Value register [31:0]*/ 59 volatile const uint32_t cntp_aival_high; 60 /*!< Offset: 0x044 (RO) Auto Increment Value register [63:32]*/ 61 volatile uint32_t cntp_aival_reload; 62 /*!< Offset: 0x048 (R/W) Auto Increment Value Reload register [63:32]*/ 63 volatile uint32_t cntp_aival_ctl; 64 /*!< Offset: 0x04C (R/W) Auto Increment Control register */ 65 volatile const uint32_t cntp_cfg; 66 /*!< Offset: 0x050 (RO) Timer Configuration register */ 67 volatile const uint32_t reserved3[991]; 68 /*!< Offset: 0x054-0xFCC Reserved */ 69 volatile const uint32_t cntp_pid4; 70 /*!< Offset: 0xFD0 (RO) Peripheral ID Register */ 71 volatile const uint32_t reserved4[3]; 72 /*!< Offset: 0xFD4-0xFDC Reserved (RAZWI) */ 73 volatile const uint32_t cntp_pid0; 74 /*!< Offset: 0xFE0 (RO) Peripheral ID Register */ 75 volatile const uint32_t cntp_pid1; 76 /*!< Offset: 0xFE4 (RO) Peripheral ID Register */ 77 volatile const uint32_t cntp_pid2; 78 /*!< Offset: 0xFE8 (RO) Peripheral ID Register */ 79 volatile const uint32_t cntp_pid3; 80 /*!< Offset: 0xFEC (RO) Peripheral ID Register */ 81 volatile const uint32_t cntp_cid0; 82 /*!< Offset: 0xFF0 (RO) Component ID Register */ 83 volatile const uint32_t cntp_cid1; 84 /*!< Offset: 0xFF4 (RO) Component ID Register */ 85 volatile const uint32_t cntp_cid2; 86 /*!< Offset: 0xFF8 (RO) Component ID Register */ 87 volatile const uint32_t cntp_cid3; 88 /*!< Offset: 0xFFC (RO) Component ID Register */ 89 }; 90 91 #ifdef __cplusplus 92 } 93 #endif 94 95 #endif /* __SYSTIMER_ARMV8_M_REG_MAP_H__ */ 96
