1 /***************************************************************************//**
2 * @file em_cmu_fpga.h
3 * @brief Clock management unit (CMU) API for FPGAs
4 * @version 5.3.5
5 *******************************************************************************
6 * # License
7 * <b>Copyright 2018 Silicon Laboratories, Inc. www.silabs.com</b>
8 *******************************************************************************
9 *
10 * Permission is granted to anyone to use this software for any purpose,
11 * including commercial applications, and to alter it and redistribute it
12 * freely, subject to the following restrictions:
13 *
14 * 1. The origin of this software must not be misrepresented; you must not
15 * claim that you wrote the original software.
16 * 2. Altered source versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software.
18 * 3. This notice may not be removed or altered from any source distribution.
19 *
20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
21 * obligation to support this Software. Silicon Labs is providing the
22 * Software "AS IS", with no express or implied warranties of any kind,
23 * including, but not limited to, any implied warranties of merchantability
24 * or fitness for any particular purpose or warranties against infringement
25 * of any proprietary rights of a third party.
26 *
27 * Silicon Labs will not be liable for any consequential, incidental, or
28 * special damages, or any other relief, or for any claim by any third party,
29 * arising from your use of this Software.
30 *
31 ******************************************************************************/
32 #ifndef EM_CMU_FPGA_H
33 #define EM_CMU_FPGA_H
34
35 #include "em_device.h"
36
37 #if defined(CMU_PRESENT) && defined(FPGA)
38
39 #include <stdbool.h>
40 #include "sl_assert.h"
41 #include "em_bus.h"
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /***************************************************************************//**
48 * @addtogroup emlib
49 * @{
50 ******************************************************************************/
51
52 /***************************************************************************//**
53 * @addtogroup CMU
54 * @{
55 ******************************************************************************/
56
57 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL // Lynx value
58 #define VSCALE_EM01_LOW_POWER 1 // Lynx value
59 #define VSCALE_EM01_HIGH_PERFORMANCE 0 // Lynx value
60
61 #if defined(LFRCO_PRECISION_MODE) && LFRCO_PRECISION_MODE
62 #define PLFRCO_PRESENT
63 #endif
64
65 /*******************************************************************************
66 ******************************** ENUMS ************************************
67 ******************************************************************************/
68 /** Clock divisors. These values are valid for prescalers. */
69 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
70 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
71 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
72 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
73 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
74 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
75 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
76 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
77 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
78 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
79 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
80 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
81 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
82 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
83 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
84 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
85
86 /** Clock divider configuration */
87 typedef uint32_t CMU_ClkDiv_TypeDef;
88
89 /** High frequency system RCO bands */
90 typedef enum {
91 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
92 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
93 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
94 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
95 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
96 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
97 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
98 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
99 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
100 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
101 cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
102 cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56MHz RC band */
103 cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64MHz RC band */
104 cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72MHz RC band */
105 cmuHFRCOFreq_UserDefined = 0,
106 } CMU_HFRCOFreq_TypeDef;
107 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
108 #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
109
110 /** HFRCODPLL frequency bands */
111 typedef enum {
112 cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */
113 cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */
114 cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */
115 cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */
116 cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */
117 cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */
118 cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */
119 cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */
120 cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */
121 cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */
122 cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */
123 cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */
124 cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */
125 cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */
126 cmuHFRCODPLLFreq_UserDefined = 0,
127 } CMU_HFRCODPLLFreq_TypeDef;
128
129 /** HFRCODPLL maximum frequency */
130 #define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz
131 /** HFRCODPLL minimum frequency */
132 #define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz
133
134 /** HFRCOEM23 frequency bands */
135 typedef enum {
136 cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */
137 cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */
138 cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */
139 cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */
140 cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */
141 cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */
142 cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */
143 cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */
144 cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */
145 cmuHFRCOEM23Freq_UserDefined = 0,
146 } CMU_HFRCOEM23Freq_TypeDef;
147
148 /** HFRCOEM23 maximum frequency */
149 #define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz
150 /** HFRCOEM23 minimum frequency */
151 #define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz
152
153 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
154 typedef enum {
155 /*******************/
156 /* Clock branches */
157 /*******************/
158
159 cmuClock_SYSCLK, /**< System clock. */
160 cmuClock_HCLK, /**< Core and AHB bus interface clock. */
161 cmuClock_EXPCLK, /**< Export clock. */
162 cmuClock_PCLK, /**< Peripheral APB bus interface clock. */
163 cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */
164 cmuClock_IADCCLK, /**< IADC clock. */
165 cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */
166 #if defined(_CMU_EM01GRPBCLKCTRL_MASK)
167 cmuClock_EM01GRPBCLK, /**< EM01GRPB clock. */
168 #endif
169 cmuClock_EM01GRPCCLK, /**< EM01GRPC clock. */
170 cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */
171 cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */
172 cmuClock_LFRCO, /**< LFRCO clock. */
173 cmuClock_ULFRCO, /**< ULFRCO clock. */
174 cmuClock_LFXO, /**< LFXO clock. */
175 cmuClock_HFRCO0, /**< HFRCO0 clock. */
176 cmuClock_HFRCOEM23, /**< HFRCOEM23 clock. */
177 cmuClock_WDOG0CLK, /**< WDOG0 clock. */
178 #if WDOG_COUNT > 1
179 cmuClock_WDOG1CLK, /**< WDOG1 clock. */
180 #endif
181 cmuClock_DPLLREFCLK, /**< DPLL reference clock. */
182 #if defined(_CMU_TRACECLKCTRL_MASK)
183 cmuClock_TRACECLK, /**< Debug trace clock. */
184 #endif
185 cmuClock_RTCCCLK, /**< RTCC clock. */
186 #if defined(LESENSE_PRESENT)
187 cmuClock_LESENSEHFCLK,
188 cmuClock_LESENSECLK,
189 #endif
190
191 /*********************/
192 /* Peripheral clocks */
193 /*********************/
194
195 cmuClock_CORE, /**< Cortex-M33 core clock. */
196 cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */
197 cmuClock_ACMP0, /**< ACMP0 clock. */
198 cmuClock_ACMP1, /**< ACMP1 clock. */
199 cmuClock_BURTC, /**< BURTC clock. */
200 #if defined(ETAMPDET_PRESENT)
201 cmuClock_ETAMPDET, /**< ETAMPDET clock. */
202 #endif
203 cmuClock_GPCRC, /**< GPCRC clock. */
204 cmuClock_GPIO, /**< GPIO clock. */
205 cmuClock_I2C0, /**< I2C0 clock. */
206 cmuClock_I2C1, /**< I2C1 clock. */
207 cmuClock_SYSCFG, /**< SYSCFG clock. */
208 cmuClock_IADC0, /**< IADC clock. */
209 cmuClock_LDMA, /**< LDMA clock. */
210 cmuClock_LDMAXBAR, /**< LDMAXBAR clock. */
211 cmuClock_LETIMER0, /**< LETIMER clock. */
212 cmuClock_PRS, /**< PRS clock. */
213 cmuClock_RTCC, /**< RTCC clock. */
214 cmuClock_SYSRTC, /**< SYSRTC clock. */
215 cmuClock_TIMER0, /**< TIMER0 clock. */
216 cmuClock_TIMER1, /**< TIMER1 clock. */
217 cmuClock_TIMER2, /**< TIMER2 clock. */
218 cmuClock_TIMER3, /**< TIMER3 clock. */
219 cmuClock_TIMER4, /**< TIMER4 clock. */
220 cmuClock_TIMER5, /**< TIMER5 clock. */
221 cmuClock_TIMER6, /**< TIMER6 clock. */
222 cmuClock_TIMER7, /**< TIMER7 clock. */
223 cmuClock_BURAM,
224 cmuClock_LESENSE,
225 cmuClock_LESENSEHF, /**< LESENSEHF clock. */
226 #if defined(USART0)
227 cmuClock_USART0, /**< USART0 clock. */
228 #endif
229 #if defined(USART1)
230 cmuClock_USART1, /**< USART1 clock. */
231 #endif
232 #if defined(USART2)
233 cmuClock_USART2, /**< USART2 clock. */
234 #endif
235 cmuClock_WDOG0, /**< WDOG0 clock. */
236 #if defined(WDOG1)
237 cmuClock_WDOG1, /**< WDOG1 clock. */
238 #endif
239 cmuClock_PDM, /**< PDM clock. */
240 cmuClock_PDMREF, /**< PDM reference clock. */
241 cmuClock_LFA,
242 cmuClock_LCDpre,
243 cmuClock_LCD,
244 #if defined(EUART0)
245 cmuClock_EUART0, /**< EUART0 clock. */
246 #endif
247 #if defined(EUSART0)
248 cmuClock_EUSART0, /**< EUSART0 clock. */
249 cmuClock_EUSART0CLK,
250 #endif
251 #if defined(EUSART1)
252 cmuClock_EUSART1, /**< EUSART1 clock. */
253 #endif
254 #if defined(EUSART2)
255 cmuClock_EUSART2, /**< EUSART2 clock. */
256 #endif
257 #if defined(EUSART3)
258 cmuClock_EUSART3, /**< EUSART3 clock. */
259 #endif
260 #if defined(EUSART4)
261 cmuClock_EUSART4, /**< EUSART4 clock. */
262 #endif
263 cmuClock_PCNT0,
264 cmuClock_KEYSCAN,
265 cmuClock_HFPER,
266 cmuClock_MSC,
267 cmuClock_DMEM,
268 cmuClock_SEMAILBOX,
269 cmuClock_SMU,
270 cmuClock_VDAC0
271 } CMU_Clock_TypeDef;
272
273 /** OCELOT TEMPORARY DEFINE. */
274 #define cmuClock_CORELE cmuClock_CORE
275
276 /** Oscillator types. */
277 typedef enum {
278 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
279 #if defined(LFRCO_PRESENT)
280 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
281 #endif
282 #if defined(PLFRCO_PRESENT)
283 cmuOsc_PLFRCO, /**< Precision Low frequency RC oscillator. */
284 #endif
285 cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
286 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
287 cmuOsc_HFRCO, /**< High frequency RC oscillator. */
288 cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
289 #if defined(HFRCOEM23_PRESENT)
290 cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
291 #endif
292 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
293 } CMU_Osc_TypeDef;
294
295 /** Selectable clock sources. */
296 typedef enum {
297 cmuSelect_Error, /**< Usage error. */
298 cmuSelect_Disabled, /**< Clock selector disabled. */
299 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
300 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
301 cmuSelect_HFRCO, /**< High frequency RC. */
302 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
303 #if defined(HFRCOEM23_PRESENT)
304 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
305 #endif
306 cmuSelect_CLKIN0, /**< External clock input. */
307 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
308 #if defined(LFRCO_PRESENT)
309 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
310 #endif
311 #if defined(PLFRCO_PRESENT)
312 cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */
313 #endif
314 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
315 cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */
316 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
317 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
318 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
319 cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */
320 cmuSelect_EM23GRPACLK, /**< EM23GRPACLK clock.*/
321 cmuSelect_EXPCLK, /**< Pin export clock. */
322 cmuSelect_PRS /**< PRS input as clock. */
323 } CMU_Select_TypeDef;
324
325 /** DPLL reference clock edge detect selector. */
326 typedef enum {
327 cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */
328 cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */
329 } CMU_DPLLEdgeSel_TypeDef;
330
331 /** DPLL lock mode selector. */
332 typedef enum {
333 cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */
334 cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */
335 } CMU_DPLLLockMode_TypeDef;
336
337 /** LFXO oscillator modes. */
338 typedef enum {
339 cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
340 cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */
341 cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */
342 } CMU_LfxoOscMode_TypeDef;
343
344 /** LFXO start-up timeout delay. */
345 typedef enum {
346 cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */
347 cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */
348 cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */
349 cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */
350 cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */
351 cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */
352 cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */
353 cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */
354 } CMU_LfxoStartupDelay_TypeDef;
355
356 //TODO UPDATE with SYXO new IP.
357 #define SYSXO
358 /** HFXO oscillator modes. */
359 typedef enum {
360 #if defined(SYSXO)
361 cmuHfxoOscMode_Crystal,
362 cmuHfxoOscMode_ExternalSine,
363 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
364 cmuHfxoOscMode_ExternalSinePkDet,
365 #endif
366 #else
367 cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
368 cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */
369 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
370 cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */
371 #endif
372 #endif
373 } CMU_HfxoOscMode_TypeDef;
374
375 /** HFXO core bias LSB change timeout. */
376 typedef enum {
377 #if defined(SYSXO)
378 cmuHfxoCbLsbTimeout_8us, /**< 8 us timeout. */
379 cmuHfxoCbLsbTimeout_20us, /**< 20 us timeout. */
380 cmuHfxoCbLsbTimeout_41us, /**< 41 us timeout. */
381 cmuHfxoCbLsbTimeout_62us, /**< 62 us timeout. */
382 cmuHfxoCbLsbTimeout_83us, /**< 83 us timeout. */
383 cmuHfxoCbLsbTimeout_104us, /**< 104 us timeout. */
384 cmuHfxoCbLsbTimeout_125us, /**< 125 us timeout. */
385 cmuHfxoCbLsbTimeout_166us, /**< 166 us timeout. */
386 cmuHfxoCbLsbTimeout_208us, /**< 208 us timeout. */
387 cmuHfxoCbLsbTimeout_250us, /**< 250 us timeout. */
388 cmuHfxoCbLsbTimeout_333us, /**< 333 us timeout. */
389 cmuHfxoCbLsbTimeout_416us, /**< 416 us timeout. */
390 cmuHfxoCbLsbTimeout_833us, /**< 833 us timeout. */
391 cmuHfxoCbLsbTimeout_1250us, /**< 1250 us timeout. */
392 cmuHfxoCbLsbTimeout_2083us, /**< 2083 us timeout. */
393 cmuHfxoCbLsbTimeout_3750us, /**< 3750 us timeout. */
394 #else
395 cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */
396 cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */
397 cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */
398 cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */
399 cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */
400 cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */
401 cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */
402 cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */
403 cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */
404 cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */
405 cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */
406 cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */
407 cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */
408 cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */
409 cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */
410 cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */
411 #endif
412 } CMU_HfxoCbLsbTimeout_TypeDef;
413
414 /** HFXO steady state timeout. */
415 typedef enum {
416 #if defined(SYSXO)
417 cmuHfxoSteadyStateTimeout_16us, /**< 16 us timeout. */
418 cmuHfxoSteadyStateTimeout_41us, /**< 41 us timeout. */
419 cmuHfxoSteadyStateTimeout_83us, /**< 83 us timeout. */
420 cmuHfxoSteadyStateTimeout_125us, /**< 125 us timeout. */
421 cmuHfxoSteadyStateTimeout_166us, /**< 166 us timeout. */
422 cmuHfxoSteadyStateTimeout_208us, /**< 208 us timeout. */
423 cmuHfxoSteadyStateTimeout_250us, /**< 250 us timeout. */
424 cmuHfxoSteadyStateTimeout_333us, /**< 333 us timeout. */
425 cmuHfxoSteadyStateTimeout_416us, /**< 416 us timeout. */
426 cmuHfxoSteadyStateTimeout_500us, /**< 500 us timeout. */
427 cmuHfxoSteadyStateTimeout_666us, /**< 666 us timeout. */
428 cmuHfxoSteadyStateTimeout_833us, /**< 833 us timeout. */
429 cmuHfxoSteadyStateTimeout_1666us, /**< 1666 us timeout. */
430 cmuHfxoSteadyStateTimeout_2500us, /**< 2500 us timeout. */
431 cmuHfxoSteadyStateTimeout_4166us, /**< 4166 us timeout. */
432 cmuHfxoSteadyStateTimeout_7500us, /**< 7500 us timeout. */
433 #else
434 cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */
435 cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */
436 cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */
437 cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */
438 cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */
439 cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */
440 cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */
441 cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */
442 cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */
443 cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */
444 cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */
445 cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */
446 cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */
447 cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */
448 cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */
449 cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */
450 #endif
451 } CMU_HfxoSteadyStateTimeout_TypeDef;
452
453 /** HFXO core degeneration control. */
454 typedef enum {
455 #if defined(SYSXO)
456 cmuHfxoCoreDegen_None, /**< No core degeneration. */
457 cmuHfxoCoreDegen_33, /**< Core degeneration control 33. */
458 cmuHfxoCoreDegen_50, /**< Core degeneration control 50. */
459 cmuHfxoCoreDegen_100, /**< Core degeneration control 100. */
460 #else
461 cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */
462 cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */
463 cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */
464 cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */
465 #endif
466 } CMU_HfxoCoreDegen_TypeDef;
467
468 /** HFXO XI and XO pin fixed capacitor control. */
469 typedef enum {
470 #if defined(SYSXO)
471 cmuHfxoCtuneFixCap_None, /**< No fixed capacitors. */
472 cmuHfxoCtuneFixCap_Xi, /**< Fixed capacitor on XI pin. */
473 cmuHfxoCtuneFixCap_Xo, /**< Fixed capacitor on XO pin. */
474 cmuHfxoCtuneFixCap_Both, /**< Fixed capacitor on both pins. */
475 #else
476 cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */
477 cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */
478 cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */
479 cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */
480 #endif
481 } CMU_HfxoCtuneFixCap_TypeDef;
482
483 /*******************************************************************************
484 ******************************* STRUCTS ***********************************
485 ******************************************************************************/
486
487 /** LFXO initialization structure. Init values should be obtained from a
488 configuration tool, app. note or xtal data sheet. */
489 typedef struct {
490 uint8_t gain; /**< Startup gain. */
491 uint8_t capTune; /**< Internal capacitance tuning. */
492 CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */
493 CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */
494 bool highAmplitudeEn; /**< High amplitude enable. */
495 bool agcEn; /**< AGC enable. */
496 bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */
497 bool failDetEn; /**< Oscillator failure detection enable. */
498 bool disOnDemand; /**< Disable on-demand requests. */
499 bool forceEn; /**< Force oscillator enable. */
500 bool regLock; /**< Lock register access. */
501 } CMU_LFXOInit_TypeDef;
502
503 /** Default LFXO initialization values for XTAL mode. */
504 #define CMU_LFXOINIT_DEFAULT \
505 { \
506 1, \
507 38, \
508 cmuLfxoStartupDelay_4KCycles, \
509 cmuLfxoOscMode_Crystal, \
510 false, /* highAmplitudeEn */ \
511 true, /* agcEn */ \
512 false, /* failDetEM4WUEn */ \
513 false, /* failDetEn */ \
514 false, /* DisOndemand */ \
515 false, /* ForceEn */ \
516 false /* Lock registers */ \
517 }
518
519 /** HFXO initialization structure. Init values should be obtained from a configuration tool,
520 app note or xtal data sheet */
521
522 typedef struct {
523 CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */
524 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */
525 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */
526 uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */
527 uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */
528 uint8_t coreBiasStartup; /**< Core bias startup current. */
529 uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */
530 CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */
531 CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */
532 uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */
533 uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */
534 uint8_t coreBiasAna; /**< Core bias current. */
535 bool enXiDcBiasAna; /**< Enable XI internal DC bias. */
536 CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */
537 bool forceXo2GndAna; /**< Force XO pin to ground. */
538 bool forceXi2GndAna; /**< Force XI pin to ground. */
539 bool disOnDemand; /**< Disable on-demand requests. */
540 bool forceEn; /**< Force oscillator enable. */
541 bool regLock; /**< Lock register access. */
542 } CMU_HFXOInit_TypeDef;
543
544 /** Default HFXO initialization values for XTAL mode. */
545 #define CMU_HFXOINIT_DEFAULT \
546 { \
547 cmuHfxoCbLsbTimeout_416us, \
548 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
549 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
550 0U, /* ctuneXoStartup */ \
551 0U, /* ctuneXiStartup */ \
552 32U, /* coreBiasStartup */ \
553 32U, /* imCoreBiasStartup */ \
554 cmuHfxoCoreDegen_None, \
555 cmuHfxoCtuneFixCap_Both, \
556 0U, /* _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, ctuneXoAna*/ \
557 0U,/* _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, ctuneXiAna*/ \
558 60U, /* coreBiasAna */ \
559 false, /* enXiDcBiasAna */ \
560 cmuHfxoOscMode_Crystal, \
561 false, /* forceXo2GndAna */ \
562 false, /* forceXi2GndAna */ \
563 false, /* DisOndemand */ \
564 false, /* ForceEn */ \
565 false /* Lock registers */ \
566 }
567
568 /** Default HFXO initialization values for external sine mode. */
569 #define CMU_HFXOINIT_EXTERNAL_SINE \
570 { \
571 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
572 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
573 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
574 0U, /* ctuneXoStartup */ \
575 0U, /* ctuneXiStartup */ \
576 0U, /* coreBiasStartup */ \
577 0U, /* imCoreBiasStartup */ \
578 cmuHfxoCoreDegen_None, \
579 cmuHfxoCtuneFixCap_None, \
580 0U, /* ctuneXoAna */ \
581 0U, /* ctuneXiAna */ \
582 0U, /* coreBiasAna */ \
583 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
584 cmuHfxoOscMode_ExternalSine, \
585 false, /* forceXo2GndAna */ \
586 false, /* forceXi2GndAna */ \
587 false, /* DisOndemand */ \
588 false, /* ForceEn */ \
589 false /* Lock registers */ \
590 }
591
592 /** Default HFXO initialization values for external sine mode with peak detector. */
593 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
594 { \
595 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
596 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
597 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
598 0U, /* ctuneXoStartup */ \
599 0U, /* ctuneXiStartup */ \
600 0U, /* coreBiasStartup */ \
601 0U, /* imCoreBiasStartup */ \
602 cmuHfxoCoreDegen_None, \
603 cmuHfxoCtuneFixCap_None, \
604 0U, /* ctuneXoAna */ \
605 0U, /* ctuneXiAna */ \
606 0U, /* coreBiasAna */ \
607 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
608 cmuHfxoOscMode_ExternalSinePkDet, \
609 false, /* forceXo2GndAna */ \
610 false, /* forceXi2GndAna */ \
611 false, /* DisOndemand */ \
612 false, /* ForceEn */ \
613 false /* Lock registers */ \
614 }
615
616 #define CMU_HFXOINIT_EXTERNAL_CLOCK CMU_HFXOINIT_DEFAULT
617
618 /*******************************************************************************
619 ***************************** PROTOTYPES **********************************
620 ******************************************************************************/
621 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
622 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
623 CMU_Osc_TypeDef upSel);
624 uint32_t CMU_CalibrateCountGet(void);
625 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
626 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
627 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
628 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
629 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
630 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
631 void CMU_FreezeEnable(bool enable);
632 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
633 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
634 CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void);
635 void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq);
636 uint32_t CMU_HFRCOStartupDelayGet(void);
637 void CMU_HFRCOStartupDelaySet(uint32_t delay);
638 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
639 void CMU_HFXOCTuneDeltaSet(int32_t delta);
640 int32_t CMU_HFXOCTuneDeltaGet(void);
641 uint32_t CMU_LCDClkFDIVGet(void);
642 void CMU_LCDClkFDIVSet(uint32_t div);
643 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
644
645 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
646 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
647 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
648 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
649 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
650 void CMU_LFXOPrecisionSet(uint16_t precision);
651 bool CMU_PCNTClockExternalGet(unsigned int instance);
652 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
653
CMU_CalibrateCont(bool enable)654 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
655 {
656 (void) enable;
657 }
658
CMU_CalibrateStart(void)659 __STATIC_INLINE void CMU_CalibrateStart(void)
660 {
661 }
662
CMU_CalibrateStop(void)663 __STATIC_INLINE void CMU_CalibrateStop(void)
664 {
665 }
666
CMU_DivToLog2(CMU_ClkDiv_TypeDef div)667 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
668 {
669 uint32_t log2;
670
671 /* Fixed 2^n prescalers take argument of 32768 or less. */
672 EFM_ASSERT((div > 0U) && (div <= 32768U));
673
674 /* Count leading zeroes and "reverse" result */
675 log2 = (31U - __CLZ(div));
676
677 return log2;
678 }
679
CMU_IntClear(uint32_t flags)680 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
681 {
682 (void) flags;
683 }
684
CMU_IntDisable(uint32_t flags)685 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
686 {
687 (void) flags;
688 }
689
CMU_IntEnable(uint32_t flags)690 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
691 {
692 (void) flags;
693 }
694
CMU_IntGet(void)695 __STATIC_INLINE uint32_t CMU_IntGet(void)
696 {
697 return 0;
698 }
699
CMU_IntGetEnabled(void)700 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
701 {
702 return 0;
703 }
704
CMU_IntSet(uint32_t flags)705 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
706 {
707 (void) flags;
708 }
CMU_Lock(void)709 __STATIC_INLINE void CMU_Lock(void)
710 {
711 }
CMU_Unlock(void)712 __STATIC_INLINE void CMU_Unlock(void)
713 {
714 }
715
716 #if !defined(_SILICON_LABS_32B_SERIES_0)
717 /***************************************************************************//**
718 * @brief
719 * Convert prescaler dividend to a logarithmic value. It only works for even
720 * numbers equal to 2^n.
721 *
722 * @param[in] presc
723 * An unscaled dividend (dividend = presc + 1).
724 *
725 * @return
726 * Logarithm of 2, as used by fixed 2^n prescalers.
727 ******************************************************************************/
CMU_PrescToLog2(uint32_t presc)728 __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc)
729 {
730 uint32_t log2;
731
732 /* Integer prescalers take argument less than 32768. */
733 EFM_ASSERT(presc < 32768U);
734
735 /* Count leading zeroes and "reverse" result. */
736 log2 = 31UL - __CLZ(presc + (uint32_t) 1);
737
738 /* Check that prescaler is a 2^n number. */
739 EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U));
740
741 return log2;
742 }
743 #endif // !defined(_SILICON_LABS_32B_SERIES_0)
744
745 /** @} (end addtogroup CMU) */
746 /** @} (end addtogroup emlib) */
747
748 #ifdef __cplusplus
749 }
750 #endif
751
752 #endif /* #if defined(CMU_PRESENT) && defined(LYNX_FPGA) */
753 #endif /* EM_CMU_FPGA_H */
754
